CN113778933A - Hardware identification method and device, electronic equipment and computer readable storage medium - Google Patents
Hardware identification method and device, electronic equipment and computer readable storage medium Download PDFInfo
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- CN113778933A CN113778933A CN202111087310.8A CN202111087310A CN113778933A CN 113778933 A CN113778933 A CN 113778933A CN 202111087310 A CN202111087310 A CN 202111087310A CN 113778933 A CN113778933 A CN 113778933A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
- G06F9/5022—Mechanisms to release resources
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Abstract
The invention discloses a hardware identification method, a hardware identification device, electronic equipment and a computer readable storage medium, wherein the method comprises the following steps: when the internal pull-up resistor and the internal pull-down resistor are both in a suspended state, acquiring a first level signal received by the internal port; when the internal pull-up resistor is in a conducting state, a second level signal received by the internal port is obtained; when the internal pull-down resistor is in a conducting state, a third level signal received by the internal port is obtained; and identifying different types of hardware according to the first level signal, the second level signal and the third level signal. The method can increase the number of the hardware types identified by a single IO, thereby releasing IO interface resources.
Description
Technical Field
The embodiment of the invention relates to the technical field of hardware identification, in particular to a hardware identification method, a hardware identification device, electronic equipment and a computer readable storage medium.
Background
In the development process of the terminal equipment, in order to reduce the workload of software development and maintenance, a single set of software needs to be adapted to various different hardware. The type of hardware is usually identified by using an Analog-to-Digital Converter (Analog-to-Digital Converter) or an Input Output (Input Output) interface, or a combination of the two.
In the prior art, when the ADC is used for identification, ADC resources of part of systems are in shortage, so that hardware types cannot be identified by using the ADC, when the IO interface is used for identification, the current single IO interface can only identify two types of hardware, and when more hardware states need to be distinguished, more IO interface resources are occupied.
Disclosure of Invention
The present disclosure provides a hardware identification method, an apparatus, an electronic device, and a computer-readable storage medium, which can increase the number of hardware types identified by a single IO, thereby releasing IO interface resources.
In a first aspect, the present disclosure provides a hardware identification method, which is applied to at least one input/output IO interface, wherein an internal port of the IO interface is electrically connected to a high level through an internal pull-up resistor, and the internal port is also grounded through an internal pull-down resistor;
the method comprises the following steps:
when the internal pull-up resistor and the internal pull-down resistor are both in a suspended state, acquiring a first level signal received by the internal port;
when the internal pull-up resistor is in a conducting state, a second level signal received by the internal port is obtained;
when the internal pull-down resistor is in a conducting state, a third level signal received by the internal port is obtained;
and identifying different types of hardware according to the first level signal, the second level signal and the third level signal.
Optionally, the identifying different types of hardware according to the first level signal, the second level signal, and the third level signal includes:
if the first level signal, the second level signal and the third level signal are all low level signals, identifying first type hardware;
if the first level signal and the third level signal are both low level signals and the second level signal is a high level signal, identifying second type hardware;
if the first level signal and the second level signal are both high level signals and the third level signal is a low level signal, identifying a third type of hardware;
and if the first level signal, the second level signal and the third level signal are all high level signals, identifying fourth type hardware.
Optionally, before acquiring the first level signal received by the internal port, the method further includes:
determining a target resistance value range of the pull-up resistor and a target resistance value range of the pull-down resistor according to the resistance value of the internal pull-up resistor, the resistance value of the internal pull-down resistor and a level threshold range;
determining a target resistance value of the pull-up resistor and a target resistance value of the pull-down resistor from the target resistance value range;
and setting the pull-up resistor and/or the pull-down resistor with corresponding resistance values for different types of hardware based on the corresponding relation between the target resistance value of the pull-up resistor and/or the target value of the pull-down resistor and the type of the hardware.
Optionally, the determining the target resistance value range of the pull-up resistor and the target resistance value range of the pull-down resistor according to the resistance value of the internal pull-up resistor, the resistance value of the internal pull-down resistor and the level threshold range includes:
determining a first target resistance range of the pull-down resistor according to the resistance value of the internal pull-up resistor and a high level threshold range;
determining a second target resistance range of the pull-down resistor according to the resistance value of the internal pull-up resistor and the low level threshold range;
determining a third target resistance range of the pull-up resistor according to the resistance value of the internal pull-down resistor and the high level threshold range;
and determining a fourth target resistance range of the pull-up resistor according to the resistance value of the internal pull-down resistor and the low level threshold range.
Optionally, before determining the first target resistance range of the pull-down resistor according to the resistance value of the internal pull-up resistor and the high level threshold range, the method further includes:
determining the high level threshold range according to a high level judgment coefficient, a system power supply and a voltage parameter;
and determining the low level threshold range according to the low level judgment coefficient, the system power supply and the voltage parameter.
Optionally, the determining the high level threshold range according to the high level judgment coefficient, the system power supply, and the voltage parameter includes:
determining a first high level threshold value according to the product of the high level judgment coefficient and the system power supply;
determining a second high level threshold based on a sum of the system power supply and the voltage parameter;
and determining a threshold range which is greater than or equal to the first high level threshold value and less than or equal to the second high level threshold value as the high level threshold range.
Optionally, the determining the low level threshold range according to the low level determination coefficient, the system power supply, and the voltage parameter includes:
determining a first low level threshold according to a negative value of the voltage parameter;
determining a second low level threshold value according to the product of the low level judgment coefficient and the system power supply;
determining a threshold range greater than or equal to the first low level threshold and less than or equal to the second low level threshold as the low level threshold range
In a second aspect, the present disclosure provides a hardware identification device, which is applied to at least one input/output IO interface, wherein an internal port of the IO interface is electrically connected to a high level through an internal pull-up resistor, and the internal port is also grounded through an internal pull-down resistor;
the identification device comprises:
the acquisition module is used for acquiring a first level signal received by the internal port when the internal pull-up resistor and the internal pull-down resistor are both in a suspended state; when the internal pull-up resistor is in a conducting state, a second level signal received by the internal port is obtained; when the internal pull-down resistor is in a conducting state, a third level signal received by the internal port is obtained;
an identification module for identifying different types of hardware according to the first level signal, the second level signal and the third level signal
In a third aspect, the present disclosure provides an electronic device comprising a memory and a processor, the memory storing a computer program, the processor implementing the steps of any one of the methods provided in the first aspect when executing the computer program.
In a fourth aspect, the present disclosure provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of any one of the methods provided by the first aspect.
According to the technical scheme provided by the disclosure, when both an internal pull-up resistor and an internal pull-down resistor are in a suspended state, a first level signal received by an internal port is obtained; when the internal pull-up resistor is in a conducting state, a second level signal received by the internal port is obtained; when the internal pull-down resistor is in a conducting state, a third level signal received by the internal port is obtained; according to the first level signal, the second level signal and the third level signal, different types of hardware are identified, each level signal can be a high level signal or a low level signal, eight possible results are provided for the three level signals, and different types of hardware are provided for each type of possible hardware, so that a single IO can identify various types of hardware, the number of hardware types identified by the single IO can be increased, and IO interface resources can be released.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present disclosure, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of an application scenario provided in the present disclosure;
FIG. 2 is a schematic flow chart of a hardware identification method according to the present disclosure;
FIG. 3 is a schematic flow chart of another hardware identification method provided by the present disclosure;
FIG. 4 is a schematic flow chart diagram illustrating another hardware identification method provided by the present disclosure;
FIG. 5 is a schematic flow chart diagram illustrating another hardware identification method provided by the present disclosure;
FIG. 6 is a schematic flow chart diagram illustrating another hardware identification method provided by the present disclosure;
FIG. 7 is a schematic flow chart diagram illustrating another hardware identification method provided by the present disclosure;
FIG. 8 is a schematic flow chart diagram illustrating another hardware identification method provided by the present disclosure;
fig. 9 is a schematic structural diagram of a hardware identification device provided in the present disclosure;
fig. 10 is a schematic diagram of an internal structure of a computer device provided by the present disclosure.
Detailed Description
In order that the above objects, features and advantages of the present disclosure may be more clearly understood, aspects of the present disclosure will be further described below. It should be noted that the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced in other ways than those described herein; it is to be understood that the embodiments disclosed in the specification are only a few embodiments of the present disclosure, and not all embodiments.
Fig. 1 is a schematic structural diagram of an application scenario provided by the present disclosure, as shown in fig. 1, including: an IO interface 10, the IO interface 10 internally includes: internal port a, internal pull-up resistor Ru and internal pull-down resistor Rd.
The internal port a is electrically connected to the high level Vcc through an internal pull-up resistor Ru, and the internal port a is also grounded through an internal pull-down resistor Rd.
The software is electrically connected with the hardware through an IO interface, the port of the IO interface connected with the software is an internal port A, and the port of the IO interface electrically connected with the hardware is an external port B. The internal port A is electrically connected with a high level Vcc through an internal pull-up resistor Ru and a first switch K1 in sequence, and the internal port A is grounded through an internal pull-down resistor Rd and a second switch K2 in sequence. The states of the internal pull-up resistor Ru and the internal pull-down resistor Rd can be changed by controlling the on-off states of the first switch K1 and the second switch K2, for example, when the first switch K1 is turned off, the internal pull-up resistor Ru is in a floating state, when the first switch K1 is turned on, the internal port a and the high level Vcc are turned on, and the internal pull-up resistor Ru is in a conducting state; when the second switch K2 is turned off, the internal pull-down resistor Rd is in a floating state, and when the second switch K2 is turned on, the internal port a is connected to ground, and the internal pull-down resistor Rd is in a conducting state.
And after the hardware is electrically connected with the IO interface, as shown in FIG. 1, the external port B is electrically connected with a high-level Vcc through a pull-up resistor R1, and/or the external port B is grounded through a pull-down resistor R2.
It should be noted that fig. 1 only exemplarily shows that the peripheral circuit of the hardware is provided with a pull-up resistor R1 and a pull-down resistor R2, and in other embodiments, the peripheral circuit may also be provided with a pull-up resistor R1 or a pull-down resistor R2.
It should be further noted that fig. 1 only exemplarily shows an application scenario including one IO interface, and in other application scenarios, the application scenario may further include a plurality of IO interfaces, and a structure of each IO interface is the same as that shown in fig. 1.
Fig. 2 is a schematic flowchart of a hardware identification method provided by the present disclosure, where the embodiment shown in fig. 2 is applied to the IO interface shown in fig. 1, and as shown in fig. 2, the method includes the specific steps of:
s101, when the internal pull-up resistor and the internal pull-down resistor are both in a suspended state, a first level signal received by the internal port is obtained.
For example, as shown in fig. 1, the first switch K1 and the second switch K2 are controlled to be turned off, so that the internal pull-up resistor Ru is disconnected from the high level Vcc and the internal pull-down resistor Rd is disconnected from the ground, i.e., the internal pull-up resistor Ru and the internal pull-down resistor Rd are both in a floating state.
Under the condition that both the internal pull-up resistor Ru and the internal pull-down resistor Rd are in a floating state, if the peripheral circuit of the hardware is only provided with the pull-up resistor R1, the voltage at the internal port a is pulled to a high level because the pull-up resistor R1 is conducted with the high level Vcc, that is, the first level signal received by the internal port a is a high level signal. If the peripheral circuit of the hardware is only provided with the pull-down resistor R2, since the pull-down resistor R2 is grounded, the voltage at the internal port a is pulled to a low level, that is, the first level signal received by the internal port a is a low level signal.
And S103, acquiring a second level signal received by the internal port when the internal pull-up resistor is in a conducting state.
For example, as shown in fig. 1, the first switch K1 is turned on and the second switch K2 is turned off, so that the internal pull-up resistor Ru is turned on with the high level Vcc and the internal pull-down resistor Rd is turned off with the ground, that is, the internal pull-up resistor Ru is in a conducting state and the internal pull-down resistor Rd is in a floating state.
If the peripheral circuit of the hardware is only provided with the pull-up resistor R1, at this time, the pull-up resistor R1 and the internal pull-up resistor Ru are both turned on with the high level Vcc, the voltage at the internal port a is pulled up to the high level, that is, the second level signal received by the internal port a is a high level signal. If the peripheral circuit of the hardware is only provided with the pull-down resistor R2, at this time, the high level signal is released to ground through the internal pull-up resistor Ru and the pull-down resistor R2 in sequence, and the voltage at the internal port a depends on the resistance of the pull-down resistor R2 and the resistance of the internal pull-up resistor Ru, that is, the second level signal received by the internal port a may be a low level signal or a high level signal.
And S105, when the internal pull-down resistor is in a conducting state, acquiring a third level signal received by the internal port.
For example, as shown in fig. 1, the first switch K1 is turned off and the second switch K2 is turned on, so that the internal pull-up resistor Ru is turned off from the high level Vcc and the internal pull-down resistor Rd is turned on from ground, that is, the internal pull-up resistor Ru is in a floating state and the internal pull-down resistor Rd is in a conducting state.
If the internal pull-up resistor Ru is in a floating state and the internal pull-down resistor Rd is in a conducting state, and if the peripheral circuit of the hardware is only provided with the pull-up resistor R1, at this time, a high level signal is released to the ground through the pull-up resistor R1 and the internal pull-down resistor Rd in sequence, the voltage at the internal port a depends on the resistance value of the pull-up resistor R1 and the resistance value of the internal pull-down resistor Rd, that is, the third level signal received by the internal port a may be a low level signal or a high level signal. If the peripheral circuit of the hardware is only provided with the pull-down resistor R2, at this time, the pull-down resistor R2 and the internal pull-down resistor Rd are both grounded, and the voltage at the internal port a is pulled to a low level, that is, the third level signal received by the internal port a is a low level signal.
And S107, identifying different types of hardware according to the first level signal, the second level signal and the third level signal.
Based on the above analysis, the first level signal, the second level signal, and the third level signal may be low level signals or high level signals, and there are eight possibilities for the result composed of the first level signal, the second level signal, and the third level signal, and eight different results may be identified based on a single IO, each result corresponds to one type of hardware, and obviously, a single IO may identify a plurality of different types of hardware.
In the embodiment, when both the internal pull-up resistor and the internal pull-down resistor are in a suspended state, a first level signal received by the internal port is obtained; when the internal pull-up resistor is in a conducting state, a second level signal received by the internal port is obtained; when the internal pull-down resistor is in a conducting state, a third level signal received by the internal port is obtained; according to the first level signal, the second level signal and the third level signal, different types of hardware are identified, each level signal can be a high level signal or a low level signal, eight possible results are provided for the three level signals, and different types of hardware are provided for each type of possible hardware, so that a single IO can identify various types of hardware, the number of hardware types identified by the single IO can be increased, and IO interface resources can be released.
Fig. 3 is a schematic flowchart of another hardware identification method provided by the present disclosure, and fig. 3 is a detailed description of a possible implementation manner when S107 is executed on the basis of the embodiment shown in fig. 2, as follows:
s1071, if the first level signal, the second level signal and the third level signal are all low level signals, identifying a first type of hardware.
And if the first level signal is a low level signal, determining that a pull-down resistor or a pull-down resistor and a pull-up resistor are arranged in a peripheral circuit of the hardware, and if the third level signal is a low level signal, determining that a pull-down circuit is arranged in the peripheral circuit. And if the second level signal is a low level signal, determining that the resistance value of the pull-down resistor meets the condition of the low level signal. Therefore, the pull-down resistor meeting the low-level signal condition is arranged in the peripheral circuit of the hardware of the type, and the hardware of the type is taken as the hardware of the first type, so that the hardware of the first type can be identified.
S1072, if the first level signal and the third level signal are both low level signals and the second level signal is a high level signal, identifying a second type of hardware.
And if the first level signal is a low level signal, determining that a pull-down resistor or a pull-down resistor and a pull-up resistor are arranged in a peripheral circuit of the hardware, and if the third level signal is a low level signal, determining that a pull-down resistor is arranged in the peripheral circuit. And if the second level signal is a high level signal, determining that the resistance value of the pull-down resistor meets the condition of the high level signal. Based on this, it can be determined that the peripheral circuit of the hardware of the type is provided with the pull-down resistor meeting the high-level signal condition, and the hardware of the type is taken as the hardware of the second type, so that the hardware of the second type can be identified.
S1073, if the first level signal and the second level signal are both high level signals and the third level signal is a low level signal, identifying a third type of hardware.
And if the first level signal is a high level signal, determining that a pull-up resistor or a pull-down resistor and a pull-up resistor are arranged in a peripheral circuit of the hardware, and if the second level signal is a high level signal, determining that a pull-up resistor is arranged in the peripheral circuit. And if the third level signal is a low level signal, determining that the resistance value of the pull-up resistor meets the condition of the low level signal. Based on this, it can be determined that the peripheral circuit of the hardware of the type is provided with the pull-up resistor satisfying the low level signal condition, and the hardware of the type is taken as the hardware of the third type, so that the hardware of the third type can be identified.
S1074, if the first level signal, the second level signal and the third level signal are all high level signals, identifying fourth type hardware.
And if the first level signal is a high level signal, determining that a pull-up resistor or a pull-down resistor and a pull-up resistor are arranged in a peripheral circuit of the hardware, and if the second level signal is a high level signal, determining that a pull-up resistor is arranged in the peripheral circuit. And if the third level signal is a high level signal, determining that the resistance value of the pull-up resistor meets the condition of the high level signal. Therefore, the pull-up resistor meeting the high-level signal condition is arranged in the peripheral circuit of the hardware of the type, and the hardware of the type is taken as the hardware of the fourth type, so that the hardware of the fourth type can be identified.
This embodiment exemplifies only four types of hardware provided with a pull-up resistor or a pull-down resistor identified by three level signals, and in other embodiments, a plurality of types of hardware provided with a pull-up resistor and a pull-down resistor may also be identified by three level signals.
In the embodiment, the first type of hardware is identified according to the condition that the first level signal, the second level signal and the third level signal are all low level signals; if the first level signal and the third level signal are both low level signals and the second level signal is a high level signal, identifying second type hardware; if the first level signal and the second level signal are both high level signals and the third level signal is a low level signal, identifying a third type of hardware; if the first level signal, the second level signal and the third level signal are all high level signals, identifying the fourth type of hardware, and identifying at least four different types of hardware based on the three level signals.
Fig. 4 is a schematic flowchart of another hardware identification method provided by the present disclosure, and fig. 4 is a flowchart of the embodiment shown in fig. 2, before executing S101, further including:
s201, determining a target resistance value range of the pull-up resistor and a target resistance value range of the pull-down resistor according to the resistance value of the internal pull-up resistor, the resistance value of the internal pull-down resistor and a level threshold range.
As a detailed description of one possible implementation of S201, as shown in fig. 5:
and S2011, determining a first target resistance range of the pull-down resistor according to the resistance value of the internal pull-up resistor and the high level threshold range.
Based on the above embodiment, if the internal pull-up resistor is in the on state and the peripheral circuit of the hardware is provided with only the pull-down resistor R2, the voltage Ua at the internal port a is Vcc R2(Ru + R2). Illustratively, the high threshold range is [ VH1, VH2], and the first target resistance range is determined according to the following equation:
VH1≤Vcc*R2(Ru+R2)≤VH2
and solving the inequality to obtain a first target resistance value range.
And S2012, determining a second target resistance range of the pull-down resistor according to the resistance value of the internal pull-up resistor and the low level threshold range.
Based on the above embodiment, illustratively, the low level threshold range is [ VL1, VL2], and the second target resistance value range is determined according to the following formula:
VL1≤Vcc*R2(Ru+R2)≤VL2
and solving the inequality to obtain a second target resistance value range.
And S2013, determining a third target resistance range of the pull-up resistor according to the resistance value of the internal pull-down resistor and the high level threshold range.
Based on the above embodiment, the internal pull-down resistors are all in the on state, and if the peripheral circuit of the hardware is provided with only the pull-up resistor R1, the voltage Ua at the internal port a is Vcc R1(Rd + R1).
Illustratively, the high threshold range is [ VH1, VH2], and the third target resistance range is determined according to the following equation:
VH1≤Vcc*R1(Rd+R1)≤VH2
and solving the inequality to obtain a third target resistance value range.
And S2014, determining a fourth target resistance range of the pull-up resistor according to the resistance value of the internal pull-down resistor and the low level threshold range.
Based on the above embodiments, illustratively, the low level threshold range is [ VL1, VL2], and the fourth target resistance value range is determined according to the following formula:
VL1≤Vcc*R1(Rd+R1)≤VL2
and solving the inequality to obtain a fourth target resistance value range.
One specific example is given below:
in the IO interface, the internal pull-up resistor Ru is 20K, the internal pull-down resistor Rd is 20K, the high-level threshold range is [1.26V, 2.1V ], the low-level threshold range is [ -0.3V, 0.54V ], and the system power Vcc is 1.8V. Determining that the first target resistance range R2 is more than or equal to 46.7K based on 1.26V more than or equal to 1.8R 2(R2+20) more than or equal to 2.1V; determining a second target resistance range R2 is less than or equal to 8.57K based on-0.3V is less than or equal to 1.8R 2(R2+20) is less than or equal to 0.54V; determining that the third target resistance range R1 is more than or equal to 46.7K based on that 1.26V is less than or equal to 1.8R 1(R1+20) is less than or equal to 2.1V; the fourth target resistance range R2 is determined to be 8.57K or less based on-0.3V or less 1.8 × R1(R1+20) or less 0.54V.
S203, determining the target resistance value of the pull-up resistor and the target resistance value of the pull-down resistor from the target resistance value range.
Illustratively, according to the above embodiment, within the first target resistance value range R2 ≧ 46.7K, a resistance value is arbitrarily determined as the target resistance value of the pull-down resistor, for example, the target resistance value of the pull-down resistor is 46.7K; within the second target resistance range R2 ≦ 8.57K, one resistance value is arbitrarily determined as another target resistance value of the pull-down resistor, for example, another target resistance value of the pull-down resistor is 8.57K. Within the third target resistance range R1 being more than or equal to 46.7K, randomly determining a resistance value as the target resistance value of the pull-up resistor, for example, the target resistance value of the pull-up resistor is 46.7K; within the fourth target resistance range R2 ≦ 8.57K, one resistance is arbitrarily determined as another target resistance of the pull-up resistor, for example, another target resistance of the pull-up resistor of 8.57K.
S205, setting the pull-up resistor and/or the pull-down resistor with corresponding resistance values for different types of hardware based on the corresponding relation between the target resistance value of the pull-up resistor and/or the target value of the pull-down resistor and the type of the hardware.
Illustratively, based on the above embodiment, a corresponding relationship between the pull-down resistor with a resistance of 8.57K and the first type of hardware, a corresponding relationship between the pull-down resistor with a resistance of 46.7K and the second type of hardware, a corresponding relationship between the pull-up resistor with a resistance of 8.57K and the third type of hardware, and a corresponding relationship between the pull-up resistor with a resistance of 46.7K and the fourth type of hardware are established. Based on the above correspondence, the pull-down resistor with a resistance of 8.57K is disposed in the peripheral circuit of the first type of hardware, the pull-down resistor with a resistance of 46.7K is disposed in the peripheral circuit of the second type of hardware, the pull-up resistor with a resistance of 8.57K is disposed in the peripheral circuit of the third type of hardware, and the pull-up resistor with a resistance of 46.7K is disposed in the peripheral circuit of the fourth type of hardware.
In the embodiment, a target resistance value range of the pull-up resistor and a target resistance value range of the pull-down resistor are determined according to the resistance value of the internal pull-up resistor, the resistance value of the internal pull-down resistor and a level threshold range; determining a target resistance value of the pull-up resistor and a target resistance value of the pull-down resistor from the target resistance value range; based on the target resistance value of the pull-up resistor and/or the target value of the pull-down resistor and the corresponding relation between the target value of the pull-up resistor and the type of the hardware, the pull-up resistor and/or the pull-down resistor with corresponding resistance values are set aiming at different types of hardware, the pull-up resistor and/or the pull-down resistor with different resistance values can be set aiming at different types of hardware, and the fact that the different types of hardware can be identified by a single IO interface is guaranteed.
Fig. 6 is a schematic flowchart of another hardware identification method provided by the present disclosure, where fig. 6 is based on the embodiment shown in fig. 5, before executing S2011, the method further includes:
s301, determining the high level threshold range according to the high level judgment coefficient, the system power supply and the voltage parameter.
As a detailed description of one possible implementation when S301 is performed, as shown in fig. 7:
s3011, determining a first high level threshold value according to the product of the high level judgment coefficient and the system power supply.
Illustratively, the first high level threshold VH1 is determined based on the following formula according to the high level determination coefficient m and the system power supply Vcc:
VH1＝m*Vcc
for example, the system power supply Vcc is 1.8V, the high level determination coefficient m is 0.7, and the first high level threshold VH1 is 1.26V determined according to the above equation.
S3012, determining a second high level threshold according to the sum of the system power supply and the voltage parameter.
Illustratively, the second high level threshold VH2 is determined based on the following equation, based on the system power supply Vcc and the voltage parameter Δ V:
VH1＝Vcc+ΔV
for example, based on the above embodiment, the voltage parameter Δ V is 0.3V, and the second high level threshold VH2 is determined to be 2.1V according to the above formula.
S3013, determines a threshold range that is greater than or equal to the first high level threshold and less than or equal to the second high level threshold as the high level threshold range.
Illustratively, based on the above embodiment, the high level threshold range may be [1.26V, 2.1V ].
And S303, determining the low level threshold range according to a low level judgment coefficient, the system power supply and the voltage parameter.
As a detailed description of one possible implementation when S303 is performed, as shown in fig. 8:
s3031, determining a first low level threshold according to the negative value of the voltage parameter.
Illustratively, a negative value- Δ V based on the voltage parameter is determined as the first low level threshold VL 1. For example, the voltage parameter Δ V is 0.3V, and the first high level threshold VL1 is-0.3V.
S3032, determining a second low level threshold according to the product of the low level judgment coefficient and the system power supply.
Illustratively, the second low level threshold VL2 is determined based on the low level determination coefficient n, the system power supply Vcc, and the following equation:
VL2＝n*Vcc
for example, the system power supply Vcc is 1.8V, the low level determination coefficient n is 0.3, and the second low level threshold VL2 is determined to be 0.54V according to the above equation.
S3033, a threshold range equal to or greater than the first low level threshold value and equal to or less than the second low level threshold value is determined as the low level threshold range.
Illustratively, based on the above embodiment, the low level threshold range may be [ -0.3V, 0.54V ].
Fig. 9 is a schematic structural diagram of the hardware identification apparatus provided in the present disclosure, and the embodiment shown in fig. 9 is applied to the IO interface shown in fig. 1, as shown in fig. 9, the hardware identification apparatus 100 includes:
an obtaining module 110, configured to obtain a first level signal received by the internal port when both the internal pull-up resistor and the internal pull-down resistor are in a suspended state; when the internal pull-up resistor is in a conducting state, a second level signal received by the internal port is obtained; and when the internal pull-down resistor is in a conducting state, acquiring a third level signal received by the internal port.
And the identifying module 120 is configured to identify different types of hardware according to the first level signal, the second level signal, and the third level signal.
Optionally, the identifying module 120 is further configured to identify a first type of hardware if the first level signal, the second level signal, and the third level signal are all low level signals; if the first level signal and the third level signal are both low level signals and the second level signal is a high level signal, identifying second type hardware; if the first level signal and the second level signal are both high level signals and the third level signal is a low level signal, identifying a third type of hardware; and if the first level signal, the second level signal and the third level signal are all high level signals, identifying fourth type hardware.
Optionally, the hardware identification apparatus 100 further includes:
the determining module is used for determining a target resistance value range of the pull-up resistor and a target resistance value range of the pull-down resistor according to the resistance value of the internal pull-up resistor, the resistance value of the internal pull-down resistor and a level threshold range; and determining the target resistance value of the pull-up resistor and the target resistance value of the pull-down resistor from the target resistance value range.
And the setting module is used for setting the pull-up resistor and/or the pull-down resistor with corresponding resistance values aiming at different types of hardware based on the corresponding relation between the target resistance value of the pull-up resistor and/or the target value of the pull-down resistor and the type of the hardware.
Optionally, the determining module is further configured to determine a first target resistance value range of the pull-down resistor according to the resistance value of the internal pull-up resistor and a high level threshold range; determining a second target resistance range of the pull-down resistor according to the resistance value of the internal pull-up resistor and the low level threshold range; determining a third target resistance range of the pull-up resistor according to the resistance value of the internal pull-down resistor and the high level threshold range; and determining a fourth target resistance range of the pull-up resistor according to the resistance value of the internal pull-down resistor and the low level threshold range.
Optionally, the determining module is further configured to determine the high level threshold range according to a high level determination coefficient, a system power supply, and a voltage parameter; and determining the low level threshold range according to the low level judgment coefficient, the system power supply and the voltage parameter.
Optionally, the determining module is further configured to determine a first high level threshold according to a product of the high level determination coefficient and the system power supply; determining a second high level threshold based on a sum of the system power supply and the voltage parameter; and determining a threshold range which is greater than or equal to the first high level threshold value and less than or equal to the second high level threshold value as the high level threshold range.
Optionally, the determining module is further configured to determine a first low level threshold according to a negative value of the voltage parameter; determining a second low level threshold value according to the product of the low level judgment coefficient and the system power supply; determining a threshold range that is greater than or equal to the first low level threshold and less than or equal to the second low level threshold as the low level threshold range.
The hardware identification apparatus provided in this embodiment is configured to execute the steps of any one of the method embodiments, and has the technical solutions and technical effects of the method embodiments, which are not described herein again.
An embodiment of the present invention further provides a computer device, where the computer device may be a terminal, and an internal structure diagram of the computer device may be as shown in fig. 10. The computer device includes a processor, a memory, a communication interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The communication interface of the computer device is used for carrying out wired or wireless communication with an external terminal, and the wireless communication can be realized through WIFI, an operator network, Near Field Communication (NFC) or other technologies. The computer program is executed by a processor to implement a method of switching customized applications. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.
Those skilled in the art will appreciate that the architecture shown in fig. 10 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, the hardware identification apparatus provided in the present application may be implemented in the form of a computer program, and the computer program may be run on a computer device as shown in fig. 10. The memory of the computer device may store various program modules constituting the switching apparatus, such as the acquisition module 110 and the identification module 120 shown in fig. 9. The computer program of each program module causes the processor to perform the steps of the method embodiments described above.
For example, the computer device shown in fig. 10 may perform steps S101, S103, and S105 through the acquisition module 110 in the hardware identification apparatus shown in fig. 9. The computer device may perform step S107 through the recognition module 120.
The embodiment of the invention also provides an electronic device, which comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes the following steps when executing the computer program:
s101, when the internal pull-up resistor and the internal pull-down resistor are both in a suspended state, a first level signal received by the internal port is obtained.
And S103, acquiring a second level signal received by the internal port when the internal pull-up resistor is in a conducting state.
And S105, when the internal pull-down resistor is in a conducting state, acquiring a third level signal received by the internal port.
And S107, identifying different types of hardware according to the first level signal, the second level signal and the third level signal.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
s1071, if the first level signal, the second level signal and the third level signal are all low level signals, identifying a first type of hardware.
S1072, if the first level signal and the third level signal are both low level signals and the second level signal is a high level signal, identifying a second type of hardware.
S1073, if the first level signal and the second level signal are both high level signals and the third level signal is a low level signal, identifying a third type of hardware.
S1074, if the first level signal, the second level signal and the third level signal are all high level signals, identifying fourth type hardware.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
s201, determining a target resistance value range of the pull-up resistor and a target resistance value range of the pull-down resistor according to the resistance value of the internal pull-up resistor, the resistance value of the internal pull-down resistor and a level threshold range.
S203, determining the target resistance value of the pull-up resistor and the target resistance value of the pull-down resistor from the target resistance value range.
S205, setting the pull-up resistor and/or the pull-down resistor with corresponding resistance values for different types of hardware based on the corresponding relation between the target resistance value of the pull-up resistor and/or the target value of the pull-down resistor and the type of the hardware.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
and S2011, determining a first target resistance range of the pull-down resistor according to the resistance value of the internal pull-up resistor and the high level threshold range.
And S2012, determining a second target resistance range of the pull-down resistor according to the resistance value of the internal pull-up resistor and the low level threshold range.
And S2013, determining a third target resistance range of the pull-up resistor according to the resistance value of the internal pull-down resistor and the high level threshold range.
And S2014, determining a fourth target resistance range of the pull-up resistor according to the resistance value of the internal pull-down resistor and the low level threshold range.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
s301, determining the high level threshold range according to the high level judgment coefficient, the system power supply and the voltage parameter.
And S303, determining the low level threshold range according to a low level judgment coefficient, the system power supply and the voltage parameter.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
s3011, determining a first high level threshold value according to the product of the high level judgment coefficient and the system power supply.
S3012, determining a second high level threshold according to the sum of the system power supply and the voltage parameter.
S3013, determines a threshold range that is greater than or equal to the first high level threshold and less than or equal to the second high level threshold as the high level threshold range.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
s3031, determining a first low level threshold according to the negative value of the voltage parameter.
S3032, determining a second low level threshold according to the product of the low level judgment coefficient and the system power supply.
S3033, a threshold range equal to or greater than the first low level threshold value and equal to or less than the second low level threshold value is determined as the low level threshold range.
In the technical scheme provided by this embodiment, when both the internal pull-up resistor and the internal pull-down resistor are in a suspended state, a first level signal received by the internal port is obtained; when the internal pull-up resistor is in a conducting state, a second level signal received by the internal port is obtained; when the internal pull-down resistor is in a conducting state, a third level signal received by the internal port is obtained; according to the first level signal, the second level signal and the third level signal, different types of hardware are identified, each level signal can be a high level signal or a low level signal, eight possible results are provided for the three level signals, and different types of hardware are provided for each type of possible hardware, so that a single IO can identify various types of hardware, the number of hardware types identified by the single IO can be increased, and IO interface resources can be released.
An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the following steps:
s101, when the internal pull-up resistor and the internal pull-down resistor are both in a suspended state, a first level signal received by the internal port is obtained.
And S103, acquiring a second level signal received by the internal port when the internal pull-up resistor is in a conducting state.
And S105, when the internal pull-down resistor is in a conducting state, acquiring a third level signal received by the internal port.
And S107, identifying different types of hardware according to the first level signal, the second level signal and the third level signal.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
s1071, if the first level signal, the second level signal and the third level signal are all low level signals, identifying a first type of hardware.
S1072, if the first level signal and the third level signal are both low level signals and the second level signal is a high level signal, identifying a second type of hardware.
S1073, if the first level signal and the second level signal are both high level signals and the third level signal is a low level signal, identifying a third type of hardware.
S1074, if the first level signal, the second level signal and the third level signal are all high level signals, identifying fourth type hardware.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
s201, determining a target resistance value range of the pull-up resistor and a target resistance value range of the pull-down resistor according to the resistance value of the internal pull-up resistor, the resistance value of the internal pull-down resistor and a level threshold range.
S203, determining the target resistance value of the pull-up resistor and the target resistance value of the pull-down resistor from the target resistance value range.
S205, setting the pull-up resistor and/or the pull-down resistor with corresponding resistance values for different types of hardware based on the corresponding relation between the target resistance value of the pull-up resistor and/or the target value of the pull-down resistor and the type of the hardware.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
and S2011, determining a first target resistance range of the pull-down resistor according to the resistance value of the internal pull-up resistor and the high level threshold range.
And S2012, determining a second target resistance range of the pull-down resistor according to the resistance value of the internal pull-up resistor and the low level threshold range.
And S2013, determining a third target resistance range of the pull-up resistor according to the resistance value of the internal pull-down resistor and the high level threshold range.
And S2014, determining a fourth target resistance range of the pull-up resistor according to the resistance value of the internal pull-down resistor and the low level threshold range.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
s301, determining the high level threshold range according to the high level judgment coefficient, the system power supply and the voltage parameter.
And S303, determining the low level threshold range according to a low level judgment coefficient, the system power supply and the voltage parameter.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
s3011, determining a first high level threshold value according to the product of the high level judgment coefficient and the system power supply.
S3012, determining a second high level threshold according to the sum of the system power supply and the voltage parameter.
S3013, determines a threshold range that is greater than or equal to the first high level threshold and less than or equal to the second high level threshold as the high level threshold range.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
s3031, determining a first low level threshold according to the negative value of the voltage parameter.
S3032, determining a second low level threshold according to the product of the low level judgment coefficient and the system power supply.
S3033, a threshold range equal to or greater than the first low level threshold value and equal to or less than the second low level threshold value is determined as the low level threshold range.
According to the technical scheme provided by the embodiment of the invention, when the internal pull-up resistor and the internal pull-down resistor are both in a suspended state, a first level signal received by an internal port is obtained; when the internal pull-up resistor is in a conducting state, a second level signal received by the internal port is obtained; when the internal pull-down resistor is in a conducting state, a third level signal received by the internal port is obtained; according to the first level signal, the second level signal and the third level signal, different types of hardware are identified, each level signal can be a high level signal or a low level signal, eight possible results are provided for the three level signals, and different types of hardware are provided for each type of possible hardware, so that a single IO can identify various types of hardware, the number of hardware types identified by the single IO can be increased, and IO interface resources can be released.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, database, or other medium used in the embodiments provided herein may include at least one of non-volatile and volatile memory. Non-volatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical storage, or the like. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and the like.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, the scope of the present description should be considered as being described in the present specification.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present disclosure, which enable those skilled in the art to understand or practice the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. The hardware identification method is characterized by being applied to at least one input/output (IO) interface, wherein an internal port of the IO interface is electrically connected with a high level through an internal pull-up resistor and is grounded through an internal pull-down resistor;
the method comprises the following steps:
when the internal pull-up resistor and the internal pull-down resistor are both in a suspended state, acquiring a first level signal received by the internal port;
when the internal pull-up resistor is in a conducting state, a second level signal received by the internal port is obtained;
when the internal pull-down resistor is in a conducting state, a third level signal received by the internal port is obtained;
and identifying different types of hardware according to the first level signal, the second level signal and the third level signal.
2. The method of claim 1, wherein identifying different types of hardware based on the first level signal, the second level signal, and the third level signal comprises:
if the first level signal, the second level signal and the third level signal are all low level signals, identifying first type hardware;
if the first level signal and the third level signal are both low level signals and the second level signal is a high level signal, identifying second type hardware;
if the first level signal and the second level signal are both high level signals and the third level signal is a low level signal, identifying a third type of hardware;
and if the first level signal, the second level signal and the third level signal are all high level signals, identifying fourth type hardware.
3. The method according to claim 1 or 2, wherein before acquiring the first level signal received by the internal port, the method further comprises:
determining a target resistance value range of the pull-up resistor and a target resistance value range of the pull-down resistor according to the resistance value of the internal pull-up resistor, the resistance value of the internal pull-down resistor and a level threshold range;
determining a target resistance value of the pull-up resistor and a target resistance value of the pull-down resistor from the target resistance value range;
and setting the pull-up resistor and/or the pull-down resistor with corresponding resistance values for different types of hardware based on the corresponding relation between the target resistance value of the pull-up resistor and/or the target value of the pull-down resistor and the type of the hardware.
4. The method of claim 3, wherein determining the target range of values of the pull-up resistor and the pull-down resistor according to the value of the internal pull-up resistor, the value of the internal pull-down resistor, and the level threshold range comprises:
determining a first target resistance range of the pull-down resistor according to the resistance value of the internal pull-up resistor and a high level threshold range;
determining a second target resistance range of the pull-down resistor according to the resistance value of the internal pull-up resistor and the low level threshold range;
determining a third target resistance range of the pull-up resistor according to the resistance value of the internal pull-down resistor and the high level threshold range;
and determining a fourth target resistance range of the pull-up resistor according to the resistance value of the internal pull-down resistor and the low level threshold range.
5. The method of claim 4, wherein before determining the first target resistance range of the pull-down resistor according to the resistance of the internal pull-up resistor and the high threshold range, the method further comprises:
determining the high level threshold range according to a high level judgment coefficient, a system power supply and a voltage parameter;
and determining the low level threshold range according to the low level judgment coefficient, the system power supply and the voltage parameter.
6. The method of claim 5, wherein determining the high level threshold range based on the high level decision coefficient, the system power supply, and the voltage parameter comprises:
determining a first high level threshold value according to the product of the high level judgment coefficient and the system power supply;
determining a second high level threshold based on a sum of the system power supply and the voltage parameter;
and determining a threshold range which is greater than or equal to the first high level threshold value and less than or equal to the second high level threshold value as the high level threshold range.
7. The method of claim 5, wherein determining the low level threshold range based on a low level decision coefficient, the system power supply, and the voltage parameter comprises:
determining a first low level threshold according to a negative value of the voltage parameter;
determining a second low level threshold value according to the product of the low level judgment coefficient and the system power supply;
determining a threshold range that is greater than or equal to the first low level threshold and less than or equal to the second low level threshold as the low level threshold range.
8. The hardware identification device is applied to at least one input/output (IO) interface, an internal port of the IO interface is electrically connected with a high level through an internal pull-up resistor, and the internal port is grounded through an internal pull-down resistor;
the identification device comprises:
the acquisition module is used for acquiring a first level signal received by the internal port when the internal pull-up resistor and the internal pull-down resistor are both in a suspended state; when the internal pull-up resistor is in a conducting state, a second level signal received by the internal port is obtained; when the internal pull-down resistor is in a conducting state, a third level signal received by the internal port is obtained;
and the identification module is used for identifying different types of hardware according to the first level signal, the second level signal and the third level signal.
9. An electronic device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor realizes the steps of the method according to any of claims 1-7 when executing the computer program.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 7.
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| CN114519027A (en) * | 2022-02-21 | 2022-05-20 | 上海矽翊微电子有限公司 | Self-adaptive communication interface, communication protocol automatic identification method and electronic device |
| CN117278355A (en) * | 2023-11-16 | 2023-12-22 | 杭州视芯科技股份有限公司 | Master-slave communication system, control method of master-slave communication system, and computer device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114519027A (en) * | 2022-02-21 | 2022-05-20 | 上海矽翊微电子有限公司 | Self-adaptive communication interface, communication protocol automatic identification method and electronic device |
| CN117278355A (en) * | 2023-11-16 | 2023-12-22 | 杭州视芯科技股份有限公司 | Master-slave communication system, control method of master-slave communication system, and computer device |
| CN117278355B (en) * | 2023-11-16 | 2024-03-08 | 杭州视芯科技股份有限公司 | Master-slave communication system, control method of master-slave communication system, and computer device |
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