CN113778031A

CN113778031A - Intelligent control node and data transmission method

Info

Publication number: CN113778031A
Application number: CN202110997602.9A
Authority: CN
Inventors: 范福基; 孙凌丽; 贾峰; 王雪峰; 黄玲; 李蒙; 朱毅明
Original assignee: Beijing Hollysys Co Ltd
Current assignee: Beijing Hollysys Co Ltd
Priority date: 2021-08-27
Filing date: 2021-08-27
Publication date: 2021-12-10

Abstract

The embodiment of the disclosure discloses an intelligent control node applied to an industrial control system and a data transmission method. Wherein, the intelligent control node includes: the controller comprises a controller body and an artificial intelligence AI module; the controller body is configured to execute logic or process control tasks; the system is also set to be communicated with an upper computer in the industrial control system through an Ethernet protocol interface and communicated with the AI module through a PCIe (peripheral component interconnect express) switch of a high-speed serial computer expansion bus; the AI module is configured to perform industrial machine vision processing-like tasks. The scheme of the embodiment of the disclosure provides a brand-new industrial control node architecture, introduces an AI module to independently process the visual processing tasks of the industrial machine, and can fully meet the intelligent processing/control requirements of related video images in an industrial control system.

Description

Intelligent control node and data transmission method

Technical Field

The invention relates to the field of industrial control, in particular to an intelligent control node applied to an industrial control system and a data transmission method.

Background

The business requirements in the industrial control field are increasingly complex, and the complexity of an industrial control system or equipment is increased by the aspects of increasing control objects, increasing complex control tasks, and providing multiple sources of heterogeneous information. Especially along with video monitoring, the image recognition technology is applied and popularized, more and more industrial control systems need to utilize video or image related intelligent schemes, and the intelligent level of overall control is further improved. Most of the intelligent algorithms have the characteristics of iterative evolution execution and strong parallelism, need strong computing power and more storage resources, and cannot be directly deployed in a traditional controller module based on an embedded platform. How to break through the limitation of the limited resource environment of a single station of the controller and enable the controller to have the intelligent identification processing and intelligent control capability of the industrial image is a problem which needs to be solved urgently in the field.

Disclosure of Invention

The embodiment of the disclosure provides an intelligent control node and a data transmission method applied to an industrial control system, provides a brand-new industrial control node (controller) architecture, and introduces an AI module to independently process industrial machine vision processing tasks, so as to fully meet the intelligent processing/control requirements of related video images in the industrial control system.

The embodiment of the present disclosure provides an intelligent control node, which is applied to an industrial control system, and includes:

the controller comprises a controller body and an artificial intelligence AI module;

wherein the controller body is configured to perform logical or process control type tasks; the system is also set to be communicated with an upper computer in the industrial control system through an Ethernet protocol interface and communicated with the AI module through a PCIe (peripheral component interconnect express) switch of a high-speed serial computer expansion bus;

the AI module is configured to perform industrial machine vision processing-like tasks.

The embodiment of the present disclosure further provides a data transmission method, which is applied to the above intelligent control node, and includes:

an industrial camera acquires video data;

an AI module in the intelligent control node processes the video data according to the preloaded image preprocessing algorithm;

the AI module processes the preprocessed video data according to the preloaded AI inference algorithm to obtain an inference result;

and the AI module processes the inference result to obtain data in a specified format according to the preloaded data format specification, and reports the data in the specified format to the upper computer.

Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an intelligent control node in an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of another intelligent control node in the embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of another intelligent control node in the embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of another intelligent control node in the embodiment of the present disclosure;

FIG. 5 is a flow chart of a data transmission method in an embodiment of the present disclosure;

FIG. 6 is a flow chart of another method of data transmission in an embodiment of the present disclosure;

FIG. 7 is a flow chart of another method of data transmission in an embodiment of the present disclosure;

fig. 8 is a flowchart of another data transmission method in the embodiment of the present disclosure.

The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.

In addition, the descriptions related to "first", "second", etc. in the present invention are only for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "connected," "secured," and the like are to be construed broadly, and for example, "secured" may be a fixed connection, a removable connection, or an integral part; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In addition, the technical solutions in the embodiments of the present invention may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination of technical solutions should not be considered to exist, and is not within the protection scope of the present invention.

The industrial control system gradually relates to the transmission and processing of more and more video or image data, and in order to improve the processing effectiveness and accuracy, the processing schemes related to the video or image are more intelligent, have the characteristics of iterative evolution execution and strong parallelism, and inevitably require stronger computing power and related resources. These intelligent processing schemes cannot be deployed easily and efficiently in existing embedded platform-based controllers. Therefore, the embodiment of the present disclosure provides a new intelligent control node architecture, which is a hybrid heterogeneous architecture of multiple types of processing units, and can support processing of real-time or non-real-time tasks such as logic control, process control, motion control, machine vision, and the like, and meet complex operation requirements. The video or image data is processed through the independent AI module, so that the processing speed can be greatly increased, and the communication bandwidth in an industrial control system network is reduced.

The embodiment of the present disclosure provides an intelligent control node, as shown in fig. 1, applied to an industrial control system, including:

a controller body 101 and an artificial intelligence AI module 102;

wherein the controller body 101 is configured to perform logic or process control type tasks; the system is also set to communicate with an upper computer in the industrial control system through an Ethernet protocol interface and communicate with the AI module 102 through a high-speed serial computer expansion bus PCIe switch;

the AI module 102 is configured to perform industrial machine vision processing-like tasks.

In some example embodiments, logic or process control type tasks are primarily directed to controlling situations in a production process where the speed of response is relatively low, e.g., tasks that allow responses to be returned on the order of hundreds of milliseconds; that is, the logic or process control type task is a task that controls the response time of the task execution in the production process not to exceed the first response time length. For example, switching value sequential control and/or analog quantity sequential operation control, performing arithmetic operations, functional operations, trigonometric operations, matrix operations, and/or closed-loop control PID (proportional-integral-derivative) operations, etc., in some exemplary embodiments the first response duration is on the order of a hundred milliseconds, e.g., the first response duration is 200 milliseconds, i.e., a logic or process control type task is a control task requiring a response time of no more than 200 milliseconds.

In some exemplary embodiments, as shown in fig. 2, the intelligent control node further includes: and the field programmable gate array FPGA module 103 is configured to execute real-time motion control tasks and is communicated with the controller body 101 through the PCIe switch.

In some exemplary embodiments, the real-time motion control-type task is mainly used for controlling the situation that the requirement on the response speed in the production process is relatively high, for example, the task which must return the response within millisecond level; namely, the real-time motion control task is a task for controlling the response time of the task execution in the production process not to exceed the second response time length. For example, control of the position, velocity and/or acceleration of the target object; the linear motion can be single-coordinate linear motion, and the motion can also be multi-coordinate platform, solid, angle transformation and the like. In some exemplary embodiments, the second response duration is a millisecond duration, for example, the second response duration is 1 millisecond, i.e., the real-time motion control-like task is a control task requiring a response within 1 millisecond.

Wherein the first response duration is greater than the second response duration.

In some exemplary embodiments, as shown in fig. 3, the intelligent control node further includes: other task execution modules 104 configured to perform collection of signal inputs, signal outputs, and/or data communication tasks with other controlled devices (field instruments); the other task execution module 104 also communicates with the controller body through the PCIe switch.

In some exemplary embodiments, acquiring the signal input comprises: the method refers to the acquisition, filtering and digital conversion of analog quantity signals such as current, voltage, temperature, pressure and the like, and/or the acquisition and filtering of switching value signals and the like. The executing the signal output includes: the latch and the simulation of the output digital quantity signal, and/or the output and the holding of the switching value signal. Data communication tasks refer to performing ethernet or fieldbus protocol communications with field instruments or other devices, including: establishment of communications, parameter configuration, data exchange and/or diagnostic processing, etc.

It can be understood that the controller body 101 is provided with the PCIe switch (PCIe switch) as a PCIe RC end to communicate with the external module 102 and 104 through the PCIe bus, which includes pre-installed data downloading, control command issuing, collected data reporting, and the like. The AI module 102 is connected to the industrial camera, can diagnose the self state, the industrial camera state, and the like, and reports the diagnosis result to the controller body 101 in real time; the AI module 102 acquires a live video or image through the industrial camera, performs graphic image recognition and processing, uploads the result to the controller body for further processing, and can also transmit an abnormal picture to the upper computer through the controller body 101 for storage.

In some exemplary embodiments, the controller body 101 includes: a CPU1011, an ethernet protocol interface 1012, and a PCIe switch 1013.

In some exemplary embodiments, as shown in fig. 4, the controller body 101 further includes PCIe RC interface logic 1014, which communicates with the external module 102 and 104 through the PCIe switch 1013. The PCIe RC interface logic 1014 is a PCIe protocol logic implemented by a hardware description language and using an RC (root complex) mode for communication.

In some exemplary embodiments, as shown in fig. 4, the AI module 102 includes: AI chipset 1021 and FPGA chipset 1022;

the AI chipset 1021 includes: a central processing unit CPU10211, an embedded neural network processor NPU10212 and an Ethernet interface 10213;

the AI chipset 1021 further includes: a first USB interface 10214 or a first SPI interface 10215;

the FPGA chipset 1022 includes: a microprocessor MCU 10221; further comprising: a second USB interface 10222 or a second SPI interface 10223;

the ethernet interface 10213 is used to communicate with an industrial camera;

the AI chipset 1021 communicates with the second USB interface 10222 of the FPGA chipset 1022 through the first USB interface 10214; alternatively, the AI chipset 1021 communicates with the second SPI interface 10223 of the FPGA chipset through the first SPI interface 10215.

In some exemplary embodiments, the FPGA chipset 1022 further includes: memory 10224, memory controller 10225, PCIe EP interface logic 10226, PCIe interface 10227;

the PCIe EP interface logic 10226 is PCIe protocol logic implemented by a hardware description language and using an EP (endpoint) mode for communication, and is also referred to as PCIe EP logic;

the FPGA chipset 1022 is configured to communicate with the controller body 101 via the PCIe interface 10227 using the PCIe EP interface logic 10226 logic.

In some exemplary embodiments, the memory 10224 is a DDR (Double Data Rate).

The FPGA chipset 1022 performs PCIe protocol communication with the controller body 101 in an EP mode, and the controller body 101 corresponds to PCIe RC interface logic 1014, also referred to as PCIe RC (Root Complex) logic.

In some exemplary embodiments, the AI chipset 1021 is further configured to act as a master to read and write data in the memory 10224 via USB (Universal Serial Bus) or SPI (Serial Peripheral Interface) protocols.

In some exemplary embodiments, the FPGA chipset 1022 is further configured to set the signal bit of the AI chipset 1021 via a general purpose input output GPIO.

Wherein the signal bit of the AI chipset 1021 comprises at least one of:

inputting an interrupt signal, a read completion signal, and a write completion signal.

In some exemplary embodiments, setting the signal bit of the AI chipset 1021 by GPIO includes: setting the low level of the signal bits through GPIO, and then the signal bits are valid; accordingly, the signal bits are cleared by setting these signal bits high through the GPIO. Other arrangements may also be selected by those skilled in the art and are not limited to the examples set forth in this disclosure.

In some exemplary embodiments, the controller body 101 is further configured to set the signal bits of the FPGA chipset 1022 through GPIO.

The signal bits of the FPGA chipset 1022 at least include: input interrupt signal of PCIe EP interface logic.

In some exemplary embodiments, setting the signal bit of the FPGA chipset 1022 through GPIO includes: setting the low level of the signal bits through GPIO, and then the signal bits are valid; accordingly, the signal bits are cleared by setting these signal bits high through the GPIO. Other arrangements may also be selected by those skilled in the art and are not limited to the examples set forth in this disclosure.

In some exemplary embodiments, the AI chipset communicates with the second USB interface of the FPGA chipset through a first USB interface, including:

the AI chip set serves as a master station, the FPGA chip set serves as a slave station, and communication is carried out through a USB protocol; or the AI chip set serves as a slave station, the FPGA chip set serves as a master station, and communication is carried out through a USB protocol;

or,

the AI chip set serves as a master station, the FPGA chip set serves as a slave station, and communication is carried out through a USB protocol; or the AI chipset is used as a slave station, and the FPGA chipset is used as a master station, and the communication is carried out through an SPI protocol.

It should be noted that the intelligent control node shown in fig. 4 is a schematic structural diagram of an embodiment of the present disclosure, and the PCIe switch 1013 in the controller body 101 and the PCIe interface 10227 in the FPGA chipset 1022 related in the above description are not temporarily embodied, and those skilled in the art can know specific implementation steps of the related aspects.

An embodiment of the present disclosure further provides a data transmission method, as shown in fig. 5, including:

step 501, an industrial camera acquires video data;

502, an AI module in the intelligent control node processes the video data according to a pre-loaded image preprocessing algorithm;

step 503, the AI module processes the preprocessed video data according to the preloaded AI inference algorithm to obtain an inference result;

and step 504, the AI module processes the inference result according to the preloaded data format specification to obtain data in a specified format, and reports the data in the specified format to an upper computer.

In some exemplary embodiments, step 502 includes:

and the CPU in the AI chip set in the AI module executes the image preprocessing algorithm to preprocess the video data.

Step 503 comprises:

and the NPU in the AI chip set in the AI module executes the AI inference algorithm to obtain the inference result.

Step 504 includes:

step 5041, the CPU in the AI chipset in the AI module processes the inference result according to the data format specification to obtain the data in the specified format;

step 5042, the AI chipset reports the data in the specified format to an FPGA chipset in the AI module;

step 5043, the FPGA chipset reports the data in the specified format to a controller body in the intelligent control node through PCIe EP interface logic;

step 5044, the controller body reports the data in the specified format to the upper computer through the ethernet interface.

In some exemplary embodiments, before step 501 or 502, the method further comprises:

step 5011, the controller body in the intelligent control node sends pre-installed data to the FPGA chipset in the AI module through a PCIe switch;

step 5012, the AI chipset in the AI module acquires the pre-installed data through a USB or SPI interface based on the communication parameters negotiated with the FPGA chipset;

in step 5013, the AI chipset loads the pre-installed data.

Wherein the pre-loaded data comprises at least one of:

an image preprocessing algorithm, an AI reasoning algorithm and a data format specification.

In some exemplary embodiments, the pre-loaded data further comprises at least one of:

the PCIe interface logic comprises initialization parameters of PCIe EP interface logic and communication parameters of an AI chip set and an FPGA chip set.

In some exemplary embodiments, the pre-loaded data further includes other download parameters from the controller (node).

In some exemplary embodiments, step 5011 includes:

after the PCIe EP interface logic of the FPGA chipset executes EP mode initialization, the controller body starts a direct memory access DMA to send the pre-installed data to an EP end data storage area in the PCIe EP interface logic of the FPGA chipset, and the pre-installed data in the EP end data storage area is written into a memory in the FPGA chipset through a storage controller in the FPGA chipset;

in some exemplary embodiments, step 5012 includes:

after the controller body finishes sending the pre-installed data, an input interrupt signal in the AI chipset is set through a GPIO (general purpose input/output) to instruct the AI chipset to download the pre-installed data;

the AI chip set is used as a protocol master station to read the pre-installed data in the memory through a USB or SPI protocol according to the indication of the input interrupt signal;

after the AI chipset finishes reading, the AI chipset sets a reading completion signal of the AI chipset;

and the FPGA chip set reads the reading completion signal of the AI chip set, resets a GPIO to clear the input interrupt signal of the AI chip set and clear the reading completion signal of the AI chip set.

step 5014, the AI module performs self-checking and/or the AI module performs state diagnosis on the connected industrial camera;

in step 5015, the AI module reports the self-inspection result and/or the industrial camera diagnosis result to the controller body.

It should be noted that, in the case that steps 5011-5015 are all executed, steps 5014-5015 and steps 5011-5013 are not limited to be executed sequentially.

In some exemplary embodiments, step 5042 includes:

the AI chip set acquires the state of a memory in the FPGA chip set;

under the condition that the state of the memory is determined to be write-in allowed, the AI chip set serves as a master station to write the data in the specified format into the memory through a USB or SPI protocol;

after the writing is completed, the AI chipset sets its own write completion signal.

In some exemplary embodiments, step 5043 includes:

the FPGA chip set reads a writing completion signal of the AI chip set;

setting an input interrupt signal of the PCIe EP interface logic through a GPIO (general purpose input/output) and clearing a write-in completion signal of the AI chipset;

the FPGA chipset sends an interrupt to the controller body through the PCIe EP interface logic;

the controller body starts a Direct Memory Access (DMA) to access an EP end data storage area in PCIe EP interface logic according to an interrupt signal, and acquires data in a specified format in the memory;

and after the data in the specified format is read, the controller body clears the input interrupt signal of the PCIe EP interface logic through a PCIe protocol.

An embodiment of the present disclosure further provides a data transmission method, where the transmission method is used to transmit downlink data to an AI chip, as shown in fig. 6, and the method includes:

1. and an EP end on the AI module FPGA chip set completes initialization, a BAR space is divided into a data storage area (used for reading and writing DDR) and a register area (used for operating GPIO).

2. The controller body sends downlink data to an EP end data storage area of PCIe EP interface logic on the AI module FPGA chip set through DMA transmission of a PCIe bus, and then writes the downlink data into the DDR through the DDR controller.

3. After the controller body finishes sending all downlink data, a register area of an EP end of PCIe EP interface logic is written through a PCIe bus, and an input interrupt signal of an AI chipset is set through a GPIO (set to be effective at a low level) to inform the AI chipset of downlink data acquisition.

4. The AI chip set is used as a protocol master station to acquire downlink data stored in DDR in the FPGA chip set through a USB/SPI protocol, and sets a reading completion signal of the AI chip set after the carrying is completed.

5. After the MCU of the FPGA chip set inquires a reading completion signal set by the AI chip set, resetting the GPIO (setting to be in high level and invalid) to clear an input interruption signal of the AI chip set and clear a reading completion signal set by the AI chip set.

An embodiment of the present disclosure further provides a data transmission method, where the data transmission method is used to transmit uplink data to a controller, as shown in fig. 7, and the method includes:

1. the AI chip set inquires the DDR data state of the FPGA chip set, when the state is write permission, the AI chip set serves as a USB/SPI master station to carry data to the FPGA chip set, the data are finally written into the DDR of the FPGA chip set, and a write completion signal on the FPGA chip set is set after the data are carried.

2. The MCU in the FPGA chipset inquires a write-in completion signal set by the AI chipset, operates the GPIO to set an input interrupt signal (set to be active at low level) of PCIe EP interface logic, and clears the write-in completion signal set by the AI chipset.

3. PCIe EP interface logic of the AI module FPGA chip set sends an interrupt to the controller body through a PCIe bus.

4. The controller body starts PCIe EP interface logic of the DMA access AI module FPGA chip set and reads data from the DDR of the FPGA chip set.

5. After the PCIe EP interface logic finishes data transmission, the controller body writes a GPIO area of the PCIe EP interface logic through a PCIe protocol, and clears an input interrupt signal (set to be invalid at a high level) of the PCIe EP interface logic through the GPIO.

The embodiment of the present disclosure further provides a data transmission method, where the graphic image recognition and processing task is mainly completed in an AI chipset, a software program of the data transmission method runs in a CPU integrated with the AI chipset, and an NPU is called by the CPU as an operation resource, as shown in fig. 8, the data transmission method includes:

1. initializing and setting;

the method comprises the following steps: the AI chip group negotiates the communication parameters with the FPGA chip group, receives the downloading parameters from the controller body, and updates and configures each operation parameter.

2. Loading an algorithm model;

the graphic image operation model file is loaded into a memory from a nonvolatile memory such as FLASH and the like, and data preparation is carried out for the subsequent AI reasoning process. If the controller body has a new downloaded algorithm model, the file in the FLASH memory is updated and reloaded into the memory, otherwise, the file is loaded into the memory once only after the AI module is powered on;

3. module self-diagnosis;

self-diagnosis is carried out on the state of the AI module and the state of the connected industrial camera, and if serious problems are diagnosed, the operation result is set to be unreliable;

4. acquiring an industrial camera image;

the acquisition of the video image signals of the industrial camera is completed, and the required video frames are acquired from the signals, wherein the acquisition can be carried out in a periodic acquisition mode or an event-triggered mode, and the acquisition depends on the setting of upper machine configuration software;

5. preprocessing an image;

the image preprocessing process includes deformity correction, rotation, size normalization, color and brightness compensation, graying, etc. for the image. And if the picture is judged to be abnormal and cannot be used, directly entering the step 8, otherwise, setting various operation parameter attributes aiming at the picture to be processed according to the entry function requirement of the algorithm model.

6. AI reasoning;

AI reasoning operation is the core part of the graphic image processing task and the part with the largest calculated amount, and the software program calls the interface function of the algorithm model and distributes the task to the NPU to complete the reasoning operation.

7. Acquiring a reasoning result;

after the NPU completes AI reasoning operation, the software program obtains AI reasoning operation results output by the NPU, and analyzes and arranges the operation results to obtain data with a specified format.

8. And reporting the result.

And the program negotiates with the FPGA chip set for communication, and sends a self-diagnosis result, a graph image operation result or an abnormal image as uplink data to the FPGA chip set and reports the uplink data to the controller body for processing.

The system architecture of the intelligent control node is a mixed heterogeneous architecture of multiple types of processing units, supports real-time and non-real-time task processing such as logic or process control, motion control, machine vision and the like, and can meet the requirement of complex operation. The controller body is interconnected with the AI module, the FPGA module and/or other modules through PCIe (peripheral component interface express), so that the cooperative work between the special accelerating unit and the processor in heterogeneous computing is realized. Compared with the traditional industrial controller, the framework has strong advantages in the aspects of rapid image acquisition, identification and processing, communication bandwidth reduction and the like, and can well meet the requirements of machine vision image processing.

It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims

1. The utility model provides an intelligent control node, is applied to industrial control system, its characterized in that includes:

2. The intelligent control node of claim 1,

further comprising: and the field programmable gate array FPGA module is set to execute real-time motion control tasks and is communicated with the controller body through the PCIe switch.

3. The intelligent control node of claim 1 or 2,

the AI module includes: an AI chip set and an FPGA chip set;

the AI chipset includes: the device comprises a Central Processing Unit (CPU), an embedded neural Network Processor (NPU) and an Ethernet interface;

the AI chipset further comprises: a first USB interface or a first SPI interface;

the FPGA chipset comprises: a microprocessor MCU; further comprising: a second USB interface or a second SPI interface;

the Ethernet interface is used for communicating with an industrial camera;

the AI chip set is communicated with a second USB interface of the FPGA chip set through a first USB interface; or the AI chipset communicates with a second SPI interface of the FPGA chipset through a first SPI interface.

4. The control node of claim 3,

the FPGA chipset further comprises: the system comprises a memory, a memory controller, PCIe EP interface logic and a PCIe interface;

the PCIe EP interface logic is PCIe protocol logic which is realized by a hardware description language and adopts EP mode communication;

the FPGA chipset is configured to communicate with the controller body through the PCIe interface by using the PCIe EP interface logic.

5. The intelligent control node of claim 4,

the AI chip set is also set as a master station to read and write the data in the memory through a USB or SPI protocol;

or,

the FPGA chip set is further set to set a signal position of the AI chip set through a general purpose input output GPIO;

or,

the controller body is further set to be used for setting the signal position of the FPGA chip set through the GPIO.

6. A data transmission method applied to the intelligent control node according to any one of claims 1-5, comprising:

an industrial camera acquires video data;

7. The method of claim 6,

the AI module in the intelligent control node processes the video data according to the preloaded image preprocessing algorithm, and the method comprises the following steps: the CPU in the AI chip set in the AI module executes the image preprocessing algorithm to preprocess the video data;

the AI module processes the preprocessed video data according to the preloaded AI inference algorithm to obtain an inference result, which comprises the following steps: the NPU in the AI chip set in the AI module executes the AI inference algorithm to obtain the inference result;

the AI module processes the reasoning result to obtain data in a specified format according to the preloaded data format specification, and reports the data in the specified format to an upper computer, and the method comprises the following steps: the CPU in the AI chip set in the AI module processes the inference result according to the data format specification to obtain the data in the specified format; the AI chip set reports the data with the specified format to an FPGA chip set in the AI module; the FPGA chipset reports the data with the specified format to a controller body in the intelligent control node through PCIe EP interface logic; and the controller body reports the data in the specified format to the upper computer through the Ethernet interface.

8. The method of claim 6,

the method further comprises the following steps:

the controller body in the intelligent control node sends pre-installed data to the FPGA chip set in the AI module through a PCIe switch;

the AI chipset in the AI module acquires the pre-installed data through a USB or SPI interface based on the communication parameters negotiated with the FPGA chipset;

the AI chip set loads the pre-installed data;

wherein the pre-loaded data comprises at least one of:

9. The method of claim 8,

the controller body in the intelligent control node sends pre-installed data to the FPGA chip set in the AI module through a PCIe switch, and the method comprises the following steps:

the AI chipset in the AI module acquires the pre-installed data through a USB or SPI interface based on the communication parameters negotiated with the FPGA chipset, and the method comprises the following steps:

after the controller body finishes sending the pre-installed data, an input interrupt signal in the AI chipset is set through a GPIO (general purpose input/output) to instruct the AI chipset to download the pre-installed data; the AI chip set is used as a protocol master station to read the pre-installed data in the memory through a USB or SPI protocol according to the indication of the input interrupt signal; after the AI chipset finishes reading, the AI chipset sets a reading completion signal of the AI chipset; and the FPGA chip set reads the reading completion signal of the AI chip set, resets a GPIO to clear the input interrupt signal of the AI chip set and clear the reading completion signal of the AI chip set.

10. The method of claim 7,

the reporting of the data in the specified format by the AI chipset to the FPGA chipset in the AI module includes:

the AI chip set acquires the state of a memory in the FPGA chip set; under the condition that the state of the memory is determined to be write-in allowed, the AI chip set serves as a master station to write the data in the specified format into the memory through a USB or SPI protocol; after the writing is finished, the AI chip set sets a writing finishing signal of the AI chip set;

the FPGA chipset reports the data with the specified format to a controller body in the intelligent control node through PCIe EP interface logic, and the method comprises the following steps:

the FPGA chip set reads a writing completion signal of the AI chip set; setting an input interrupt signal of the PCIe EP interface logic through a GPIO (general purpose input/output) and clearing a write-in completion signal of the AI chipset; the FPGA chipset sends an interrupt to the controller body through the PCIe EP interface logic; the controller body starts a Direct Memory Access (DMA) to access an EP end data storage area in PCIe EP interface logic according to an interrupt signal, and acquires data in a specified format in the memory; and after the data in the specified format is read, the controller body clears the input interrupt signal of the PCIe EP interface logic through a PCIe protocol.