CN113765648A

CN113765648A - Full-duplex communication method, device and system

Info

Publication number: CN113765648A
Application number: CN202010486100.5A
Authority: CN
Inventors: 张晓风; 赵砚博; 涂建平; 王祥
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-06-01
Filing date: 2020-06-01
Publication date: 2021-12-07
Anticipated expiration: 2040-06-01
Also published as: WO2021244094A1; CN113765648B

Abstract

The embodiment of the application provides a full-duplex communication method, a full-duplex communication device and a full-duplex communication system, which can realize full-duplex communication under the condition that clock frequencies of signals transmitted in two directions are not synchronous. The full duplex communication method comprises the following steps: the first interface device acquires a first serial signal of a first communication device, wherein the first serial signal is adapted to a first clock frequency; the first interface device carries out first clock frequency conversion on the first serial signal to obtain a second serial signal, wherein the second serial signal is adaptive to a second clock frequency which is greater than the first clock frequency; the first interface device sends the second serial signal to a second interface device; the second interface device carries out second clock frequency conversion on the second serial signal to obtain the first serial signal; the second interface device acquires a third serial signal of the second communication device, wherein the third serial signal is adapted to the second clock frequency; the second interface device sends the third serial signal to the first interface device.

Description

Full-duplex communication method, device and system

Technical Field

The present application relates to the field of communications, and more particularly, to a full duplex communication method, apparatus, and system in the field of communications.

Background

Vehicles play an increasingly important role in daily life, in-vehicle communication networks refer to communication between in-vehicle components and in-vehicle gateways, communication between in-vehicle area gateways, communication between data center switches and servers, and the like, and transmission rates of communication networks are one important index for evaluating transmission performance of in-vehicle communication networks.

A SERializer (SER)/DESerializer (DES), abbreviated as SERDES, adopts a point-to-point serial communication technology, converts multiple paths of low-speed parallel signals into high-speed serial signals at a transmitting end, transmits the high-speed serial signals to a receiving end through media such as light or copper, and then converts the serial signals into low-speed parallel signals at the receiving end again. The SERDES mainly applies a differential signal transmission technology, has the advantages of low power consumption, strong interference resistance and high speed, and is embedded with a clock in a differential signal, so that the SERDES plays an important role in the process of improving the communication transmission rate.

Full duplex communication refers to the simultaneous presence of signals transmitted in both directions at any time during communication, i.e., the simultaneous transmission and reception of signals is supported.

Since the number of cables is an important factor to be considered for reducing the cost of the communication network in the vehicle, combining SERDES transmission with full-duplex communication may be considered to convert a data transmission mode in which one transmission line transmits a signal and one transmission line receives a signal into a full-duplex communication mode in which one transmission line simultaneously transmits and receives a signal, thereby reducing the number of cables required in the communication network.

However, when the SERDES is used for full duplex communication, if the transmitting end and the receiving end of both communication parties respectively use independent clock sources, that is, the clock frequencies of the signals transmitted in both directions are not synchronous, so that full duplex communication cannot be realized.

Disclosure of Invention

The application provides a full-duplex communication method which can realize full-duplex communication under the condition that clock frequencies of signals transmitted in two directions are not synchronous.

In a first aspect, an embodiment of the present application provides a full duplex communication method. The method may employ a full duplex communication system, which may include a first interface device and a second interface device, with full duplex communication between the first interface device and the second interface device. The full duplex communication method comprises the following steps: the first interface device acquires a first serial signal of a first communication device, wherein the first serial signal is adapted to a first clock frequency; the first interface device carries out first clock frequency conversion on the first serial signal to obtain a second serial signal, wherein the second serial signal is adaptive to a second clock frequency which is greater than the first clock frequency; the first interface device sends the second serial signal to a second interface device; the second interface device carries out second clock frequency conversion on the second serial signal to obtain the first serial signal; the second interface device acquires a third serial signal of the second communication device, wherein the third serial signal is adapted to the second clock frequency; the second interface device sends the third serial signal to the first interface device.

When the second clock frequency is higher than the first clock frequency, the first serial signal and the third serial signal transmitted in the two transmission directions are not synchronous, so that full duplex communication cannot be performed.

By adopting the full-duplex communication method provided by the embodiment of the application, the first interface device performs the first clock frequency conversion on the first serial signal of the first communication device, which is adapted to the first clock frequency, so as to obtain the second serial signal, which is adapted to the second clock frequency. In this way, the second serial signal and the third serial signal transmitted in both transmission directions are adapted to the same second clock frequency, so that clock frequency synchronization is achieved. Therefore, the second interface device can cancel the echo of the third signal from the received signal based on the second clock frequency, recover the second serial signal, and recover the first serial signal by performing the second clock frequency conversion on the second serial signal, thereby enabling full duplex communication.

In one possible implementation, the first serial signal may be a differential signal.

Optionally, the first interface device may acquire the first serial signal in various ways, which is not limited in this embodiment of the application.

In a possible implementation, the first interface device may receive the first serial signal from the first communication device.

Accordingly, the first communication device determines a plurality of first parallel signals to be transmitted; performing parallel-to-serial conversion on the plurality of first parallel signals to obtain a first serial signal; and transmitting the first serial signal to the first interface apparatus.

In another possible implementation, the first interface means may receive a plurality of first parallel signals from the first communication means; the plurality of first parallel signals are subjected to parallel-to-serial conversion to obtain the first serial signal.

Accordingly, the first communication device determines a plurality of first parallel signals to be transmitted; and transmitting the plurality of first parallel signals to the first interface device.

That is, the process of parallel-to-serial conversion may be performed by the first communication apparatus or by the first interface apparatus.

In a possible implementation manner, when the first serial signal is a signal transmitted within a first transmission time, the first interface device may determine the first number according to the second clock frequency and the first clock frequency; the first number of first signals is added to the first serial signal to obtain the second serial signal.

In a possible implementation, the first interface means may determine the first number according to a difference between the second clock frequency and the first transmission time.

In a possible implementation manner, the first interface device may add the first number of the first signals to the first serial signal according to a first conversion parameter to obtain the second serial signal, where the first conversion parameter includes at least one of a signal type of the first signal or an addition position of each of the first signals.

Optionally, the first interface device may add the first number of first signals at a plurality of positions in the first serial signal, which is not limited in this embodiment of the application.

In a first possible implementation, the first interface means may add the first number of first signals before the start position of the first serial signal.

In a second possible implementation, the first interface means may add the first number of first signals after the end position of the first serial signal.

In a third possible implementation, the first interface means may add the first number of first signals at any position between a start position and an end position of the first serial signal.

Optionally, the first signal may be of multiple signal types, which is not limited in this application.

In a first possible implementation, the first signal may be an idle symbol.

In a second possible implementation, the first signal may be a predefined other symbol.

Optionally, the first interface device may pre-configure the first conversion parameter in various ways, which is not limited in this embodiment of the application.

In a first possible implementation, the first conversion parameter may be predefined in the transport protocol.

In a second possible implementation, the first interface device may send the first conversion parameter to the second interface device before signal transmission.

In a third possible implementation, the first interface device may pre-configure the first conversion parameter before factory shipment.

Optionally, the first interface device may acquire the second clock frequency in various ways, which is not limited in this embodiment of the application.

In a possible implementation manner, the first interface device may perform frequency modulation on the first clock frequency to obtain the second clock frequency; alternatively, the first interface means may obtain the second clock frequency provided by the first clock source.

In one possible implementation, the second interface device may receive a second interface signal, the second interface signal including echo signals of the second serial signal and the third serial signal; and canceling the echo signal of the third serial signal from the second interface signal to obtain the second serial signal.

In a possible implementation, the second interface means may determine the first number according to the second clock frequency and the first clock frequency; the first number of first signals is deleted from the second serial signal to obtain the first serial signal.

In a possible implementation, the second interface device may delete the first number of the first signals from the second serial signal according to a first conversion parameter, resulting in the first serial signal, the first conversion parameter including at least one of a signal type of the first signal or an addition position of each of the first signals.

It should be noted that the second clock frequency conversion can be understood as the reverse process of the first clock frequency conversion, that is, the first interface device obtains the second serial signal by adding a first number of first signals to the first serial signal, and then the second interface device obtains the first serial signal in the opposite way, that is, by deleting the first number of first signals from the second serial signal, wherein the first interface device and the second interface device need to unify the signal types and adding positions of the first number of first signals. To avoid repetition, further description is omitted here.

Optionally, the second interface device may pre-configure the first conversion parameter in various ways, which is not limited in this embodiment of the application.

In a second possible implementation, the second interface device may receive the first conversion parameter from the first interface device before signal transmission.

In a third possible implementation, the second interface device may pre-configure the first conversion parameter before factory shipment.

In one possible implementation, the third serial signal may be a differential signal.

Optionally, the second interface device may acquire the third serial signal in various ways, which is not limited in this embodiment of the application.

In a possible implementation, the second interface device may receive the third serial signal from the second communication device.

Accordingly, the second communication device determines a plurality of second parallel signals to be transmitted; performing parallel-to-serial conversion on the plurality of second parallel signals to obtain a third serial signal; and transmits the third serial signal to the second interface device.

In another possible implementation, the second interface means may receive a plurality of second parallel signals from the second communication means; and performing parallel-to-serial conversion on the plurality of second parallel signals to obtain the third serial signal.

Accordingly, the second communication device determines a plurality of second parallel signals to be transmitted; and transmitting the plurality of second parallel signals to the second interface device.

That is, the process of parallel-to-serial conversion may be performed by the second communication apparatus or by the second interface apparatus.

In one possible implementation, the first interface device may receive a first interface signal, the first interface signal including the third serial signal and an echo signal of the second serial signal; and cancelling the echo signal of the second serial signal from the first interface signal to obtain the third serial signal.

Optionally, the method may further include: the first interface device transmits the third serial signal to the first communication device.

Optionally, the first interface device may send the third serial signal to the first communication device in a variety of ways, which is not limited in this embodiment of the present application.

In a possible implementation, the first interface device may send the third serial signal directly to the first communication device.

Accordingly, the first communication device receives the third serial signal from the first interface device; and performing serial-to-parallel conversion on the third serial signals to obtain a plurality of second parallel signals.

In another possible implementation manner, the first interface device may perform serial-to-parallel conversion on the third serial signal to obtain the plurality of second parallel signals, and send the plurality of second parallel signals to the first communication device.

Accordingly, the first communication device receives the plurality of second parallel signals from the first interface device.

That is, the process of serial-to-parallel conversion may be performed by the first interface apparatus or by the first communication apparatus.

Optionally, the method may further include: the second interface device sends the first serial signal to the second communication device.

Optionally, the second interface device may send the first serial signal to the second communication device in various ways, which is not limited in this embodiment of the present application.

In a possible implementation, the second interface device may send the first serial signal directly to the second communication device.

Accordingly, the second communication device receives the first serial signal from the second interface device; and performing serial-to-parallel conversion on the first serial signals to obtain a plurality of first parallel signals.

In another possible implementation manner, the second interface device may perform serial-to-parallel conversion on the first serial signal to obtain a plurality of first parallel signals; transmitting the plurality of first parallel signals to the second communication device.

That is, the process of serial-to-parallel conversion may be performed by the second communication apparatus or by the second interface apparatus.

Optionally, the acquiring, by the second interface device, the third serial signal of the second communication device may include: the second interface device acquires a fourth serial signal of the second communication device, wherein the fourth serial signal is adapted to a third clock frequency, the third clock frequency is different from the first clock frequency, and the second clock frequency is greater than the third clock frequency; and the second interface device performs third clock frequency conversion on the fourth serial signal to obtain the third serial signal.

In a possible implementation, the second interface means may determine a second number according to the second clock frequency and the third clock frequency; and adding the second number of second signals to the fourth serial signal to obtain the third serial signal.

In a possible implementation manner, the second interface device may add the second number of second signals to the fourth serial signal according to a second conversion parameter to obtain the third serial signal, where the second conversion parameter includes at least one of a signal type of the second signal or an addition position of each of the second signals.

It should be noted that the process of performing the third clock frequency conversion on the fourth serial signal by the second interface device is similar to the process of performing the first clock frequency conversion on the first serial signal by the interface device, and the process of performing the first clock frequency conversion may be referred to, and is not repeated herein to avoid repetition.

Accordingly, the first interface device may perform a fourth clock frequency conversion on the third serial signal to obtain the fourth serial signal.

In a possible implementation, the first interface means may determine a second number according to the second clock frequency and the third clock frequency; and deleting the second number of second signals from the third serial signals to obtain the fourth serial signals.

In a possible implementation manner, the first interface device may delete the second number of the second signals from the third serial signal according to a second conversion parameter, so as to obtain the fourth serial signal, where the second conversion parameter includes at least one of a signal type of the second signals or an addition position of each of the second signals.

Optionally, the first interface device sends the third serial signal to the first communication device, and may be replaced with: the first interface device transmits the fourth serial signal to the first communication device.

Since the first serial signal sent by the first communication device to the second communication device is adapted to the first clock frequency, and the fourth serial signal sent by the second communication device to the first communication device is adapted to the third clock frequency, when the first clock frequency is different from the third clock frequency, the clock frequencies adapted to the first serial signal and the fourth serial signal transmitted in the two transmission directions are not synchronous, so that full duplex communication cannot be performed.

By adopting the full-duplex communication method provided by the embodiment of the application, the first interface device can obtain the second serial signal adapted to the second clock frequency by performing the first clock frequency conversion on the first serial signal adapted to the first clock frequency of the first communication device, and similarly, the second interface device can obtain the third serial signal adapted to the second clock frequency by performing the third clock frequency conversion on the fourth serial signal adapted to the third clock frequency of the second communication device. In this way, the second serial signal and the third serial signal transmitted in both transmission directions are adapted to the same second clock frequency, so that clock frequency synchronization is achieved. Therefore, the second interface device can cancel the echo of the third signal from the received signal based on the second clock frequency, recover the second serial signal, and recover the first serial signal by performing the second clock frequency conversion on the second serial signal, and similarly, the first interface device can cancel the echo of the second signal from the received signal based on the second clock frequency, recover the third serial signal, and recover the fourth serial signal by performing the fourth clock frequency conversion on the third serial signal, thereby enabling full duplex communication.

In a second aspect, an embodiment of the present application further provides a full duplex communication method. The method may be applied to a full duplex communication system comprising a first interface device and a second interface device, the first interface device and the second interface device performing full duplex communication therebetween. The method comprises the following steps: the first interface device acquires a first serial signal of a first communication device, wherein the first serial signal is adapted to a first clock frequency; the first interface device carries out first clock frequency conversion on the first serial signal to obtain a second serial signal, wherein the second serial signal is adaptive to a second clock frequency which is greater than the first clock frequency; the first interface device sends the second serial signal to the second interface device; the first interface device receives a third serial signal from the second interface device, the third serial signal being adapted to the second clock frequency.

In a possible implementation manner, the first serial signal is a signal transmitted in a first transmission time, and the first interface device performs a first clock frequency conversion on the first serial signal to obtain a second serial signal, including: the first interface device determines a first number according to the second clock frequency and the first clock frequency; the first interface device adds the first number of first signals to the first serial signal to obtain the second serial signal.

In a possible implementation manner, the first interface device adds the first number of first signals to the first serial signal to obtain the second serial signal, and includes: the first interface device adds the first number of the first signals to the first serial signal according to a first conversion parameter to obtain the second serial signal, wherein the first conversion parameter includes at least one of a signal type of the first signal or an adding position of each first signal.

In a possible implementation manner, the third serial signal is obtained by performing a third clock frequency conversion on a fourth serial signal of the second communication device, the fourth serial signal is adapted to a third clock frequency, the third clock frequency is different from the first clock frequency, and the second clock frequency is greater than the third clock frequency, the method further includes: the first interface device performs fourth clock frequency conversion on the third serial signal to obtain the fourth serial signal.

In a possible implementation manner, the third serial signal is a signal transmitted within the second transmission time, and the first interface device performs a fourth clock frequency conversion on the third serial signal to obtain the fourth serial signal, including: the first interface device determines a second number according to the second clock frequency and the third clock frequency; the first interface device deletes the second number of second signals from the third serial signal to obtain the fourth serial signal.

In a possible implementation manner, the deleting, by the first interface device, the second number of second signals from the third serial signal to obtain the fourth serial signal includes: the first interface device deletes the second number of the second signals from the third serial signals according to a second conversion parameter to obtain the fourth serial signals, wherein the second conversion parameter includes at least one of a signal type of the second signals or an adding position of each second signal.

In one possible implementation, the second clock frequency is obtained by frequency modulating the first clock frequency; alternatively, the second clock frequency is provided by the first clock source.

In a third aspect, an embodiment of the present application further provides a full duplex communication method. The method may be applied to a full duplex communication system comprising a first interface device and a second interface device, the first interface device and the second interface device performing full duplex communication therebetween. The method comprises the following steps: the second interface device acquires a third serial signal of the second communication device, wherein the third serial signal is adapted to the second clock frequency; the second interface device sends the third serial signal to the first interface device; the second interface device receives a second serial signal from the first interface device, the second serial signal is obtained by performing first clock frequency conversion on a first serial signal of a first communication device, the first serial signal is adapted to a first clock frequency, the second serial signal is adapted to a second clock frequency, and the second clock frequency is greater than the first clock frequency; the second interface device performs second clock frequency conversion on the second serial signal to obtain the first serial signal.

In a possible implementation manner, the second serial signal is a signal transmitted in a first transmission time, and the second interface device performs a second clock frequency conversion on the second serial signal to obtain the first serial signal, including: the second interface device determines a first number according to the second clock frequency and the first clock frequency; the second interface device deletes the first number of first signals from the second serial signal to obtain the first serial signal.

In a possible implementation manner, the second interface device deletes the first number of first signals from the second serial signal to obtain the first serial signal, including: the second interface device deletes the first number of the first signals from the second serial signal according to a first conversion parameter, so as to obtain the first serial signal, wherein the first conversion parameter comprises at least one of a signal type of the first signals or an adding position of each first signal.

In one possible implementation manner, the acquiring, by the second interface device, the third serial signal of the second communication device includes: the second interface device acquires a fourth serial signal of the second communication device, wherein the fourth serial signal is adapted to a third clock frequency, the third clock frequency is different from the first clock frequency, and the second clock frequency is greater than the third clock frequency; and the second interface device performs third clock frequency conversion on the fourth serial signal to obtain the third serial signal.

In a possible implementation manner, the fourth serial signal is a signal transmitted within a second transmission time, and the second interface device performs a third clock frequency conversion on the fourth serial signal to obtain the third serial signal, including: the second interface means determining a second number based on the second clock frequency and the third clock frequency; the second interface device adds the second number of second signals to the fourth serial signal to obtain the third serial signal.

In a possible implementation manner, the adding, by the second interface device, the second number of second signals to the fourth serial signal to obtain the third serial signal includes: the second interface device adds the second number of second signals to the fourth serial signal according to a second conversion parameter to obtain the third serial signal, wherein the second conversion parameter includes at least one of a signal type of the second signal or an adding position of each second signal.

In a fourth aspect, an embodiment of the present application further provides an interface apparatus for full duplex communication, where the apparatus includes means for implementing the method described in the second aspect or various possible implementations of the second aspect.

In a fifth aspect, an embodiment of the present application further provides an interface apparatus for full duplex communication, where the apparatus includes means for implementing the method described in the third aspect or various possible implementations of the third aspect.

In a sixth aspect, an embodiment of the present application further provides a full-duplex communication system, where the system includes the interface apparatus described in the fourth aspect and the interface apparatus described in the fifth aspect.

In a seventh aspect, an embodiment of the present application further provides a full-duplex communication apparatus, where the apparatus includes a first interface and a second interface, and full-duplex communication is performed between the first interface and the second interface through a transmission line, where the first interface is used to implement the method in the foregoing second aspect or various possible implementation manners of the second aspect, and the second interface is used to implement the method in the foregoing third aspect or various possible implementation manners of the third aspect.

In an eighth aspect, an embodiment of the present application further provides a chip apparatus, including: at least one processor and a memory, the at least one processor being configured to execute code in the memory, wherein when the at least one processor executes the code, the chip apparatus implements the method described in the second aspect or the various possible implementations of the second aspect or the method described in the third aspect or the various possible implementations of the third aspect.

In a ninth aspect, this embodiment of the present application further provides a computer-readable storage medium for storing a computer program, where the computer program includes instructions for implementing the method described in the second aspect or the various possible implementations of the second aspect, or the method described in the third aspect or the various possible implementations of the third aspect.

In a tenth aspect, the present application further provides a computer program product, where the computer program product includes instructions, and when the instructions are run on a computer or a processor, the computer or the processor is caused to implement the method described in the foregoing second aspect or various possible implementations of the second aspect, or the method described in the foregoing third aspect or various possible implementations of the third aspect.

Drawings

FIG. 1 is a schematic diagram of the operation of a conventional serializer/deserializer transmission;

fig. 2 is a schematic diagram of the operation principle of a conventional full-duplex communication system;

fig. 3 is a schematic flow chart of a full-duplex communication method 100 provided by an embodiment of the present application;

fig. 4 is a schematic block diagram of a full-duplex communication system 200 provided by an embodiment of the present application;

fig. 5 is another schematic block diagram of a full-duplex communication system 200 provided by an embodiment of the present application;

fig. 6 is a schematic block diagram of an interface device 300 provided in an embodiment of the present application;

FIG. 7 is a schematic block diagram of an interface apparatus 400 provided by an embodiment of the present application;

fig. 8 is a schematic block diagram of a chip 500 provided in an embodiment of the present application.

Detailed Description

For clarity, some of the nomenclature referred to in the examples of this application will be described first.

1、SERDES

The SERDES means that at a transmitting end, a plurality of low-speed parallel signals are converted into a high-speed serial signal by a serializer, and the high-speed serial signal is transmitted to a receiving end through a transmission line (such as a cable); accordingly, at the receiving end, the high-speed serial signal is converted into a plurality of low-speed parallel signals again by the deserializer.

For example: figure 1 shows a schematic diagram of the working principle of SERDES transmission. Fig. 1 includes a process of transmitting a signal and a process of receiving a signal.

In the process of sending the signals, at a first sending end, the

parallel signals

1 and 2 are converted into serial signals 1 by a serializer, and are transmitted to a second receiving end through a first transmission line; accordingly, at the first receiving end, the serial signal 1 is converted into

parallel signals

1 and 2 by the deserializer.

In the process of receiving the signals, the

parallel signals

3 and 4 are converted into serial signals 2 by the serializer at the second transmitting end and are transmitted to the second receiving end through the second transmission line; correspondingly, at the second receiving end, the serial signal 1 is converted again into

parallel signals

3 and 4 by the deserializer.

It should be noted that clock timing is also very important for applications using a serializer, and the SERDES embeds clocks in signals, so that all components including a transmitting end and a receiving end can realize clock synchronization according to the clocks embedded in the signals. In addition, the SERDES mainly applies a differential signal transmission technology and has the advantages of low power consumption, strong interference resistance and high speed.

2. Full duplex communication system

A full-duplex communication system refers to a communication system in which signals transmitted in both directions coexist at any time during communication, that is, a communication system supporting simultaneous transmission and reception of data is supported.

For example: fig. 2 shows a schematic diagram of the operation of a full-duplex communication system, which comprises a first communication device, a second communication device, a first interface device and a second interface device, as shown in fig. 2. The first communication device comprises a first sending end and a first receiving end, the second communication device comprises a second sending end and a second receiving end, the first interface device comprises a first interface module, a second interface module and a first mixing module, and the second interface device comprises a third interface module, a fourth interface module and a second mixing module. The first sending module is electrically connected with the first interface module, the first receiving module is electrically connected with the second interface module, the second sending module is electrically connected with the third interface module, the second receiving module is electrically connected with the fourth interface module, and the first mixing module is connected with the second mixing module through a transmission line for full-duplex communication.

The first interface module is used for receiving a first signal from the first sending module, and the first signal is adapted to a first clock frequency; the first signal is sent to the first mixing module.

The first mixing module is used for receiving the first signal from the first interface module and sending the first signal to the second mixing module through the transmission line.

The third interface module is used for receiving a third signal from the second sending module, and the third signal is adapted to the first clock frequency; the third signal is sent to the second mixing module.

The second mixing module is used for receiving the third signal from the third interface module and sending the third signal to the first mixing module through the transmission line.

The first mixing module is further configured to receive a first interface signal through the transmission line, the first interface signal including the third signal from the second mixing module and an echo signal of the first signal; cancelling an echo signal of the first signal from the first interface signal based on the first clock frequency to obtain a third signal; and sending the third signal to the first receiving module.

The second mixing module is further configured to receive a second interface signal through the transmission line, the second interface signal including echo signals of the first signal and the third signal from the first mixing module; cancelling the echo signal of the third signal from the second interface signal based on the first clock frequency to obtain the first signal; and sending the first signal to the second receiving module.

It should be noted that, because the transmission line has the first signal and the third signal that are transmitted in two directions, an echo signal may be generated in each transmission direction during transmission through the transmission line, so that the signals received by the mixing module include both the received signal and the transmitted signal, that is, the echo signal of the transmitted signal and the received signal are superimposed together. Therefore, echo cancellation techniques may be used to cancel the echo signal of the transmitted signal in each transmission direction and recover the received signal, and the echo cancellation techniques use a premise that clock frequency synchronization of signal adaptation in both transmission directions is required.

3. Clock frequency

The clock frequency is the same concept as the data transfer rate, and is given in Hertz (HZ) and the data transfer rate is given in bits per second (bit/s).

For example: the data transmission rate is 100kbit/s, which means that 100kbit can be transmitted in 1 second, and if only 1bit of data can be transmitted by 1 clock pulse, 100kbit of data needs to be transmitted in 1 second, that is, the period T of each clock pulse is 1/100000 us 10 us.

The number of repeated changes of the square wave in 1 second is referred to as "frequency" of the signal, and is denoted by F, and the time required for the waveform of the signal to change once is referred to as "period" of the signal, and is denoted by T, and is expressed in seconds. The frequency and period have the following relationship: f is 1/T.

Therefore, if the clock period is 10us, i.e. 0.00001s, the corresponding clock frequency F is 1/T is 1/0.00001s is 100000 HZ is 100 kZH.

In summary, HZ and bit/s are one and the same concept.

For example: if the clock period is 1HZ, the rate of transmitting data is 1 bit/s; the clock period is 100kHZ, the rate of transmitting data is 100 kbit/s.

In a communication network in a vehicle, in order to reduce wiring complexity, it is desirable to reduce the number of transmission lines while saving costs, and it is possible to combine SERDES transmission with full duplex communication, i.e., to convert a transmission mode in which a signal is transmitted through a first transmission line and received through a second transmission line in SERDES transmission into a transmission mode in which bidirectional signals are simultaneously transmitted through a transmission line for full duplex communication.

However, in SERDES transmission, the transmission process and the reception process of a signal are generally asynchronous, that is, the two-way transmitted signal adapts to different clock frequencies, in this case, if the SERDES transmission is applied to a full-duplex communication system, which may cause the clock frequencies of the signal adaptations in different transmission directions to be asynchronous, it will be impossible to cancel the echo signal of the transmitted signal from the received signal by using echo cancellation technology and recover the received signal, and therefore, full-duplex communication cannot be achieved.

Fig. 3 shows a schematic flow chart of a full-duplex communication method 100 provided by the embodiment of the present application. The method 100 may be applied to a full duplex communication system, which may include a first interface device and a second interface device, between which full duplex communication is performed.

S110, the first interface device obtains a first serial signal of a first communication device, where the first serial signal is adapted to a first clock frequency.

S120, the first interface device performs a first clock frequency conversion on the first serial signal to obtain a second serial signal, where the second serial signal is adapted to a second clock frequency, and the second clock frequency is greater than the first clock frequency.

For example: the first clock frequency is 500Hz, the second clock frequency is 800Hz, the difference between the second clock frequency and the first intermediate frequency is 300Hz, and the transmission rate corresponding to the difference is 300 bits/s. When the first transmission time is 1s, the first quantity is 300 bits; when the first transmission time is 10ms, the first number is 3 bits.

That is, taking the first transmission time as 1s as an example, in the first transmission time, only 500bits can be transmitted based on the first clock frequency, and now since the adapted clock frequency is increased from the first clock frequency to the second clock frequency, 300bits more need to be transmitted in the first transmission time to satisfy 800bits/s corresponding to the second clock frequency.

For example: the first number is 5, the first serial signal is [ signal 1, signal 2, signal 3, signal 4, signal 5, signal 6, signal 7, signal 8, signal 9, signal 10] for example, and the second serial signal may be [ first signal 1, first signal 2, first signal 3, first signal 4, first signal 5, signal 1, signal 2, signal 3, signal 4, signal 5, signal 6, signal 7, signal 8, signal 9, signal 10 ].

For example: the first number is 5, the first serial signal is [ signal 1, signal 2, signal 3, signal 4, signal 5, signal 6, signal 7, signal 8, signal 9, signal 10] for example, and the second serial signal may be [ signal 1, signal 2, first signal 1, signal 3, signal 4, first signal 2, signal 5, signal 6, first signal 3, signal 7, signal 8, first signal 4, signal 9, signal 10, first signal 5 ].

In a first possible implementation, the first signal may be an idle symbol.

S130, the first interface device sends the second serial signal to the second interface device; accordingly, the second interface device receives the second serial signal from the first interface device.

S140, the second interface device performs a second clock frequency conversion on the second serial signal to obtain the first serial signal.

S150, the second interface device obtains a third serial signal of the second communication device, the third serial signal being adapted to the second clock frequency.

S160, the second interface device sends the third serial signal to the first interface device; accordingly, the first interface device receives the third serial signal from the second interface device.

It should be noted that the execution order of S110 to S140 and S150 to S160 is not sequential.

Optionally, in S150, the acquiring, by the second interface device, the third serial signal of the second communication device may include: the second interface device acquires a fourth serial signal of the second communication device, wherein the fourth serial signal is adapted to a third clock frequency, the third clock frequency is different from the first clock frequency, and the second clock frequency is greater than the third clock frequency; and the second interface device performs third clock frequency conversion on the fourth serial signal to obtain the third serial signal.

The full-duplex communication method 100 provided by the embodiment of the present application is described above with reference to fig. 3, and a full-duplex communication system to which the method 100 is applied will be described below.

Fig. 4 illustrates a full-duplex communication system 200 provided by an embodiment of the present application. As shown in fig. 4, the full duplex communication system 200 includes a first communication device 210, a second communication device 220, a first interface device 230 of the first communication device 210, and a second interface device 240 of the second communication device 220, and the first interface device 230 and the second interface device 240 perform full duplex communication.

The first communication device 210 includes a first transmitting module 211 and a first receiving module 212, the second communication device 220 includes a second transmitting module 221 and a second receiving module 222, the first interface device 230 includes a first interface module 231, a first processing module 232, a first mixing module 233, a second processing module 234 and a second interface module 235, and the second interface device 240 includes a second interface module 241, a third processing module 242, a second mixing module 243, a fourth processing module 244 and a fourth interface module 245.

It should be noted that fig. 4 only schematically illustrates that the first interface device 230 and the first communication device 210 are two independent devices, and the second interface device 240 and the second communication device 220 are two independent devices, respectively, but the embodiment of the present invention is not limited thereto.

Alternatively, the first interface device 230 may be integrated in the first communication device 210, that is, the first interface module 231 and the first sending module 211 may be understood as a same module, and the second interface module 235 and the first receiving module 212 may be understood as a same module. Similarly, the second interface device 240 may be integrated in the second communication device 220, that is, the third interface module 241 and the second sending module 221 may be understood as a same module, and the fourth interface module 245 and the second receiving module 222 may be understood as a same module, which is not limited in this embodiment of the application.

It should be noted that the above devices may be understood as virtual devices or physical devices, and the above integration may be logical integration or physical integration.

First, a process in which the first communication apparatus 210 transmits the first serial signal to the second communication apparatus 220 through the system 200 will be described.

The first sending module 211 is configured to send a first serial signal to the first interface module 231, where the first serial signal is adapted to the first clock frequency, as shown in step (1) in fig. 4.

The first interface module 231 is used for receiving the first serial signal from the first sending module 211; the first serial signal is sent to the first processing module 232, as shown in step (2) of fig. 4.

It should be noted that the above process may refer to S110 in the method embodiment.

The first processing module 232 is configured to receive the first serial signal from the first interface module 231; performing a first clock frequency conversion on the first serial signal to obtain a second serial signal, where the second serial signal is adapted to a second clock frequency, and the second clock frequency is greater than the first clock frequency, as shown in step (3) in fig. 4; the second serial signal is sent to the first mixing module 233, as in step (4) of fig. 4.

In one possible implementation, as shown in fig. 5, the first processing module 232 may include a first clock adaptation module 232-1 and a first obtaining module 232-2. The first clock adaptation module 232-1 is used for receiving the first serial signal from the first interface module 231; determining a first number according to the first clock frequency and the second clock frequency, as in step (3-1) of fig. 5; the first serial signal and the first amount of information are sent to the first obtaining module 232-2, as in step (3-2) of fig. 5. The first obtaining module 232-2 is configured to receive the first serial signal and the first amount of information from the first clock adaptation module 232-1; adding the first number of first signals to the first serial signal to obtain the second serial signal, as shown in step (3-3) of fig. 5; the second serial signal is sent to the first mixing module 233.

It should be noted that, the first clock frequency conversion process may refer to S120 in the method embodiment.

The first mixing module 233 is configured to receive the second serial signal sent by the first processing module 232 and send the second serial signal to the second mixing module 243, as shown in step (5) of fig. 4.

It should be noted that the above process may refer to S130 in the method embodiment.

The second mixing module 243 is configured to receive a second interface signal from the first mixing module 233, where the second interface signal includes the second serial signal and an echo signal of a third serial signal (the process of obtaining the third serial signal will be described below); canceling the echo signal of the third serial signal from the second interface signal to obtain the second serial signal, as shown in step (6) in fig. 4; the second serial signal is sent to the fourth processing module 244, as shown in step (7) of fig. 4.

The fourth processing module 244 is configured to receive the second serial signal from the second mixing module 243; performing a second clock frequency conversion on the second serial signal to obtain the first serial signal, as shown in step (8) in fig. 4; the first serial signal is sent to the fourth interface module 245, as shown in step (9) of fig. 4.

In one possible implementation, as shown in fig. 5, the fourth processing module 244 may include a fourth clock adaptation module 244-1 and a fourth obtaining module 244-2. The fourth clock adaptation module 244-1 is configured to receive the second serial signal from the second mixing module 243; determining a first number based on the first clock frequency and the second clock frequency, as in step (8-1) of FIG. 5; the second serial signal and the first amount of information are sent to the fourth obtaining module 244-2, as in step (8-2) of FIG. 5. The fourth obtaining module 244-2 is used for receiving the second serial signal and the first amount of information from the fourth clock adaptation module 244-1; deleting the first number of first signals from the second serial signal to obtain the first serial signal, as shown in step (8-3) of fig. 5; the first serial signal is sent to the fourth interface module 245.

It should be noted that, the second clock frequency conversion process may refer to S140 in the method embodiment.

The fourth interface module 245 is configured to receive the first serial signal from the fourth processing module 244 and send the first serial signal to the second receiving module 222, as shown in step (10) of fig. 4.

The second receiving module 222 is used for receiving the first serial signal from the fourth interface module 245.

The process of the second communication device 220 transmitting the fourth serial signal to the first communication device 210 through the system 200 will be described.

The second sending module 221 is configured to send a fourth serial signal to the third interface module 241, where the fourth serial signal is adapted to a third clock frequency, the third clock frequency is different from the first clock frequency, and the second clock frequency is greater than the third clock frequency, as shown in step (11) in fig. 4.

The third interface module 241 is used for receiving the fourth serial signal from the first sending module 221; the fourth serial signal is sent to the third processing module 242, as in step (12) of fig. 4.

The third processing module 242 is configured to receive the fourth serial signal from the first interface module 241; performing a third clock frequency conversion on the fourth serial signal to obtain a third serial signal, wherein the third serial signal is adapted to the second clock frequency, as shown in step (13) in fig. 4; the third serial signal is sent to the second mixing module 243, as in step (14) of fig. 4.

In one possible implementation, as shown in fig. 5, the third processing module 242 may include a third clock adaptation module 242-1 and a third obtaining module 242-2. The third clock adaptation module 242-1 is used for receiving the fourth serial signal from the third interface module 241; determining a second number according to the third clock frequency and the second clock frequency, as shown in step (13-1) of FIG. 5; the fourth serial signal and the second amount of information are sent to the third obtaining module 242-2, as in step (13-2) of fig. 5. The third obtaining module 242-2 is used for receiving the fourth serial signal and the second amount of information from the third clock adapting module 242-1; adding the second number of first signals to the fourth serial signal to obtain the third serial signal, as shown in step (13-3) of fig. 5; the third serial signal is sent to the second mixing module 243.

It should be noted that, the third clock frequency conversion process described above may refer to the related embodiment of S150 in the method embodiment.

The second mixing module 243 is configured to receive the third serial signal sent by the third processing module 242 and send the third serial signal to the first mixing module 233, as shown in step (15) in fig. 4.

The first mixing module 233 is configured to receive a first interface signal from the second mixing module 243, where the first interface signal includes the third serial signal and an echo signal of the second serial signal; canceling the echo signal of the second serial signal from the first interface signal to obtain the third serial signal, as shown in step (16) of fig. 4; the third serial signal is sent to the second processing module 234, as shown in step (17) of fig. 4.

It should be noted that the above process may refer to the related embodiment of S160 in the method embodiment.

The second processing module 234 is configured to receive the third serial signal from the first mixing module 233; performing a fourth clock frequency conversion on the third serial signal to obtain a fourth serial signal, as shown in step (18) in fig. 4; the fourth serial signal is sent to the second interface module 235, as in step (19) of fig. 4.

In one possible implementation, as shown in fig. 5, the second processing module 234 may include a second clock adaptation module 234-1 and a second obtaining module 234-2. The second clock adaptation module 234-1 is for receiving the third serial signal from the first mixing module 233; determining a second number based on the third clock frequency and the second clock frequency, as in step (18-1) of FIG. 5; the third serial signal and the second amount of information are sent to the second obtaining module 234-2, as in step (18-2) of FIG. 5. The second obtaining module 234-2 is used for receiving the third serial signal and the second amount of information from the second clock adapting module 234-1; deleting the second number of second signals from the third serial signal to obtain the fourth serial signal, as shown in step (18-3) of fig. 5; the fourth serial signal is sent to the second interface module 235.

It should be noted that, the fourth clock frequency conversion process described above may refer to the related embodiment of S150 in the method embodiment.

The fourth interface module 235 is configured to receive the fourth serial signal from the second processing module 234 and send the fourth serial signal to the first receiving module 212, as shown in step (20) of fig. 4.

The first receiving module 212 is used for receiving the fourth serial signal from the second interface module 235.

In a possible implementation manner, as shown in fig. 5, the first interface device 130 may further include a first clock recovery module 236, a clock source 237, and a first frequency modulation module 238.

The first clock recovery module 236 is used to recover the first clock frequency adapted to the first serial signal from the first serial signal received by the first interface module 231 and provide the first clock frequency to the first clock adaptation module 232-1.

The clock source 237 is used for providing a second clock frequency for the first clock adaptation module 232-1, the first obtaining module 232-2, the first mixing module 233, the second clock adaptation module 234-1 and the first frequency modulation module 238.

The first frequency modulation module 238 is configured to perform frequency modulation on the second clock frequency provided by the clock source 237 to obtain the third clock frequency, and provide the third clock frequency for the second clock adaptation module 234-1, the second obtaining module 234-2 and the second interface module 235.

In a possible implementation manner, the function of the clock source 237 can also be implemented by the first fm module 237, and the first clock recovery module 236 is further configured to provide the first clock frequency for the first fm module 237. The first frequency modulation module 238 is configured to perform frequency modulation on the first clock frequency provided by the first clock recovery module 236 to obtain the second clock frequency and the third clock frequency, provide the second clock frequency for the first clock adaptation module 232-1, the first obtaining module 232-2, the first mixing module 233, and the second clock adaptation module 234-1, and provide the third clock frequency for the second clock adaptation module 234-1, the second obtaining module 234-2, and the second interface module 235.

Alternatively, the first clock recovery module 236 may be implemented by hardware or software, which is not limited in this embodiment of the application.

In one possible implementation, when the first clock recovery module 236 is implemented by hardware, the first clock recovery module 236 may include a first clock recovery circuit.

Alternatively, the clock source 237 may be implemented by hardware or software, which is not limited in this embodiment of the present application.

In one possible implementation, when the clock source 237 is implemented by hardware, the clock source 237 may include a first clock circuit.

Alternatively, the first frequency modulation module 238 may be implemented by hardware or software, which is not limited in this embodiment of the present application.

In one possible implementation, when the first frequency modulation module 238 is implemented by hardware, the first frequency modulation module 238 may include a first frequency modulation circuit.

In one possible implementation, the second interface device 240 may further include a second clock recovery module 246, a third clock recovery module 247, and a second frequency modulation module 248.

The second clock recovery module 246 is used for recovering the third clock frequency adapted to the fourth signal from the fourth signal received by the third interface module 241, and providing the third clock frequency for the third clock adaptation module 242-1.

The third clock recovery module 247 is configured to recover the second clock frequency adapted to the second serial signal from the second interface signal received by the second mixing module 243, and provide the second clock frequency for the third clock adaptation module 242-1, the third obtaining module 242-2, the fourth clock adaptation module 244-1, and the second frequency modulation module 248.

The second frequency modulation module 248 is configured to perform frequency modulation on the second clock frequency provided by the third clock recovery module 247 to obtain the first clock frequency, and provide the first clock frequency for the fourth clock adaptation module 244-1, the fourth obtaining module 244-2, and the fourth interface module 245.

Alternatively, the second clock recovery module 246 may be implemented by hardware or software, which is not limited in this embodiment of the application.

In one possible implementation, when the second clock recovery module 246 is implemented in hardware, the second clock recovery module 246 may include a second clock recovery circuit.

Alternatively, the third clock recovery module 247 may be implemented by hardware or software, which is not limited in this embodiment of the application.

In one possible implementation, when the third clock recovery module 247 is implemented by hardware, the third clock recovery module 247 may include a third clock recovery circuit.

Alternatively, the second frequency modulation module 248 may be implemented by hardware or software, which is not limited in this embodiment of the application.

In one possible implementation, when the second fm module 248 is implemented by hardware, the second fm module 248 may include a second fm circuit.

It should be noted that, in the above embodiment, the first communication device sends the first serial signal adapted to the first clock frequency to the second communication device through the system 200, and the second communication device sends the fourth serial signal adapted to the third clock frequency to the first communication device through the system 200, where the first clock frequency is different from the third clock frequency.

Optionally, taking the first clock frequency being smaller than the third clock frequency as an example, the system 200 provided in the embodiment of the present application may further achieve clock frequency synchronization of the bidirectional transmission signal by increasing the adaptive first clock frequency to the third clock frequency, that is, the fourth serial signal does not need to be adjusted, so as to implement full duplex communication. The specific implementation process is similar to that in the above embodiment, and is not described herein again to avoid repetition.

While the embodiments of the present application provide a full duplex communication system 200 as described above with reference to fig. 4 and 5, an interface apparatus 300 for performing the method 100 in the system 200 as described above will be described below with reference to fig. 6 and 7.

It should be noted that the apparatus 300 may be the first interface apparatus or the second interface apparatus described in the above embodiment of the method 100, and this embodiment of the present application is not limited thereto.

It is understood that the apparatus 300 comprises corresponding hardware and/or software modules for performing the respective functions in order to realize the above-mentioned functions. The present application is capable of being implemented in hardware or a combination of hardware and computer software in conjunction with the exemplary algorithm steps described in connection with the embodiments disclosed herein. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, with the embodiment described in connection with the particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The present embodiment may perform the division of the functional modules on the apparatus 300 according to the above method example, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The integrated module may be implemented in the form of hardware. It should be noted that the division of the modules in this embodiment is schematic, and is only a logic function division, and there may be another division manner in actual implementation.

In the case of dividing each functional module by corresponding functions, fig. 6 shows a schematic diagram of a possible composition of the first interface device or the second interface device involved in the above embodiments, and as shown in fig. 6, the apparatus 300 may include: a transceiving unit 310 and a processing unit 320.

Wherein the processing unit 320 may control the transceiver unit 310 to implement the methods described in the above-described method 100 embodiments, and/or other processes for the techniques described herein.

It should be noted that all relevant contents of each step related to the above method embodiment may be referred to the functional description of the corresponding functional module, and are not described herein again.

The present embodiment provides an apparatus 300 for performing the method 100, so that the same effect as the above implementation method can be achieved.

In one possible implementation, the apparatus 300 is a first interface apparatus, and correspondingly, the processing unit 310 may include a first clock adaptation module 232-1, a first obtaining module 232-2, a first mixing module 233, a second clock adaptation module 234-1, and a second obtaining module 234-2. The transceiving unit 320 may include a first interface module 231 and a second interface module 235.

Optionally, the processing unit 310 may further include a first clock recovery module 236, a clock source 237, and a first frequency modulation module 238.

In a possible implementation, the apparatus 300 is a second interface apparatus, and correspondingly, the processing unit 310 may include a third clock adaptation module 242-1, a third obtaining module 242-2, a second mixing module 243, a fourth clock adaptation module 244-1, and a fourth obtaining module 244-2. The transceiving unit 320 may include a third interface module 241 and a fourth interface module 245.

Optionally, the processing unit 310 may further include a second clock recovery module 246, a third clock recovery module 247, and a second frequency modulation module 238.

In case an integrated unit is employed, the apparatus 300 may comprise a processing unit, a storage unit and a communication unit. The processing unit may be configured to control and manage the operation of the apparatus 300, and for example, may be configured to support the apparatus 300 to execute the steps executed by the above units. The memory unit may be used to support the apparatus 300 in executing stored program codes and data, etc. The communication unit may be used to support the communication of the apparatus 300 with other devices.

Wherein the processing unit may be a processor or a controller. Which may implement or perform the various illustrative logical blocks, modules, and circuits described in connection with the disclosure. A processor may also be a combination of computing functions, e.g., a combination of one or more microprocessors, a Digital Signal Processing (DSP) and a microprocessor, or the like. The storage unit may be a memory. The communication unit may specifically be a radio frequency circuit, a bluetooth chip, a Wi-Fi chip, or other devices that interact with other electronic devices.

In a possible implementation manner, the apparatus 300 according to this embodiment may be an interface apparatus 400 having a structure shown in fig. 7, where the apparatus 400 may be a schematic structural diagram of a first interface apparatus, and may also be a schematic structural diagram of the first interface apparatus, where the apparatus 400 includes a processor 410 and a transceiver 420, and the processor 410 and the transceiver 420 communicate with each other through an internal connection path. The related functions implemented by the processing unit 320 in fig. 6 may be implemented by the processor 410, and the related functions implemented by the transceiver unit 310 may be implemented by the processor 410 controlling the transceiver 420.

Optionally, the interface 400 may further include a memory 430, and the processor 410, the transceiver 420 and the memory 430 communicate with each other through an internal connection path. The associated functions performed by the memory unit depicted in fig. 6 may be performed by the memory 430.

The present embodiment also provides a computer storage medium, in which computer instructions are stored, and when the computer instructions are run on an electronic device, the electronic device executes the above related method steps to implement the full duplex communication method in the above embodiment.

The present embodiment also provides a computer program product, which when running on a computer, causes the computer to execute the relevant steps described above, so as to implement the full-duplex communication method in the above embodiments.

In addition, embodiments of the present application also provide an apparatus, which may be specifically a chip, a component or a module, and may include a processor and a memory connected to each other; the memory is used for storing computer execution instructions, and when the device runs, the processor can execute the computer execution instructions stored in the memory, so that the chip can execute the access method in the above-mentioned method embodiments.

Fig. 8 shows a schematic structure of a chip 500. Chip 500 includes one or more processors 510 and interface circuits 520. Optionally, the chip 500 may further include a bus 530. Wherein:

processor 510 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 510. The processor 510 described above may be a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The methods, steps disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The interface circuit 520 may be used for transmitting or receiving data, instructions or information, and the processor 510 may perform processing by using the data, instructions or other information received by the interface circuit 520, and may transmit processing completion information through the interface circuit 520.

Optionally, the chip further comprises a memory, which may include read only memory and random access memory, and provides operating instructions and data to the processor. The portion of memory may also include non-volatile random access memory (NVRAM).

Optionally, the memory stores executable software modules or data structures, and the processor may perform corresponding operations by calling the operation instructions stored in the memory (the operation instructions may be stored in an operating system).

Alternatively, the chip may be used in the first interface device or the second interface device according to the embodiments of the present application. Optionally, interface circuit 520 may be used to output the results of the execution by processor 510. For the access method provided in one or more embodiments of the present application, reference may be made to the foregoing embodiments, which are not described herein again.

It should be noted that the functions corresponding to the processor 510 and the interface circuit 520 may be implemented by hardware design, software design, or a combination of hardware and software, which is not limited herein.

The first interface device, the second interface device, the computer storage medium, the computer program product, or the chip provided in this embodiment are all configured to execute the corresponding methods provided above, so that the beneficial effects achieved by the first interface device, the second interface device, the computer storage medium, the computer program product, or the chip may refer to the beneficial effects in the corresponding methods provided above, and are not described herein again.

It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A full-duplex communication method, the method being applied to a full-duplex communication system, the system including a first interface device and a second interface device, the first interface device and the second interface device performing full-duplex communication therebetween, the method comprising:

the first interface device acquires a first serial signal of a first communication device, wherein the first serial signal is adapted to a first clock frequency;

the first interface device performs first clock frequency conversion on the first serial signal to obtain a second serial signal, wherein the second serial signal is adapted to a second clock frequency, and the second clock frequency is greater than the first clock frequency;

the first interface device sends the second serial signal to the second interface device;

the first interface device receives a third serial signal from the second interface device, the third serial signal being adapted to the second clock frequency.

2. The method of claim 1, wherein the first serial signal is transmitted in a first transmission time, and the first interface device performs a first clock frequency conversion on the first serial signal to obtain a second serial signal, comprising:

the first interface device determines a first number according to the second clock frequency and the first clock frequency;

the first interface device adds the first number of first signals to the first serial signal to obtain the second serial signal.

3. The method of claim 2, wherein the first interface device adds the first number of first signals to the first serial signal to obtain the second serial signal, comprising:

the first interface device adds the first number of the first signals to the first serial signal according to a first conversion parameter to obtain the second serial signal, wherein the first conversion parameter includes at least one of a signal type of the first signal or an adding position of each first signal.

4. The method according to any of claims 1 to 3, wherein the third serial signal is obtained by a third clock frequency conversion of a fourth serial signal of a second communication device, the fourth serial signal being adapted to a third clock frequency, the third clock frequency being different from the first clock frequency, and the second clock frequency being greater than the third clock frequency, the method further comprising:

and the first interface device performs fourth clock frequency conversion on the third serial signal to obtain a fourth serial signal.

5. The method according to claim 4, wherein the third serial signal is transmitted in a second transmission time, and the fourth clock frequency conversion is performed on the third serial signal by the first interface device to obtain the fourth serial signal, including:

the first interface device determines a second number according to the second clock frequency and the third clock frequency;

the first interface device deletes the second number of second signals from the third serial signal to obtain the fourth serial signal.

6. The method of claim 5, wherein the first interface device removing the second number of second signals from the third serial signal to obtain the fourth serial signal comprises:

the first interface device deletes the second number of second signals from the third serial signals according to a second conversion parameter to obtain the fourth serial signals, wherein the second conversion parameter includes at least one of a signal type of the second signals or an adding position of each second signal.

7. The method according to any one of claims 1 to 6, wherein the second clock frequency is obtained by frequency modulating the first clock frequency; or, the second clock frequency is provided by the first clock source.

8. A full-duplex communication method, the method being applied to a full-duplex communication system, the system including a first interface device and a second interface device, the first interface device and the second interface device performing full-duplex communication therebetween, the method comprising:

the second interface device acquires a third serial signal of a second communication device, wherein the third serial signal is adaptive to a second clock frequency;

the second interface device sends the third serial signal to the first interface device;

the second interface device receives a second serial signal from the first interface device, the second serial signal is obtained by performing first clock frequency conversion on a first serial signal of a first communication device, the first serial signal is adapted to a first clock frequency, the second serial signal is adapted to a second clock frequency, and the second clock frequency is greater than the first clock frequency;

and the second interface device performs second clock frequency conversion on the second serial signal to obtain the first serial signal.

9. The method of claim 8, wherein the second serial signal is transmitted during a first transmission time, and the second interface device performs a second clock frequency conversion on the second serial signal to obtain the first serial signal, comprising:

the second interface device determines a first number according to the second clock frequency and the first clock frequency;

the second interface device deletes the first number of first signals from the second serial signal to obtain the first serial signal.

10. The method of claim 9, wherein the second interface device removing the first number of first signals from the second serial signal to obtain the first serial signal comprises:

the second interface device deletes the first number of the first signals from the second serial signals according to a first conversion parameter, so as to obtain the first serial signals, wherein the first conversion parameter comprises at least one of a signal type of the first signals or an adding position of each first signal.

11. The method according to any one of claims 8 to 10, wherein the second interface device acquiring the third serial signal of the second communication device comprises:

the second interface device acquires a fourth serial signal of the second communication device, wherein the fourth serial signal is adapted to a third clock frequency, the third clock frequency is different from the first clock frequency, and the second clock frequency is greater than the third clock frequency;

and the second interface device performs third clock frequency conversion on the fourth serial signal to obtain a third serial signal.

12. The method according to claim 11, wherein the fourth serial signal is transmitted in a second transmission time, and the second interface device performs a third clock frequency conversion on the fourth serial signal to obtain the third serial signal, including:

the second interface device determines a second number according to the second clock frequency and the third clock frequency;

the second interface device adds the second number of second signals to the fourth serial signal to obtain the third serial signal.

13. The method of claim 12, wherein the second interface device adds the second number of second signals to the fourth serial signal to obtain the third serial signal, comprising:

the second interface device adds the second number of second signals to the fourth serial signal according to a second conversion parameter to obtain the third serial signal, where the second conversion parameter includes at least one of a signal type of the second signal or an addition position of each second signal.

14. A chip apparatus, comprising: at least one processor and a memory, the at least one processor being configured to execute code in the memory, wherein the chip means implements the method of any one of the preceding claims 1 to 7 or any one of the claims 8 to 13 when the code is executed by the at least one processor.

15. A full duplex system, characterized in that the system comprises a first interface and a second interface, the first interface and the second interface are connected through a transmission line for full duplex communication, the first interface is used for implementing the method of any of the preceding claims 1 to 7, and the second interface is used for implementing the method of any of the preceding claims 8 to 13.

16. A computer-readable storage medium for storing a computer program, characterized in that the computer program comprises instructions for implementing the method of any of the preceding claims 1 to 7 or any of the claims 8 to 13.

17. A computer program product comprising instructions which, when run on a computer or processor, cause the computer or processor to carry out the method of any of claims 1 to 7 or any of claims 8 to 13.