CN113765504A - Universal dynamic delay jitter elimination method, device, terminal and storage medium - Google Patents
Universal dynamic delay jitter elimination method, device, terminal and storage medium Download PDFInfo
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Abstract
The invention discloses a universal dynamic delay jitter elimination method, a universal dynamic delay jitter elimination device, a universal dynamic delay jitter elimination terminal and a universal dynamic delay jitter elimination storage medium, wherein whether the operation is false operation is detected; when the false operation is detected, recording the number of false operations; and adjusting the jitter elimination delay time of the next operation according to the recorded false operation times, and performing jitter elimination processing based on the adjusted jitter elimination delay time during the next operation. The method can adjust the jitter elimination delay time according to the number of false operations, so that the jitter elimination delay time is more reasonable, the judgment for multiple times is avoided, and the judgment accuracy is ensured; meanwhile, one shake elimination module can be used to adapt to different application scenes, and the workload of developers is reduced.
Description
Technical Field
The invention relates to the field of time delay jitter elimination, in particular to a universal dynamic time delay jitter elimination method, a universal dynamic time delay jitter elimination device, a universal dynamic time delay jitter elimination terminal and a storage medium.
Background
Jitter elimination is generally used for a mechanical elastic switch or a hot plug connector, when the mechanical switch is opened or closed or the connector is plugged, due to instability of manual operation and instability of contacts of the mechanical elastic switch/the connector, a system cannot effectively judge a high/low level state of a signal, namely a metastable state, before the signal state is stable. Taking a connector as an example, when the connector is inserted into the connection, the signal will not be immediately stable, and a series of jitter will be accompanied at the moment of insertion, and such jitter will cause the system to misjudge the signal status. In order to avoid this, i.e. to correctly recognize the insertion and extraction of the mechanical spring switch and the connector, it is necessary to deal with jitter of the signal.
The existing state machine is usually used for eliminating jitter, when the new state is detected to be different from the old state, state transition is carried out and delayed, the new state is detected after delay, if the state is not changed, the state change is determined to be effective change, and the old state is assigned to be the new state and is output to the system.
Taking the key operation as an example: the key operation can be divided into 4 states, i.e. key pressing action S0, key pressing action S1, stable pressing action S2 and key releasing action S3. Assume that the level is 0 when the key is pressed and 1 when it is not pressed. A key initial state S0 indicating no key press, holding S0; when the key is pressed, the state S1 is entered.
First, the initial state of the key is S0, and when an input of 1 is detected, this indicates that no key has been pressed, and S0 is maintained. When the key input is 0, pressing a key, and after the time delay, if the input is still 0, switching to a state S1; after the state is switched to the state S1, the input is still 0 after the delay time, and the state is continuously switched to the state S2; similarly, if the input remains 0 after a delay time from the transition to the state S2, the transition to S3 indicates that a key press is indeed present and the message can be passed to the system. In this process, any state detects that the input is 1, indicating that the last key operation is a disturbance and that the key operation is not actually performed, and the state is switched back to S0. In the state of S3, it is detected that the input is high, i.e., there is a key release operation, and the state is switched back to S0.
In the state transition process of S1-S3, each state needs to be delayed, and the jitter elimination delay process generally takes 10ms or 20 ms. The selection of the delay time is very important, and if the delay time is too short, the state machine needs to judge for many times; if the delay is too long, the judgment efficiency is low. However, on one hand, the current delay time is generally determined by experience, and on the other hand, different application scenes have different jitter elimination requirements, and accordingly, a state machine needs to configure a jitter elimination module for each application scene, so that the workload of developers is increased.
Disclosure of Invention
In order to solve the above problems, the present invention provides a general dynamic delay debouncing method, apparatus, terminal and storage medium, which can dynamically adjust the debouncing delay time of each operation, and can be applied to various application scenarios by using one debouncing module.
In a first aspect, the present invention provides a general dynamic delay jitter elimination method, which includes the following steps:
detecting whether the operation is false operation;
when the false operation is detected, recording the number of false operations;
and adjusting the jitter elimination delay time of the next operation according to the recorded false operation times, and performing jitter elimination processing based on the adjusted jitter elimination delay time during the next operation.
Further, adjusting the jitter elimination delay time of the next operation according to the recorded number of false operations, specifically calculating the jitter elimination delay time of the next operation by the following formula:
delayn+1=delayn+ delayn*delaycounter/N；
wherein, delaynDelay time for the nth operationn+1For the debounce delay time of the (N + 1) th operation, delaycounter is the number of recorded false operations, and N is the number of states experienced by the operation process.
Further, the method comprises the following steps:
after the detection of the false operation, when a normal operation is detected, the recorded number of false operations is cleared.
Further, the method comprises the following steps:
and setting the jitter elimination delay time of the next operation as the initial jitter elimination delay time when the recorded false operation times are cleared.
In a second aspect, the present invention provides a general dynamic delay jitter elimination apparatus, including,
an operation detection unit: detecting whether the operation is false operation;
false operation number recording unit: when the false operation is detected, recording the number of false operations;
a jitter elimination delay time adjustment unit: and adjusting the jitter elimination delay time of the next operation according to the recorded false operation times.
Further, the jitter elimination delay time adjustment unit adjusts the jitter elimination delay time of the next operation according to the recorded number of false operations, specifically, the jitter elimination delay time of the next operation is calculated by the following formula:
delayn+1=delayn+ delayn*delaycounter/N；
wherein, delaynDelay time for the nth operationn+1For the debounce delay time of the (N + 1) th operation, delaycounter is the number of recorded false operations, and N is the number of states experienced by the operation process.
Further, the device also comprises a control device,
a recording false operation number zero clearing unit: after the detection of the false operation, when a normal operation is detected, the recorded number of false operations is cleared.
Further, the jitter elimination delay time adjustment unit is further configured to set the jitter elimination delay time of the next operation as the initial jitter elimination delay time when the recorded number of false operations is zero.
In a third aspect, a technical solution of the present invention provides a terminal, including:
the memorizer is used for storing a general dynamic delay jitter elimination program;
and the processor is used for realizing the steps of the universal dynamic delay jitter elimination method in any one of the above steps when the universal dynamic delay jitter elimination program is executed.
In a fourth aspect, an embodiment of the present invention provides a readable storage medium, where a general dynamic latency debounce program is stored on the readable storage medium, and when executed by a processor, the general dynamic latency debounce program implements the steps of the general dynamic latency debounce method as described in any one of the above.
Compared with the prior art, the universal dynamic delay jitter elimination method, the universal dynamic delay jitter elimination device, the universal dynamic delay jitter elimination terminal and the storage medium have the following beneficial effects: and recording the number of false operations when the false operations are detected, adjusting the jitter elimination delay time of the next operation according to the recorded number of false operations, and performing jitter elimination processing on the basis of the adjusted jitter elimination delay time during the next operation. The method can adjust the jitter elimination delay time according to the number of false operations, so that the jitter elimination delay time is more reasonable, the judgment for multiple times is avoided, and the judgment accuracy is ensured; meanwhile, one shake elimination module can be used to adapt to different application scenes, and the workload of developers is reduced.
Drawings
For a clearer explanation of the embodiments or technical solutions of the prior art of the present application, the drawings needed for the description of the embodiments or prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic flow chart of a general dynamic delay jitter elimination method according to an embodiment of the present invention;
fig. 2 is a schematic flow chart of a general dynamic delay jitter elimination method according to a second embodiment of the present invention;
fig. 3 is a schematic flow chart of a general dynamic delay jitter elimination method according to a third embodiment of the present invention;
fig. 4 is a schematic block diagram of a general dynamic delay jitter reduction apparatus according to a fourth embodiment of the present invention;
fig. 5 is a schematic block diagram of a structure of a general dynamic delay jitter reduction apparatus according to a sixth embodiment of the present invention;
fig. 6 is a schematic structural diagram of a terminal according to a seventh embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Example one
In a scene needing jitter elimination, such as a mechanical elastic switch or a hot plug connector, a state machine is usually used for eliminating jitter, when a new state is detected to be different from an old state, state transition is carried out and delayed, the new state is detected after delay, if the state is not changed, the state change is determined to be an effective change, and the old state is assigned to be the new state and is output to a system.
Taking the key operation as an example: the key operation can be divided into 4 states, i.e. key pressing action S0, key pressing action S1, stable pressing action S2 and key releasing action S3. Assume that the level is 0 when the key is pressed and 1 when it is not pressed. A key initial state S0 indicating no key press, holding S0; when the key is pressed, the state S1 is entered.
First, the initial state of the key is S0, and when an input of 1 is detected, this indicates that no key has been pressed, and S0 is maintained. When the key input is 0, pressing a key, and after the time delay, if the input is still 0, switching to a state S1; after the state is switched to the state S1, the input is still 0 after the delay time, and the state is continuously switched to the state S2; similarly, if the input remains 0 after a delay time from the transition to the state S2, the transition to S3 indicates that a key press is indeed present and the message can be passed to the system. In this process, any state detects that the input is 1, indicating that the last key operation is a disturbance and that the key operation is not actually performed, and the state is switched back to S0. In the state of S3, it is detected that the input is high, i.e., there is a key release operation, and the state is switched back to S0.
In the state transition process of S1-S3, each state needs to be delayed, and the jitter elimination delay process generally takes 10ms or 20 ms. The selection of the delay time is very important, and if the delay time is too short, the state machine needs to judge for many times; if the delay is too long, the judgment efficiency is low. However, on one hand, the current delay time is generally determined by experience, and on the other hand, different application scenes have different jitter elimination requirements, and accordingly, a state machine needs to configure a jitter elimination module for each application scene, so that the workload of developers is increased.
Therefore, the present embodiment provides a general dynamic delay debouncing method, which can dynamically adjust the debouncing delay time of each operation, and can be applied to various application scenarios by using one debouncing module.
Fig. 1 is a schematic flow chart of a general dynamic delay jitter elimination method provided in this embodiment, which includes the following steps.
S101, whether the operation is false operation is detected.
That is, whether the detection operation is the interference operation or the normal operation, and the interference operation is the false operation, and for example, when the key operation is detected that the input becomes 1 after the time delay after the state S1, the operation is the interference operation, that is, the false operation. If the state shifts to S3, the operation is normal.
S102, when the false operation is detected, recording the number of false operations.
Note that the number of false operations recorded is the number of accumulated times. For example, if the first operation is a false operation, the number of false operations is recorded as 1, and if the second operation is still a false operation, the number of false operations is recorded plus 1, i.e., the number of false operations is 2.
And S103, adjusting the jitter elimination delay time of the next operation according to the recorded false operation times, and performing jitter elimination processing on the basis of the adjusted jitter elimination delay time during the next operation.
If false operation occurs, the jitter elimination delay time of the next operation is adjusted in time, the accuracy of the next judgment is improved, and false detection is avoided.
In the general dynamic delay debouncing method provided in this embodiment, the number of false operations is recorded when a false operation is detected, the debouncing delay time of the next operation is adjusted according to the recorded number of false operations, and the debouncing processing is performed based on the adjusted debouncing delay time during the next operation. The method can adjust the jitter elimination delay time according to the number of false operations, so that the jitter elimination delay time is more reasonable, the judgment for multiple times is avoided, and the judgment accuracy is ensured; meanwhile, one shake elimination module can be used to adapt to different application scenes, and the workload of developers is reduced.
Example two
Considering that after a false operation is detected, the probability that the false operation still occurs next time is still larger, the present embodiment adjusts the debounce delay time of the next operation according to the recorded number of false operations, and the adjusted debounce delay time is prolonged before adjustment.
Specifically, the debounce delay time for the next operation is calculated by the following formula:
delayn+1=delayn+ delayn*delaycounter/N
wherein, delaynDelay time for the nth operationn+1For the debounce delay time of the (N + 1) th operation, delaycounter is the number of recorded false operations, and N is the number of states experienced by the operation process.
Taking the key operation as an example, the four states of S0, S1, S2 and S3 are passed through, so that N is 4 in the above formula during the key operation. Of course, in other scenarios, the value of N is adjusted according to the number of states experienced in the specific operation process.
It should be noted that an initial value of the debounce delay time, i.e. the debounce delay time delay of the first operation, needs to be preset before detection1。
Still taking the key operation as an example, if the first operation is a false operation, the number of false operations is recorded as 1, and the jitter elimination delay time delay of the second operation is calculated2=delay1+ delay1*1/4. If the second operation is still false operation, recording the number of false operations as 2, and further calculating the jitter elimination delay time delay of the third operation3=delay2+ delay2*2/4。
Fig. 2 is a schematic flow chart of a general dynamic delay jitter elimination method provided in this embodiment, which includes the following steps.
S201, detecting whether the operation is false operation.
S202, when the false operation is detected, recording the number of false operations.
S203, according to the formula delayn+1=delayn+ delayndelaycounter/N calculating the next operationJitter elimination delay time.
In the general dynamic delay debounce method provided by this embodiment, the number of false operations is recorded when a false operation is detected, and a formula delay is used according to the recorded number of false operationsn+1=delayn+ delayndelaycounter/N adjusts the jitter elimination delay time of the next operation, and performs jitter elimination processing based on the adjusted jitter elimination delay time at the next operation. The method can adjust the jitter elimination delay time according to the number of false operations, so that the jitter elimination delay time is more reasonable, the judgment for multiple times is avoided, and the judgment accuracy is ensured; meanwhile, one shake elimination module can be used to adapt to different application scenes, and the workload of developers is reduced.
EXAMPLE III
After the normal operation is detected, the probability of the next normal operation is higher, so that the recorded false operation times are cleared in time after the normal operation is detected, the jitter elimination delay time of the next operation is correspondingly adjusted to be the initial jitter elimination delay time, and the recording of the false operation times and the adjustment of the jitter elimination delay time are carried out again.
Fig. 3 is a schematic flow chart of a general dynamic delay jitter elimination method provided in this embodiment, which includes the following steps.
S301, detecting whether the operation is false operation.
S302, when the false operation is detected, recording the number of false operations.
S303, according to the formula delayn+1=delayn+ delayndelaycounter/N calculates the debounce delay time for the next operation.
Wherein, delaynDelay time for the nth operationn+1For the debounce delay time of the (N + 1) th operation, delaycounter is the number of recorded false operations, and N is the number of states experienced by the operation process.
S304, after the false operation is detected, when one normal operation is detected, the recorded false operation frequency is cleared.
S305, setting the jitter elimination delay time of the next operation as the initial jitter elimination delay time when the recorded false operation times are clear.
It should be noted that, except that when the recorded number of times of the false operation is zero, that is, when the previous false operation is changed to the normal operation of the time, the debounce delay time of the next operation is set as the initial debounce delay time, otherwise, the initial debounce delay time is set according to the formula delayn+1=delayn+ delayndelaycounter/N calculates the debounce delay time for the next operation.
In the general dynamic delay debounce method provided by this embodiment, the number of false operations is recorded when a false operation is detected, and a formula delay is used according to the recorded number of false operationsn+1=delayn+ delayndelaycounter/N adjusts the jitter elimination delay time of the next operation, and performs jitter elimination processing based on the adjusted jitter elimination delay time at the next operation. In addition, after the false operation is changed into the normal operation, the recorded false operation times are cleared in time, and the jitter elimination delay time of the next operation is set as the initial jitter elimination delay time, so that the state detection efficiency is improved. The method can adjust the jitter elimination delay time according to the number of false operations, so that the jitter elimination delay time is more reasonable, the judgment for multiple times is avoided, and the judgment accuracy is ensured; meanwhile, one shake elimination module can be used to adapt to different application scenes, and the workload of developers is reduced.
Example four
In order to solve the problems that the current delay time is generally determined by experience, different application scenes have different jitter elimination requirements, a state machine needs to configure a jitter elimination module for each application scene correspondingly, and the workload of developers is increased, the embodiment provides the general dynamic delay jitter elimination device, the jitter elimination delay time of each operation can be dynamically adjusted, and one jitter elimination module can be applied to various application scenes.
Fig. 4 is a schematic block diagram of a structure of a general dynamic delay jitter reduction apparatus provided in this embodiment, which includes the following functional units.
Operation detection unit 101: it is detected whether the operation is a false operation.
That is, whether the detection operation is the interference operation or the normal operation, and the interference operation is the false operation, and for example, when the key operation is detected that the input becomes 1 after the time delay after the state S1, the operation is the interference operation, that is, the false operation. If the state shifts to S3, the operation is normal.
The false operation number recording unit 102: when a false operation is detected, the number of false operations is recorded.
Note that the number of false operations recorded is the number of accumulated times. For example, if the first operation is a false operation, the number of false operations is recorded as 1, and if the second operation is still a false operation, the number of false operations is recorded plus 1, i.e., the number of false operations is 2.
Jitter elimination delay time adjustment unit 103: and adjusting the jitter elimination delay time of the next operation according to the recorded false operation times.
It should be noted that the jitter elimination processing is performed based on the adjusted jitter elimination delay time at the next operation. And if false operation occurs, the jitter elimination delay time of the next operation is timely adjusted, the accuracy of the next judgment is improved, and the false detection is avoided.
In the general dynamic delay debouncing apparatus provided in this embodiment, the number of false operations is recorded when a false operation is detected, the debouncing delay time of the next operation is adjusted according to the recorded number of false operations, and the debouncing process is performed based on the adjusted debouncing delay time during the next operation. The method can adjust the jitter elimination delay time according to the number of false operations, so that the jitter elimination delay time is more reasonable, the judgment for multiple times is avoided, and the judgment accuracy is ensured; meanwhile, one shake elimination module can be used to adapt to different application scenes, and the workload of developers is reduced.
EXAMPLE five
Fig. 4 is a schematic block diagram of a structure of a general dynamic delay jitter reduction apparatus provided in this embodiment, which includes the following functional units.
Operation detection unit 101: it is detected whether the operation is a false operation.
The false operation number recording unit 102: when a false operation is detected, the number of false operations is recorded.
Jitter elimination delay time adjustment unit 103: and adjusting the jitter elimination delay time of the next operation according to the recorded false operation times.
Considering that after a false operation is detected, the probability that the false operation still occurs next time is still larger, the present embodiment adjusts the debounce delay time of the next operation according to the recorded number of false operations, and the adjusted debounce delay time is prolonged before adjustment.
Specifically, the debounce delay time adjustment unit 103 calculates the debounce delay time for the next operation by the following formula:
delayn+1=delayn+ delayn*delaycounter/N
wherein, delaynDelay time for the nth operationn+1For the debounce delay time of the (N + 1) th operation, delaycounter is the number of recorded false operations, and N is the number of states experienced by the operation process.
Taking the key operation as an example, the four states of S0, S1, S2 and S3 are passed through, so that N is 4 in the above formula during the key operation. Of course, in other scenarios, the value of N is adjusted according to the number of states experienced in the specific operation process.
It should be noted that an initial value of the debounce delay time, i.e. the debounce delay time delay of the first operation, needs to be preset before detection1。
Still taking the key operation as an example, if the first operation is a false operation, the number of false operations is recorded as 1, and the jitter elimination delay time delay of the second operation is calculated2=delay1+ delay1*1/4. If the second operation is still false operation, recording the number of false operations as 2, and further calculating the jitter elimination delay time delay of the third operation3=delay2+ delay2*2/4。
In the general dynamic delay debounce apparatus provided in this embodiment, the number of false operations is recorded when a false operation is detected, and a formula delay is used according to the recorded number of false operationsn+1=delayn+ delayndelaycounter/N adjusts the jitter elimination delay time of the next operation, and performs jitter elimination processing based on the adjusted jitter elimination delay time at the next operation. The invention can be operated according to the falseThe jitter elimination delay time is adjusted for times, so that the jitter elimination delay time is more reasonable, repeated judgment is avoided, and the judgment accuracy is ensured; meanwhile, one shake elimination module can be used to adapt to different application scenes, and the workload of developers is reduced.
EXAMPLE six
After the normal operation is detected, the probability of the next normal operation is higher, so that the recorded false operation times are cleared in time after the normal operation is detected, the jitter elimination delay time of the next operation is correspondingly adjusted to be the initial jitter elimination delay time, and the recording of the false operation times and the adjustment of the jitter elimination delay time are carried out again.
Fig. 5 is a schematic block diagram of a structure of a general dynamic delay jitter reduction apparatus provided in this embodiment, which includes the following functional units.
Operation detection unit 101: it is detected whether the operation is a false operation.
The false operation number recording unit 102: when a false operation is detected, the number of false operations is recorded.
Jitter elimination delay time adjustment unit 103: and adjusting the jitter elimination delay time of the next operation according to the recorded false operation times.
Recording false operation number clearing unit 104: after the detection of the false operation, when a normal operation is detected, the recorded number of false operations is cleared.
Wherein, the jitter elimination delay time adjustment unit 103 calculates the jitter elimination delay time of the next operation by the following formula:
delayn+1=delayn+ delayn*delaycounter/N
wherein, delaynDelay time for the nth operationn+1For the debounce delay time of the (N + 1) th operation, delaycounter is the number of recorded false operations, and N is the number of states experienced by the operation process.
In addition, the jitter elimination delay time adjustment unit 103 is further configured to set the jitter elimination delay time of the next operation as the initial jitter elimination delay time when the recorded number of false operations is zero.
It should be noted that, in the following description,except that when the recorded number of false operations is zero, namely the false operation is changed into the normal operation of the time, the jitter elimination delay time of the next operation is set as the initial jitter elimination delay time, and the jitter elimination delay time is set according to the formula delay in other casesn+1=delayn+ delayndelaycounter/N calculates the debounce delay time for the next operation.
In the general dynamic delay debounce apparatus provided in this embodiment, the number of false operations is recorded when a false operation is detected, and a formula delay is used according to the recorded number of false operationsn+1=delayn+ delayndelaycounter/N adjusts the jitter elimination delay time of the next operation, and performs jitter elimination processing based on the adjusted jitter elimination delay time at the next operation. In addition, after the false operation is changed into the normal operation, the recorded false operation times are cleared in time, and the jitter elimination delay time of the next operation is set as the initial jitter elimination delay time, so that the state detection efficiency is improved. The method can adjust the jitter elimination delay time according to the number of false operations, so that the jitter elimination delay time is more reasonable, the judgment for multiple times is avoided, and the judgment accuracy is ensured; meanwhile, one shake elimination module can be used to adapt to different application scenes, and the workload of developers is reduced.
EXAMPLE seven
Fig. 6 is a schematic structural diagram of a terminal device 600 according to an embodiment of the present invention, including: a processor 610, a memory 620, and a communication unit 630. The processor 610 is configured to implement the following steps when implementing the general dynamic latency debounce program stored in the memory 620:
detecting whether the operation is false operation;
when the false operation is detected, recording the number of false operations;
and adjusting the jitter elimination delay time of the next operation according to the recorded false operation times, and performing jitter elimination processing based on the adjusted jitter elimination delay time during the next operation.
The general dynamic delay jitter elimination method of the invention records the number of times of false operation when the false operation is detected, adjusts the jitter elimination delay time of the next operation according to the recorded number of times of false operation, and carries out jitter elimination processing based on the adjusted jitter elimination delay time during the next operation. The method can adjust the jitter elimination delay time according to the number of false operations, so that the jitter elimination delay time is more reasonable, the judgment for multiple times is avoided, and the judgment accuracy is ensured; meanwhile, one shake elimination module can be used to adapt to different application scenes, and the workload of developers is reduced.
In some embodiments, when the processor 610 executes the general dynamic latency debounce subroutine stored in the memory 620, the following steps may be specifically implemented: calculating the jitter elimination delay time of the next operation by the following formula: delayn+1=delayn+ delayndelaycounter/N; wherein, delaynDelay time for the nth operationn+1For the debounce delay time of the (N + 1) th operation, delaycounter is the number of recorded false operations, and N is the number of states experienced by the operation process.
In some embodiments, when the processor 610 executes the general dynamic latency debounce subroutine stored in the memory 620, the following steps may be specifically implemented: after the detection of the false operation, when a normal operation is detected, the recorded number of false operations is cleared.
In some embodiments, when the processor 610 executes the general dynamic latency debounce subroutine stored in the memory 620, the following steps may be specifically implemented: and setting the jitter elimination delay time of the next operation as the initial jitter elimination delay time when the recorded false operation times are cleared.
The terminal device 600 may include: a processor 610, a memory 620, and a communication unit 630. The components communicate via one or more buses, and those skilled in the art will appreciate that the architecture of the servers shown in the figures is not intended to be limiting, and may be a bus architecture, a star architecture, a combination of more or less components than those shown, or a different arrangement of components.
The memory 620 may be used for storing instructions executed by the processor 610, and the memory 620 may be implemented by any type of volatile or non-volatile storage terminal or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The executable instructions in memory 620, when executed by processor 610, enable terminal 600 to perform some or all of the steps in the method embodiments described below.
The processor 610 is a control center of the storage terminal, connects various parts of the entire electronic terminal using various interfaces and lines, and performs various functions of the electronic terminal and/or processes data by operating or executing software programs and/or units stored in the memory 620 and calling data stored in the memory. The processor may be composed of an Integrated Circuit (IC), for example, a single packaged IC, or a plurality of packaged ICs connected with the same or different functions. For example, the processor 610 may include only a Central Processing Unit (CPU). In the embodiment of the present invention, the CPU may be a single operation core, or may include multiple operation cores.
A communication unit 630, configured to establish a communication channel so that the storage terminal can communicate with other terminals. And receiving user data sent by other terminals or sending the user data to other terminals.
Example eight
The present invention also provides a computer storage medium, wherein the computer storage medium may store a program, and the program may include some or all of the steps in the embodiments provided by the present invention when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a Random Access Memory (RAM).
The computer storage medium stores a general dynamic latency debounce program that when executed by a processor performs the steps of:
detecting whether the operation is false operation;
when the false operation is detected, recording the number of false operations;
and adjusting the jitter elimination delay time of the next operation according to the recorded false operation times, and performing jitter elimination processing based on the adjusted jitter elimination delay time during the next operation.
The general dynamic delay jitter elimination method of the invention records the number of times of false operation when the false operation is detected, adjusts the jitter elimination delay time of the next operation according to the recorded number of times of false operation, and carries out jitter elimination processing based on the adjusted jitter elimination delay time during the next operation. The method can adjust the jitter elimination delay time according to the number of false operations, so that the jitter elimination delay time is more reasonable, the judgment for multiple times is avoided, and the judgment accuracy is ensured; meanwhile, one shake elimination module can be used to adapt to different application scenes, and the workload of developers is reduced.
In some specific embodiments, when the general dynamic latency debounce subroutine stored in the readable storage medium is executed, the following steps may be specifically implemented: calculating the jitter elimination delay time of the next operation by the following formula: delayn+1=delayn+ delayndelaycounter/N; wherein, delaynDelay time for the nth operationn+1For the debounce delay time of the (N + 1) th operation, delaycounter is the number of recorded false operations, and N is the number of states experienced by the operation process.
In some specific embodiments, when the general dynamic latency debounce subroutine stored in the readable storage medium is executed, the following steps may be specifically implemented: after the detection of the false operation, when a normal operation is detected, the recorded number of false operations is cleared.
In some specific embodiments, when the general dynamic latency debounce subroutine stored in the readable storage medium is executed, the following steps may be specifically implemented: and setting the jitter elimination delay time of the next operation as the initial jitter elimination delay time when the recorded false operation times are cleared.
Those skilled in the art will readily appreciate that the techniques of the embodiments of the present invention may be implemented as software plus a required general purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present invention may be embodied in the form of a software product, where the computer software product is stored in a storage medium, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and the like, and the storage medium can store program codes, and includes instructions for enabling a computer terminal (which may be a personal computer, a server, or a second terminal, a network terminal, and the like) to perform all or part of the steps of the method in the embodiments of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The above disclosure is only for the preferred embodiments of the present invention, but the present invention is not limited thereto, and any non-inventive changes that can be made by those skilled in the art and several modifications and amendments made without departing from the principle of the present invention shall fall within the protection scope of the present invention.
Claims (10)
1. A general dynamic delay jitter elimination method is characterized by comprising the following steps:
detecting whether the operation is false operation;
when the false operation is detected, recording the number of false operations;
and adjusting the jitter elimination delay time of the next operation according to the recorded false operation times, and performing jitter elimination processing based on the adjusted jitter elimination delay time during the next operation.
2. The universal dynamic latency debouncing method of claim 1, wherein the debouncing latency for the next operation is adjusted according to the recorded number of false operations, and specifically, the debouncing latency for the next operation is calculated by the following formula:
delayn+1=delayn+ delayn*delaycounter/N；
wherein, delaynDelay time for the nth operationn+1For the debounce delay time of the (N + 1) th operation, delaycounter is the number of recorded false operations, and N is the number of states experienced by the operation process.
3. The universal dynamic delay debounce method according to claim 2, further comprising the steps of:
after the detection of the false operation, when a normal operation is detected, the recorded number of false operations is cleared.
4. The universal dynamic delay debounce method according to claim 3, further comprising the steps of:
and setting the jitter elimination delay time of the next operation as the initial jitter elimination delay time when the recorded false operation times are cleared.
5. A universal dynamic delay jitter-eliminating device is characterized in that it comprises,
an operation detection unit: detecting whether the operation is false operation;
false operation number recording unit: when the false operation is detected, recording the number of false operations;
a jitter elimination delay time adjustment unit: and adjusting the jitter elimination delay time of the next operation according to the recorded false operation times.
6. The universal dynamic delay debouncing device of claim 5, wherein the debounce delay time adjustment unit adjusts the debounce delay time of the next operation according to the recorded number of false operations, and specifically calculates the debounce delay time of the next operation according to the following formula:
delayn+1=delayn+ delayn*delaycounter/N；
wherein, delaynDelay time for the nth operationn+1For the debounce delay time of the (N + 1) th operation, delaycounter is the number of recorded false operations, and N is the number of states experienced by the operation process.
7. The universal dynamic delay debounce apparatus of claim 6, further comprising,
a recording false operation number zero clearing unit: after the detection of the false operation, when a normal operation is detected, the recorded number of false operations is cleared.
8. The universal dynamic delay debouncing apparatus of claim 7, wherein the debounce delay time adjustment unit is further configured to set the debounce delay time of the next operation to the initial debounce delay time when the recorded number of false operations is clear.
9. A terminal, comprising:
the memorizer is used for storing a general dynamic delay jitter elimination program;
a processor for implementing the steps of the general dynamic latency debounce method according to any one of claims 1 to 4 when executing the general dynamic latency debounce program.
10. A readable storage medium, having a general dynamic latency debounce program stored thereon, wherein the general dynamic latency debounce program, when executed by a processor, implements the steps of the general dynamic latency debounce method according to any one of claims 1 to 4.
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|---|---|---|---|---|
| CN116186086A (en) * | 2023-02-09 | 2023-05-30 | 辰芯半导体（深圳）有限公司 | Adaptive key jitter elimination digital processing method and system based on branch prediction |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109743263A (en) * | 2019-01-14 | 2019-05-10 | 北京三体云联科技有限公司 | Dynamic jitter buffer method, apparatus and computer equipment |
| CN111327386A (en) * | 2018-12-14 | 2020-06-23 | 深圳市中兴微电子技术有限公司 | Delay jitter compensation method and device and computer storage medium |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111327386A (en) * | 2018-12-14 | 2020-06-23 | 深圳市中兴微电子技术有限公司 | Delay jitter compensation method and device and computer storage medium |
| CN109743263A (en) * | 2019-01-14 | 2019-05-10 | 北京三体云联科技有限公司 | Dynamic jitter buffer method, apparatus and computer equipment |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116186086A (en) * | 2023-02-09 | 2023-05-30 | 辰芯半导体（深圳）有限公司 | Adaptive key jitter elimination digital processing method and system based on branch prediction |
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