CN113765499B - Bandwidth calibration circuit and method for broadband active RC filter - Google Patents
Bandwidth calibration circuit and method for broadband active RC filter Download PDFInfo
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Abstract
The application relates to a broadband active RC filter bandwidth calibration circuit and a method. The circuit comprises: the device comprises a frequency divider, a resistor network, a capacitor charge-discharge switch, a comparator, a binary search algorithm, a decoder and a digital-to-analog converter. The bandwidth adjustment control signal corresponding to the bandwidth of the filter generates a reference voltage through the digital-to-analog converter and sends the reference voltage to one input end of the comparator, charge and discharge nodes of the resistor network and the capacitor network are connected to the other input end of the comparator, a binary search algorithm generates a corresponding filter bandwidth search code according to an output result of the comparator, and the decoder converts the filter bandwidth search code into a corresponding resistor-capacitor network adjustment value. The calibration method comprises: 1) The number of passive elements in the broadband active RC filter is obviously reduced, the chip area is saved, and the circuit design complexity is reduced; 2) The wide input frequency range of the crystal oscillator is supported; 3) The circuit has the advantages of simple structure, convenience for industrial realization and the like.
Description
Technical Field
The present application relates to the field of analog integrated circuits, and in particular, to a wideband filter bandwidth calibration circuit and method for software defined radio.
Background
The excellent linearity of the active RC filter makes it widely used in radio frequency transceivers. A wideband active RC filter with high linearity performance is usually integrated in a software defined radio frequency transceiver, which is mainly used to avoid aliasing during sampling (receive chain) and to suppress the periodic spectrum in the baseband signal (transmit chain).
The deviation introduced by PVT can seriously affect the bandwidth accuracy of the active RC filter, which causes aliasing or insufficient suppression of periodic frequency spectrum, and in serious cases, it can also suppress the high frequency part of the effective signal, which causes signal distortion.
To ensure high precision of filter bandwidth, calibration of RC time constant is usually required, and in patent "bandwidth calibration for filter" (application No. 201210558928.2, grant No. CN103078630 a), stability of RC time constant is ensured by changing capacitance value of switch capacitor under driving of clock CLK. The main reason is that: 1) The calibration is carried out only by using a capacitor network, and the resistor network is used for adjusting the bandwidth of the broadband filter, so that the number of passive devices in the filter is very large, and the filter is particularly applied to a software defined radio multi-channel radio frequency transceiver; 2) The RC time constant depends on a constant CLK clock frequency (usually from an external crystal oscillator), and in a software-defined radio application scenario, it is usually necessary to support a very wide input frequency range of the crystal oscillator, and the conventional calibration structure cannot work properly.
Patent "a filter bandwidth calibration circuit" (application No. 201410024682. X) proposes a broadband active RC filter bandwidth calibration scheme suitable for software defined radio application scenarios, which guarantees the stability of RC time constants (different bandwidths correspond to different time constants) by counting the high level duration in one period of the divided external clock and comparing with the preset value in the register. Compared with the traditional scheme, the method has the advantages that: 1) RC networks in the oscillator can be used for adjusting the bandwidth of the filter, so that the freedom degree of bandwidth adjustment is increased, and the number of passive elements in the filter can be obviously reduced; 2) The generation of the external clock CLK does not depend on an external crystal oscillator, but is provided by fractional frequency division through an internally integrated frequency synthesizer, different filter bandwidths correspond to different external clock frequencies, and the wide crystal oscillator input frequency range required in a radio application scene can be defined by software. However, this calibration method still has significant limitations: 1) An RC oscillator circuit and a counter need to be additionally constructed, so that the complexity of circuit design is increased; 2) The calibration of the filter bandwidth depends on an internal frequency synthesizer and a fractional frequency divider, the calibration process is complex, and the clock jitter generated by the fractional frequency divider affects the counting precision and deteriorates the bandwidth calibration precision of the filter.
Disclosure of Invention
In view of the above, it is necessary to provide a wideband active RC filter bandwidth calibration circuit and method with better calibration efficiency and efficiency.
A wideband active RC filter bandwidth calibration circuit, the calibration circuit comprising: the device comprises a frequency divider, a resistance network, a capacitor charge-discharge switch, a comparator, a binary search algorithm module, a decoder and a digital-to-analog converter;
the frequency divider divides the input frequency of the external TCXO crystal oscillator to obtain a clock signal;
the capacitor charge-discharge switch is used for controlling the on-off of the charge and discharge of the resistor network and the capacitor network;
the charge and discharge nodes of the resistor network and the capacitor network are connected with one input end of the comparator, and the output of the digital-to-analog converter is connected with the other input end of the comparator; the digital-to-analog converter is used for converting the bandwidth adjustment control signal into a reference voltage;
the input of the binary search algorithm module is connected with the output of the comparator, and the output of the binary search algorithm module is connected with the input of the decoder; the binary search algorithm module is used for generating a filter bandwidth search code according to the output result of the comparator;
the decoder is used for converting the filter bandwidth searching code into the corresponding adjusting values of the resistor network and the capacitor network.
In one embodiment, the method further comprises the following steps: the resistor network is formed by connecting a series resistor network and a parallel resistor network in series; the capacitor network is formed by connecting a series capacitor network and a parallel capacitor network in parallel;
in one embodiment, the charging and discharging circuit further comprises a clock inverter, wherein the clock inverter is used for connecting the charging and discharging node after inverting the clock signal.
In one embodiment, the method further comprises the following steps: when the clock signal is at a low level, the capacitor network is in a charging state, and when the clock signal is at a high level, the capacitor network is in a discharging state.
In one embodiment, the method further comprises the following steps: the comparator and the binary search algorithm module operate on a rising edge of the clock signal.
In one embodiment, the method further comprises the following steps: the comparator is a self-calibration comparator with a direct current mismatch compensation function.
In one embodiment, the method further comprises the following steps: the output of the decoder is also connected to a main filter.
A method for calibrating the bandwidth of a wideband active RC filter, the method comprising:
setting the frequency dividing ratio of a frequency divider according to the input frequency of an external TCXO crystal oscillator to obtain a clock signal of a broadband active RC filter bandwidth calibration circuit;
determining a bandwidth adjustment control signal of a preset bandwidth according to a preset lookup table; the lookup table is a data table of the relationship between the filter bandwidth and the time constant values of the capacitor network and the resistor network;
converting the bandwidth adjustment control signal into a reference voltage through a digital-to-analog converter, and inputting the reference voltage into one input end of a comparator;
connecting the charge and discharge nodes of the resistor network and the capacitor network to the other input end of the comparator;
generating a corresponding filter bandwidth search code through a binary search algorithm module according to an output result of the comparator;
converting the filter bandwidth searching code into corresponding adjusting values of the resistor network and the capacitor network through a decoder according to the lookup table;
and adjusting the resistance network and the capacitance network according to the adjustment value to realize the calibration of the bandwidth of the broadband filter.
In one embodiment, the method further comprises the following steps: determining the bandwidth range and the design bandwidth precision of a filter;
selecting a section of lowest frequency band bandwidth range, fixing the resistance value of the resistance network, and determining the capacitance network according to the design precision;
fixing the capacitor network, sequentially reducing the resistance of the resistor network by times until all bandwidth ranges are covered, and determining a final resistor network;
copying the determined final capacitance-resistance network into a capacitance-resistance network of a calibration circuit in equal proportion;
and sequentially coding the capacitor network and the resistor network in the calibration circuit according to the size sequence of the bandwidth, and establishing a lookup table between the bandwidth and the time constant values of the resistor network and the capacitor network.
In one embodiment, the method further comprises the following steps: determining the bandwidth range and the design bandwidth precision of a filter;
selecting a section of lowest frequency band bandwidth range, fixing the capacitance value of the capacitor network, and determining the resistor network according to the design precision;
fixing the resistance network, sequentially reducing the capacitance of the capacitance network by times until all bandwidth ranges are covered, and determining a final capacitance network;
copying the determined final capacitance-resistance network into a capacitance-resistance network of a calibration circuit in equal proportion;
and sequentially coding the capacitor network and the resistor network in the calibration circuit according to the size sequence of the bandwidth, and establishing a lookup table between the bandwidth and the time constant values of the resistor network and the capacitor network.
The bandwidth calibration circuit and method of the broadband active RC filter have the following beneficial effects:
1) The resistor network and the capacitor network can be used for calibrating the bandwidth of the filter, so that the degree of freedom of bandwidth calibration is increased, the number of passive elements in the filter is greatly saved, particularly when the order of the filter is higher and the filter is applied to a software-defined radio multi-channel radio frequency transceiver, and the design processes of the resistor network and the capacitor network are given in detail;
2) Supporting a wide range of crystal oscillator input frequency ranges;
3) The hardware cost of the bandwidth calibration circuit is similar to that of the traditional bandwidth calibration circuit, and the bandwidth calibration circuit is simple in structure, easy to implement and convenient for industrial use.
Drawings
FIG. 1 is a block diagram of a circuit suitable for calibration of the bandwidth of a wideband filter in one embodiment;
FIG. 2 is a schematic flow chart of a method for calibrating the bandwidth of a broadband active RC filter in one embodiment;
FIG. 3 is a flow diagram of wideband filter bandwidth calibration in an exemplary embodiment;
FIG. 4 is a circuit diagram of an exemplary design of a wideband filter bandwidth calibration circuit in an exemplary embodiment;
FIG. 5 is a graph of the charging time constant of the RC network versus the input reference voltage in one embodiment;
fig. 6 shows the bandwidth calibration results of a 5 th order active RC filter designed in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
A wideband active RC filter bandwidth calibration circuit, as shown in fig. 1, wherein the calibration circuit comprises: the device comprises a frequency divider, a resistance network, a capacitor charge-discharge switch, a comparator, a binary search algorithm module, a decoder and a digital-to-analog converter;
the frequency divider divides the input frequency of the external TCXO crystal oscillator to obtain a clock signal;
the capacitor charge-discharge switch is used for controlling the on-off of the charge and discharge of the resistor network and the capacitor network;
the charge and discharge nodes of the resistor network and the capacitor network are connected with one input end of the comparator, and the output of the digital-to-analog converter is connected with the other input end of the comparator; the digital-to-analog converter is used for converting the bandwidth adjustment control signal into a reference voltage;
the input of the binary search algorithm module is connected with the output of the comparator, and the output of the binary search algorithm module is connected with the input of the decoder; the binary search algorithm module is used for generating a filter bandwidth search code according to the output result of the comparator;
the decoder is used for converting the filter bandwidth searching code into the corresponding adjusting values of the resistor network and the capacitor network.
In one embodiment, the method further comprises the following steps: the resistance network is formed by connecting a series resistance network and a parallel resistance network in series; the capacitor network is formed by connecting a series capacitor network and a parallel capacitor network in parallel;
in one embodiment, the charging and discharging circuit further comprises a clock inverter, wherein the clock inverter is used for connecting the charging and discharging nodes after inverting the clock signal.
In one embodiment, the method further comprises the following steps: when the clock signal is at a low level, the capacitor network is in a charging state, and when the clock signal is at a high level, the capacitor network is in a discharging state.
In one embodiment, the method further comprises the following steps: the comparator and binary search algorithm module operate on the rising edge of the clock signal.
In one embodiment, the method further comprises the following steps: the comparator is a self-calibration comparator with a direct current mismatch compensation function.
In one embodiment, the method further comprises the following steps: the output of the decoder is also connected to the main filter, so that the main filter can complete corresponding bandwidth setting after the calibration process is finished.
The working principle is as follows: when the falling edge of the clock CLK comes, the capacitor network is in a charging state, the charging time constant is RC, wherein R and C are the values of the resistor network and the capacitor network under the actual working condition respectively, and when the rising edge of the clock CLK comes, the output voltage value (the regulated voltage value) V of the resistor-capacitor network adj Comprises the following steps:
V adj (t)| t＝T/2 ＝V DD -V DD exp(-t/RC)| t＝T/2 (1)
where T is the clock period of CLK. When V is adj Is higher than a preset reference voltage value V ref When the frequency is large, the output result of the binary search algorithm is searched in the direction of reducing the bandwidth frequency by adjusting the value of the resistance-capacitance network through the decoder, and when V is less than V, the frequency is adjusted to be larger adj Than a predetermined reference voltage value V ref In hours, the binary search algorithm searches toward an increase in bandwidth frequency.
V ref The determination of (2) is determined by a calculation and search mode, and the calculation corresponding formula is as follows:
V ref ＝V DD -V DD exp(-t/R dom C dom )| t＝T/2 (2)
wherein R is dom And C dom The values of the resistor network and the capacitor network under the typical process angle and normal temperature condition and R corresponding to different bandwidth frequencies dom And C dom Is different, a bandwidth adjustment control signal generated by the SPI interface (or other type of chip configuration interface) generates the reference voltage value V via the DAC ref . In order to avoid the reduction of calibration accuracy caused by direct current offset introduced by the comparator, a self-calibration comparator with a direct current mismatch compensation function can be adopted.
A method for calibrating the bandwidth of a wideband active RC filter, as shown in fig. 2, the method comprising:
and 214, adjusting the resistance network and the capacitance network according to the adjustment value to realize the bandwidth calibration of the broadband filter.
The bandwidth calibration circuit and method for the broadband active RC filter have the following beneficial effects:
1) The resistor network and the capacitor network can be used for calibrating the bandwidth of the filter, so that the degree of freedom of bandwidth calibration is increased, the number of passive elements in the filter is greatly saved, particularly when the order of the filter is higher and the filter is applied to a software-defined radio multi-channel radio frequency transceiver, and the design processes of the resistor network and the capacitor network are given in detail;
2) Supporting a wide range of crystal oscillator input frequency ranges;
3) The hardware cost of the bandwidth calibration circuit is similar to that of the traditional bandwidth calibration circuit, and the bandwidth calibration circuit is simple in structure, easy to implement and convenient for industrial use.
It should be understood that, although the steps in the flowchart of fig. 2 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 2 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
In one embodiment, as shown in fig. 3, a flowchart for calibrating a bandwidth of a wideband filter proposed in the present invention includes:
1) Determining the bandwidth range and the bandwidth precision of a filter;
2) Determining the final design bandwidth precision under typical process angles and normal temperature conditions according to the influence of the working temperature range and the process deviation on the actual bandwidth;
3) Selecting a section of lowest frequency band bandwidth range, fixing a resistance (capacitance) value, and determining a capacitance (resistance) network according to design precision;
4) The method comprises the following steps of fixing a capacitor (resistor) network, sequentially reducing the number of resistors (capacitors) until all bandwidth ranges are covered, and determining a final resistor (capacitor) network;
5) Copying the determined final capacitance-resistance network into a capacitance-resistance network of a calibration circuit in equal proportion;
6) Sequentially coding the capacitance-resistance network in the calibration circuit according to the size sequence of the bandwidth, corresponding the corresponding codes to the input of the decoder, and establishing a lookup table among the bandwidth, the resistance network and the time constant value of the capacitance network;
7) And setting a proper frequency dividing ratio N according to the TCXO frequency, and generating a corresponding bandwidth adjustment control signal according to the lookup table and the formula (2).
Another embodiment, as shown in fig. 4, includes:
1) Determining the bandwidth range and the bandwidth precision of a filter;
the frequency range of the baseband bandwidth covered by the filter is 1-30.4 MHz, and the bandwidth precision of the filter is less than 10%.
2) Determining the final design bandwidth precision under the conditions of a typical process angle and normal temperature according to the influence of the working temperature range and the process deviation on the actual bandwidth;
and finally determining to design according to 5% of filter bandwidth precision under typical process angles and normal temperature conditions according to the process deviation of the selected process and the sensitivity to the temperature.
3) Selecting a section of lowest frequency band bandwidth range, fixing a resistance value, and determining a capacitance network according to design precision;
the bandwidth range of the selected lowest frequency band is 1-1.9 MHz, and the bandwidth precision is 5%, so that the step can be determined to be 0.1MHz, and 10 frequency points are calculated, so that under the condition that the resistance value of the resistor is fixed, the capacitance network needs 10 different capacitance values.
4) The resistors of the fixed capacitor network are sequentially multiplied until all bandwidth ranges are covered, and a final resistor network is determined;
the resistance is reduced by times, the bandwidth and the stepping are increased by times, and 5 frequency range ranges of 1-1.9 MHz/0.1MHz, 2-3.8 MHz/0.2MHz, 4-7.6 MHz/0.4MHz, 8-15.2 MHz/0.8MHz and 16-30.4 MHz/1.6MHz are needed after all bandwidth ranges are covered. In the figure, a series resistance network consisting of 1 resistor is connected in series with a parallel resistance network consisting of 4 parallel resistance networks to form a total resistance network, and the values of the resistance network can generate 5 conditions: 8R 0 、4R 0 、2R 0 、R 0 、R 0 And 2, each resistance value can cover the bandwidth frequency of the filter of 1-30.4 MHz only by sequentially matching 10 different parallel capacitor network values.
5) Copying the determined final capacitance-resistance network into a capacitance-resistance network of a calibration circuit in equal proportion;
the rc network after the equal-scale replication is shown in fig. 4.
6) Sequentially coding the capacitance-resistance network in the calibration circuit according to the size sequence of the bandwidth, corresponding the codes to the input of the decoder, and establishing a lookup table among the bandwidth, the time constant values of the resistance network and the capacitance network;
the filters can provide 50 bandwidth values in total, and the encoding is carried out sequentially from small to large, and the filter can correspond to the input of a 6-bit decoder. Wherein "000000" corresponds to the minimum bandwidth of the filter bandwidth and "110001 to 111111" corresponds to the maximum value of the filter bandwidth. Sequentially providing a lookup table among the bandwidth, the time constant values of the resistance network and the capacitance network;
7) And setting a proper frequency dividing ratio N according to the TCXO frequency, and generating a corresponding bandwidth adjustment control signal according to the lookup table and the formula (2).
The software defines the TCXO frequency input range required for the radio application scenario to be 7.5-120 MHz,according to the formula (2), in order to avoid V ref The division ratio N can provide four division cases: x 2, × 1,/2,/4 to ensure that the frequency range of the charge and discharge clock CLK is between 15 and 30 MHz. Finding out the time constant value corresponding to the preset bandwidth according to the lookup table among the bandwidth, the time constant values of the resistor network and the capacitor network, and substituting the time constant value into the formula (2) to obtain the preset V ref And finally obtaining the bandwidth adjustment control signal which should be input.
FIG. 5 shows the charging time constant of the RC network and the input reference voltage V ref Graph of the relationship between the charge and discharge clocks (the frequency of the charge and discharge clock is 15MHz DD ＝1.8V)。
At minimum clock frequency and requirement V ref The maximum value of the time constant of the resistance-capacitance network, namely R, can be obtained under the condition that the minimum value is 0.15V dom C dom ＝4*10 -7 s, which is an important constraint in designing a resistor-capacitor network.
Fig. 6 shows the bandwidth calibration result of a 5 th order active RC filter designed according to the above design example (the preset baseband bandwidth is 20.8 MHz).
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent application shall be subject to the appended claims.
Claims (8)
1. A wideband active RC filter bandwidth calibration circuit, the calibration circuit comprising: the device comprises a frequency divider, a resistance network, a capacitor charge and discharge switch, a comparator, a binary search algorithm module, a decoder and a digital-to-analog converter;
the frequency divider divides the input frequency of the external TCXO crystal oscillator to obtain a clock signal;
the capacitor charge-discharge switch is used for controlling the on-off of the charge and discharge of the resistor network and the capacitor network;
the charge and discharge nodes of the resistor network and the capacitor network are connected with one input end of the comparator, and the output of the digital-to-analog converter is connected with the other input end of the comparator; the digital-to-analog converter is used for converting the bandwidth adjustment control signal into a reference voltage; the determination formula of the reference voltage is as follows:
V ref ＝V DD -V DD exp(-t/R dom C dom )| t＝T/2
wherein, V ref Is a reference voltage, T is a clock period, R dom And C dom The values of the resistor network and the capacitor network are respectively at a typical process angle and under a normal temperature condition;
the bandwidth adjustment control signal is determined according to a pre-established lookup table; the lookup table is a data table of the relationship between the filter bandwidth and the time constant values of the capacitor network and the resistor network; the setting process of the lookup table comprises the following steps:
determining the bandwidth range and the design bandwidth precision of a filter;
selecting a section of lowest frequency band bandwidth range, if the capacitance value of the capacitor network is fixed, determining the resistor network according to design precision, fixing the resistor network, and sequentially reducing the capacitance of the capacitor network by times until all the bandwidth ranges are covered, and determining the final capacitor network; if the resistance value of the resistance network is fixed, determining a capacitance network according to design precision, fixing the capacitance network, sequentially reducing the resistance of the resistance network until all bandwidth ranges are covered, and determining a final resistance network;
copying the determined final capacitance-resistance network into a capacitance-resistance network of a calibration circuit in equal proportion;
sequentially coding the capacitor network and the resistor network in the calibration circuit according to the size sequence of the bandwidth, and establishing a lookup table between the bandwidth and the time constant values of the resistor network and the capacitor network;
the input of the binary search algorithm module is connected with the output of the comparator, and the output of the binary search algorithm module is connected with the input of the decoder; the binary search algorithm module is used for generating a filter bandwidth search code according to the output result of the comparator;
the decoder is used for converting the filter bandwidth searching code into the corresponding adjusting values of the resistor network and the capacitor network.
2. The calibration circuit of claim 1, the resistor network being formed by a series resistor network and a parallel resistor network connected in series; the capacitor network is formed by connecting a series capacitor network and a parallel capacitor network in parallel.
3. The calibration circuit of claim 1, further comprising a clock inverter, wherein the clock inverter is configured to invert the clock signal and connect the inverted clock signal to the charge and discharge nodes.
4. The calibration circuit of claim 1, wherein the capacitive network is in a charged state when the clock signal is low and in a discharged state when the clock signal is high.
5. The calibration circuit of claim 1, wherein the comparator and the binary search algorithm module operate on a rising edge of the clock signal.
6. The calibration circuit of claim 1, wherein the comparator is a self-calibration comparator with dc mismatch compensation.
7. The calibration circuit of claim 1, wherein the output of the decoder is further coupled to a main filter.
8. A wideband active RC filter bandwidth calibration method applied to the wideband active RC filter bandwidth calibration circuit of any one of claims 1 to 7, the method comprising:
setting the frequency dividing ratio of a frequency divider according to the input frequency of an external TCXO crystal oscillator to obtain a clock signal of a broadband active RC filter bandwidth calibration circuit;
determining a bandwidth adjustment control signal of a preset bandwidth according to a preset lookup table; the lookup table is a data table of the relationship between the filter bandwidth and the time constant values of the capacitor network and the resistor network; the setting process of the lookup table comprises the following steps:
determining the bandwidth range and the design bandwidth precision of a filter;
selecting a section of lowest frequency band bandwidth range, if the capacitance value of the capacitor network is fixed, determining the resistor network according to design precision, fixing the resistor network, and sequentially reducing the capacitance of the capacitor network by times until all the bandwidth ranges are covered, and determining the final capacitor network; if the resistance value of the resistance network is fixed, determining a capacitance network according to design precision, fixing the capacitance network, sequentially reducing the resistance of the resistance network until all bandwidth ranges are covered, and determining a final resistance network;
copying the obtained final capacitance-resistance network into a capacitance-resistance network of a calibration circuit in equal proportion;
sequentially coding the capacitor network and the resistor network in the calibration circuit according to the size sequence of the bandwidth, and establishing a lookup table between the bandwidth and the time constant values of the resistor network and the capacitor network;
converting the bandwidth adjustment control signal into a reference voltage through a digital-to-analog converter, and inputting the reference voltage into one input end of a comparator; the determination formula of the reference voltage is as follows:
V ref ＝V DD -V DD exp(-t/R dom C dom )| t＝T/2
wherein, V ref Is a reference voltage, T is a clock period, R dom And C dom The values of the resistor network and the capacitor network are respectively at a typical process angle and under a normal temperature condition;
connecting the charge and discharge nodes of the resistor network and the capacitor network to the other input end of the comparator;
generating a corresponding filter bandwidth search code through a binary search algorithm module according to an output result of the comparator;
converting the filter bandwidth searching code into corresponding adjusting values of the resistor network and the capacitor network through a decoder according to the lookup table;
and adjusting the resistance network and the capacitance network according to the adjustment value to realize the calibration of the bandwidth of the broadband filter.
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