CN113764173B

CN113764173B - Planar transformer structure integrated with Y capacitor

Info

Publication number: CN113764173B
Application number: CN202111202503.3A
Authority: CN
Inventors: 钱钦松; 徐诗云; 许胜有; 孙伟锋; 时龙兴
Original assignee: Southeast University-Wuxi Institute Of Integrated Circuit Technology; Southeast University
Current assignee: Southeast University-Wuxi Institute Of Integrated Circuit Technology; Southeast University
Priority date: 2021-10-15
Filing date: 2021-10-15
Publication date: 2023-08-15
Anticipated expiration: 2041-10-15
Also published as: CN113764173A

Abstract

The invention discloses a planar transformer integrated with a Y capacitor, and relates to the field of electromagnetic compatibility and magnetic component design. The primary winding and the secondary winding are staggered, and the parasitic capacitance of the primary winding and the secondary winding improves the noise conduction path of the secondary rectifying diode. One end of the auxiliary winding is connected with the primary side ground, the other end of the auxiliary winding is suspended, and an integrated Y Capacitor (CY) is formed with the secondary side winding, so that the noise conduction paths of the primary side switching tube and the secondary side rectifier diode are improved. On the premise of keeping the advantages of low leakage inductance and high efficiency of the planar transformer with the complete cross transposition structure, the parasitic capacitance between the primary side winding and the secondary side winding is utilized, so that the planar transformer becomes a low impedance path for guiding noise, the adverse effect caused by the inter-stage capacitance is almost eliminated, and the interference of the switching power supply on external conduction noise can be effectively reduced. Meanwhile, the area of the switching power supply can be further reduced by integrating the Y capacitor, so that the miniaturization of the switching power supply is facilitated, and the power density of the switching power supply is improved.

Description

Planar transformer structure integrated with Y capacitor

Technical Field

The invention relates to the technical field of switching power supplies, in particular to electromagnetic compatibility and magnetic component design.

Background

With the rapid development of portable electronic devices, there is an increasing demand for an increase in the charging speed and a decrease in the volume of the charging device. Increasing the switching frequency is an effective means of reducing the size and increasing the efficiency, but exacerbates the EMI problem of switching power supplies.

Planar transformers offer significant advantages in height, volume and mass over conventional transformers, while parasitic capacitance is easier to control and can be exploited as a path for noise return. The thin structure of the planar transformer conductor can reduce the influence caused by the high-frequency effect, thereby reducing the loss. Meanwhile, the primary side and the secondary side in the planar transformer structure are more tightly coupled, so that leakage inductance can be reduced, and extra noise caused by the leakage inductance is reduced. The staggered arrangement of the planar transformer windings can reduce leakage inductance of the transformer and loss of the transformer, but can bring about larger inter-stage capacitance, thereby bringing about adverse effects on EMI, and meanwhile, the design of the shielding layer is difficult.

The Y capacitor can effectively reduce common mode interference in the high frequency band, but adding the Y capacitor often requires designing an additional loop and using an additional safety capacitor, and may cause difficulties in PCB wiring. And longer PCB routing and parasitic inductances of capacitor pins, contacts, etc., can degrade Y capacitance performance.

Disclosure of Invention

Technical problems: aiming at the technical problem brought by adding the Y capacitor, the invention provides a planar transformer structure integrating the Y capacitor. The structure makes use of the parasitic capacitance between the primary side winding and the secondary side winding to become a low impedance path for guiding noise on the premise of keeping the advantages of low leakage inductance and high efficiency of the planar transformer with the complete cross transposition structure, almost eliminates the adverse effect caused by the inter-stage capacitance, and can effectively reduce the interference of the switching power supply to external conduction noise. Meanwhile, the area of the switching power supply can be further reduced by integrating the Y capacitor, so that the miniaturization of the switching power supply is facilitated, and the power density of the switching power supply is improved.

The technical scheme is as follows: in order to solve the technical problems, the invention provides a planar transformer integrated with a Y capacitor, which comprises a primary side winding, a secondary side winding, an auxiliary winding, a top magnetic core and a base magnetic core; the primary side windings and the secondary side windings are staggered; the auxiliary winding is positioned beside the secondary winding at the lowest part, one port of the auxiliary winding is connected with the primary side of the primary side in the ground, and the other port of the auxiliary winding is suspended to form an integrated Y capacitor with the secondary winding; the two ports of the primary side winding are a first port and a second port respectively, the first port is connected with a primary side external circuit hot spot, and the second port is connected with a primary side external circuit cold spot; the two ports of the secondary side winding are a third port and a fourth port respectively, the third port is connected with a secondary side external circuit cold point, and the fourth port is connected with a secondary side external circuit hot point; the cold point is a point where the voltage does not change when the circuit works, and the hot point is a point where the voltage changes when the circuit works.

Wherein:

a first parasitic capacitance is formed between the first port and the fourth port, a second parasitic capacitance is formed between the second port and the fourth port, a third parasitic capacitance is formed between the second port and the third port, the second parasitic capacitance and the third parasitic capacitance provide a low-impedance flow path for noise generated by the secondary rectifying diode, and noise current does not flow back to the secondary rectifying diode through the ground; other parasitic capacitances between the primary side winding and the secondary side winding are small and negligible.

One port of the auxiliary winding is connected with the primary side of the primary side in the ground, and the other port of the auxiliary winding is suspended; the auxiliary winding and the secondary winding form an integrated Y capacitor, and two ends of the integrated Y capacitor are respectively connected with a secondary side third port and a primary side ground, so that noise current flowing into a secondary side cold point through other parasitic capacitors by a primary side switching tube flows back to the switching tube through the integrated Y capacitor.

The number of turns and the number of layers of each layer of the primary side winding and the secondary side winding are adjustable so as to meet the design of various turn ratios.

The integrated Y capacitance between the cold points of the auxiliary winding and the secondary winding and other parasitic capacitances between the primary winding and the secondary winding meet the calculation formula of the capacitance value of the plate capacitor: c=εs/d. The facing area S between the windings is estimated by an area calculation formula of a circular ring, the dielectric constant epsilon is determined by the selected PCB, and the plate distance d is determined by the thickness of an insulating layer of the PCB.

The line widths of each layer of the primary side winding, the secondary side winding and the auxiliary winding are as large as possible so as to obtain the lowest loss and the largest parasitic capacitance opposite area S, thereby obtaining the highest efficiency and the largest parasitic capacitance value.

The parasitic capacitance between the auxiliary winding and the ports other than the third port where the secondary side cold point is located is small.

And partial noise generated by the secondary side rectifying diode flows back to the secondary side rectifying diode through an integrated Y capacitor, a primary side ground, a bus capacitor, a primary side positive parasitic capacitor and a secondary side second parasitic capacitor formed by the auxiliary winding.

The beneficial effects are that: compared with the prior art, the invention has the beneficial effects that:

1. the Y capacitor is integrated into the planar transformer, and no additional separation component is needed, so that parasitic inductance of a PCB wiring, a capacitor pin, a contact point and the like is avoided, the area of the PCB can be reduced, and the miniaturization of the switching power supply is facilitated.

2. The invention fully utilizes the parasitic capacitance between the primary winding and the secondary winding, so that the parasitic capacitance becomes a low-impedance path for guiding noise, the adverse effect caused by the inter-stage capacitance is almost eliminated, and the interference of high-frequency conduction noise outside the switching power supply can be effectively reduced.

3. The invention can also keep the advantages of low leakage inductance and high efficiency of the complete cross transposition structure of the primary side winding and the secondary side winding under the condition of not adding a shielding layer, thereby reducing noise interference possibly caused by the leakage inductance and improving the efficiency of the switching power supply.

Drawings

Fig. 1 is a schematic diagram of a planar transformer integrated with Y-capacitors according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of a conventional discrete device Y capacitor structure according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of a planar transformer integrated Y capacitor structure according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of a noise main conduction path according to an embodiment of the present invention.

The drawings are as follows:

1. a primary winding;

2. a secondary side winding;

3. an auxiliary winding;

4. a top magnetic core;

5. a base magnetic core;

NC. suspended in the air

A: a first port; i.e. the point where the primary winding is connected to the primary external circuit hot spot;

b: a second port; i.e. the point where the primary winding is connected to the cold point of the primary external circuit;

c: a third port; namely, the point at which the secondary side winding is connected with the cold point of the secondary side external circuit;

d: a fourth port; namely, the point where the secondary side winding is connected with the secondary side external circuit hot spot;

CY: integrating a Y capacitor; i.e. an integrated Y-capacitor formed by the auxiliary winding and the secondary winding distributed capacitance;

PGND: primary side land;

vin: the primary side is positive;

cad: a first parasitic capacitance; i.e. parasitic capacitance between the first port a and the fourth port D;

cbd: a second parasitic capacitance; i.e. parasitic capacitance between the second port B and the fourth port D;

cbc: a third parasitic capacitance; i.e. parasitic capacitance between the second port B and the third port C;

cac: a fourth parasitic capacitance; i.e. parasitic capacitance between the first port a and the third port C;

cab: a fifth parasitic capacitance; i.e. parasitic capacitance between the first port a and the second port B;

ccd: a sixth parasitic capacitance; i.e. parasitic capacitance between the third port C and the fourth port D;

q1: a switching tube;

d1: a rectifier diode;

lm: exciting inductance;

lr: leakage inductance;

RL: a load;

co: an output capacitance;

cbus: a bus capacitor;

ce: secondary cold spot capacitance to ground.

Detailed Description

The invention relates to a planar transformer integrated with a Y capacitor, which comprises a primary side winding 1, a secondary side winding 2, an auxiliary winding 3, a top magnetic core 4 and a base magnetic core 5; the primary side winding 1 and the secondary side winding 2 are arranged in a staggered manner; the auxiliary winding 3 is positioned beside the secondary side winding 2, one end of the auxiliary winding 3 is connected with the primary side ground PGND, and an integrated Y capacitor CY is formed with the secondary side winding 2; the two ports of the primary winding 1 are a first port A and a second port B respectively, the first port A is connected with a primary external circuit hot spot, and the second port B is connected with a primary external circuit cold spot; the two ports of the secondary side winding 2 are a third port C and a fourth port D respectively, the third port C is connected with a secondary side external circuit cold point, and the fourth port D is connected with a secondary side external circuit hot point; the cold point is a point where the voltage does not change when the circuit works, and the hot point is a point where the voltage changes when the circuit works.

The invention is described in further detail below with reference to the accompanying drawings.

Fig. 1 shows a typical planar transformer structure with integrated Y-capacitor, wherein the first layer and the third layer from top to bottom are primary windings, each layer has 2 turns, the two layers of windings are connected in series, two ports of the primary windings are respectively a first port a and a second port B, the first port a is connected with a primary hot spot, and the second port B is connected with a primary cold spot; the second layer and the fourth layer are secondary side windings, each layer is provided with 1 turn, the two layers of windings are connected in series, two ports of the secondary side windings are respectively provided with a third port C and a fourth port D, the third port C is connected with a secondary side cold point, and the fourth port D is connected with a secondary side hot point; the fifth layer is an auxiliary winding, one port of the auxiliary winding is connected with the primary ground PGND, and the other port of the auxiliary winding is suspended; the cold point is the point that the voltage does not change when the circuit works, and the hot point is the point that the voltage changes when the circuit works. The size of the magnetic core adopted in the structure is EQ20, and the material of the magnetic core is 3F46. The width of the winding is as large as possible, so that copper loss can be reduced, parasitic capacitance can be increased, and a lower-impedance conduction path is provided for high-frequency noise.

As shown in fig. 1, the planar transformer winding structure integrated with the Y capacitor is a complete cross transposition structure and has the advantages of low leakage inductance and high efficiency. Parasitic capacitances that have a significant impact on the circuit in this structure are: the first parasitic capacitance Cad, the second parasitic capacitance Cbd, the third parasitic capacitance Cbc, and the integrated Y capacitance CY. The capacitance values of other parasitic capacitances are all 1-2 orders of magnitude lower than the four parasitic capacitance values, and can be ignored.

In a preferred embodiment, the transformer structure proposed by the present invention is applied to a flyback converter. Fig. 2 is a schematic diagram of the structure of a conventional integrated Y capacitor of a discrete device, where a discrete safety capacitor is connected to a primary side ground PGND and a secondary side cold point, i.e., a third port C, through PCB traces, respectively. This structure requires additional loops to be designed and additional safety capacitors to be used, and may present difficulties in PCB routing. And longer PCB routing and parasitic inductances of capacitor pins, contacts, etc. can degrade the performance of the integrated Y-capacitor.

Fig. 3 is a schematic circuit stage diagram of the planar transformer integrated Y-capacitor structure according to the present invention. The integrated Y capacitor is realized by the parasitic capacitance between the auxiliary winding and the secondary side winding connected with the secondary side cold point, namely the third port C, namely the integrated Y capacitor CY, and additional discrete devices and loops are not needed, so that the area of the PCB can be reduced, and the miniaturization of the switching power supply is facilitated. The two integrated Y-capacitor implementations shown in fig. 2 and 3 are completely equivalent to improve the effect of the high frequency noise conduction path, so that the auxiliary winding can be omitted and the structure shown in fig. 2 can be used for the equivalent when analyzing the high frequency noise conduction path of the integrated Y-capacitor implementation shown in fig. 3.

Fig. 4 shows the high frequency noise conduction path of a flyback converter employing the Y-capacitor integrated planar transformer structure of the present invention, illustrating the effect of such Y-capacitor integrated planar transformer structure on reducing conducted EMI. The auxiliary winding is omitted from fig. 4 and replaced with an equivalent integrated Y capacitor to facilitate high frequency noise conduction path analysis. For flyback converters, the most dominant sources of noise are the switching tubes on the primary side and the rectifier diodes on the secondary side. For a common planar transformer structure, high-frequency noise generated by a primary side switching tube can flow into the ground through an interstage capacitor together with noise generated by a secondary side rectifying diode through a parasitic capacitor (usually a capacitor to the ground such as a radiating fin) of the secondary side, so that the high-frequency noise flows into an L arm and an N arm of the LISN at the same time, is detected by the LISN as high-frequency common mode noise, and finally flows back to the switching tube and the rectifying diode through wires and other capacitors, and therefore the switching power supply product can not meet the EMI test standard.

The mode of reducing the common mode interference is to add a shielding layer between the primary side winding and the secondary side winding, so that the inter-stage capacitance can be greatly reduced, and high-frequency noise generated by the switching tube is difficult to flow into the secondary side and then flow into the ground through the inter-stage capacitance. However, the addition of the shielding layer can effectively reduce high-frequency common mode noise, but can reduce the coupling coefficient of the primary side winding and the secondary side winding, so that leakage inductance is increased; meanwhile, if the windings adopt a cross transposition structure, a plurality of shielding layers are needed, the design of the shielding layers is very complex, and meanwhile, larger passive loss can be brought.

The mode of reducing common mode interference adopted by the invention is to add a conduction path with lower impedance besides the parasitic capacitance of the secondary side to the ground, so that noise flows back to a noise source through other conduction paths instead of passing through the ground, and therefore, the noise does not flow through the LISN, and the effect of improving high-frequency EMI is achieved. Fig. 2 shows the main conduction path of high frequency noise in the flyback converter circuit after the planar transformer winding structure of the integrated Y-capacitor shown in fig. 1 is used. Parasitic capacitances in planar transformer winding structures that have significant impact on the circuit are: the first parasitic capacitance Cad, the second parasitic capacitance Cbd, the third parasitic capacitance Cbc, the integrated Y capacitance CY, the bus capacitance Cbus and the output capacitance Co in the circuit are all capacitances with large capacitance values, and can be regarded as short circuits at high frequencies, so that the capacitances can be regarded as main paths of high-frequency noise conduction. Other parasitic capacitances are relatively large in impedance due to their negligible size and are therefore not the main path for high frequency noise conduction.

The dashed arrow in fig. 4 shows the main conduction path of the primary side switching tube high frequency noise. The high-frequency noise generated by the switch tube Q1 is conducted to the secondary side cold point (C point shown in fig. 4) through any way, so long as the capacitance value of the integrated Y capacitor CY is far greater than the parasitic capacitance value of the secondary side to the ground, most of the noise can flow back to the primary side switch tube through the integrated Y capacitor CY, and therefore high-frequency EMI is improved. The path with the lowest impedance is through parasitic capacitance Cad, diode D1, output capacitance Co to the cold point, most of the noise flowing back through integrated Y capacitance CY.

The solid arrows in fig. 4 show the primary conduction path of the secondary side rectifier diode high frequency noise. The high frequency noise generated by the rectifier diode D1 is mostly conducted to the cold spot through the output capacitor Co, and there are two low impedance conduction paths in the circuit: one is that the current sequentially passes through the parasitic capacitance, namely a third parasitic capacitance Cbc and a second parasitic capacitance Cbd, and finally flows back to the rectifying diode D1; the other path with a slightly larger impedance is conducted to the primary side through the integrated Y capacitor CY, then conducted to the primary side L line from the primary side N line through the bus capacitor, and finally reflowed through the second parasitic capacitor Cbd. Due to the presence of these two low impedance conductive paths, most of the high frequency noise generated by the rectifier diode D1 will not flow into ground through the parasitic capacitance of the secondary side to ground and will not be detected by the LISN.

The above specific embodiments and examples are specific support for the technical idea of the planar transformer integrated with the Y capacitor provided by the present invention, and the protection scope of the present invention cannot be limited by the specific support, and any equivalent change or equivalent modification made on the basis of the technical scheme according to the technical idea provided by the present invention still belongs to the protection scope of the technical scheme of the present invention.

Claims

1. A planar transformer integrated with a Y capacitor, which is characterized by comprising a primary side winding (1), a secondary side winding (2), an auxiliary winding (3), a top magnetic core (4) and a base magnetic core (5); the primary side windings (1) and the secondary side windings (2) are arranged in a staggered manner; the auxiliary winding (3) is positioned beside the secondary side winding (2) at the lowest part, one port of the auxiliary winding (3) is connected with the primary side ground (PGND), and the other port is suspended (NC) to form an integrated Y Capacitor (CY) with the secondary side winding (2); the two ports of the primary winding (1) are a first port (A) and a second port (B) respectively, the first port (A) is connected with a primary external circuit hot spot, and the second port (B) is connected with a primary external circuit cold spot; two ports of the secondary side winding (2) are a third port (C) and a fourth port (D) respectively, the third port (C) is connected with a cold point of the secondary side external circuit, and the fourth port (D) is connected with a hot point of the secondary side external circuit; the cold point is a point where the voltage does not change when the circuit works, and the hot point is a point where the voltage changes when the circuit works.

2. A planar transformer integrated with Y capacitor according to claim 1, wherein a first parasitic capacitor (Cad) is formed between the first port (a) and the fourth port (D), a second parasitic capacitor (Cbd) is formed between the second port (B) and the fourth port (D), a third parasitic capacitor (Cbc) is formed between the second port (B) and the third port (C), and the second parasitic capacitor (Cbd) and the third parasitic capacitor (Cbc) provide a low impedance flow path for noise generated by the secondary rectifying diode (D1), and noise current flows back to the secondary rectifying diode (D1) without going through the ground; other parasitic capacitances between the primary winding (1) and the secondary winding (2) are small and negligible.

3. A planar transformer integrated with Y-capacitors according to claim 1, characterized in that said auxiliary winding (3) has one port connected to primary side Primary Ground (PGND) and the other port floating (NC); the auxiliary winding (3) and the secondary winding (2) form an integrated Y Capacitor (CY), and two ends of the integrated Y Capacitor (CY) are respectively connected with a secondary side third port (C) and a primary side ground (PGND), so that noise current flowing into a secondary side cold point through other parasitic capacitors by a primary side switching tube (Q1) flows back to the switching tube (Q1) through the integrated Y Capacitor (CY).

4. The planar transformer integrated with the Y capacitor according to claim 1, wherein the number of turns and the number of layers of each layer of the primary side winding (1) and the secondary side winding (2) are adjustable to meet various turn ratio designs.

5. -a planar transformer integrating Y-capacitance according to claim 1, characterized in that the integrated Y-Capacitance (CY) between the auxiliary winding (3) and the secondary winding cold point and the other parasitic capacitances between the primary winding (1) and the secondary winding (2) satisfy the calculation formula of the planar capacitor capacitance value: c=εs/d. The facing area S between the windings is estimated by an area calculation formula of a circular ring, the dielectric constant epsilon is determined by the selected PCB, and the plate distance d is determined by the thickness of an insulating layer of the PCB.

6. The planar transformer integrated with the Y capacitor according to claim 1, wherein each layer of the primary winding (1), the secondary winding (2) and the auxiliary winding (3) has a line width as large as possible to obtain the lowest loss and the largest parasitic capacitance facing area S, thereby obtaining the highest efficiency and the largest parasitic capacitance value.

7. A planar transformer integrating Y-capacitance according to claim 1, characterized in that the parasitic capacitance between the auxiliary winding (3) and the port other than the third port (C) where the secondary side cold point is located is small.

8. The Y-capacitor integrated planar transformer according to claim 1, wherein part of noise generated by the secondary rectifying diode (D1) flows back to the secondary rectifying diode (D1) through the integrated Y-Capacitor (CY), primary Ground (PGND), bus capacitor (Cbus), primary positive (Vin), primary and secondary second parasitic capacitors (Cbd) formed by the auxiliary winding (3).