CN113763861A

CN113763861A - Display panel, driving method thereof and display device

Info

Publication number: CN113763861A
Application number: CN202111101405.0A
Authority: CN
Inventors: 唐艳芳; 黄敏; 黄建才
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2021-09-18
Filing date: 2021-09-18
Publication date: 2021-12-07

Abstract

The invention provides a display panel, a driving method thereof and a display device, wherein the display panel comprises a plurality of pixel units, and each pixel unit at least comprises a first color sub-pixel, a second color sub-pixel and a third color sub-pixel; the display device comprises a plurality of driving circuit units, a plurality of driving circuit units and a control unit, wherein the driving circuit units at least comprise a first driving circuit, a second driving circuit and a third driving circuit, in a display stage, the first driving circuit provides a first driving voltage for a first color sub-pixel, the second driving circuit provides a second driving voltage for a second color sub-pixel, and the third driving circuit provides a third driving voltage for a third color sub-pixel; the luminous efficiency of the first color sub-pixel is lower than that of the second color sub-pixel and the third color sub-pixel, and the duty ratio of the first driving voltage is larger than that of the second driving voltage and the third driving voltage. The invention ensures that the display panel and the display device have more uniform brightness.

Description

Display panel, driving method thereof and display device

Technical Field

The invention relates to the technical field of display, in particular to a display panel, a driving method thereof and a display device.

Background

With the increasing demand of people on terminal display, Micro-LEDs become a hot spot technology in the display market in recent years, and compared with the display technologies such as mass-produced LCDs and OLEDs, Micro-LEDs have more excellent performance in technical dimensions such as brightness, color, viewing angle, contrast, resolution, and lifetime.

At present, Micro-LED display panels need to be produced in a real sense, and some technical difficulties need to be overcome, for example, the existing Micro-LED elements with different colors have different light emitting efficiencies due to factors such as materials, the Micro-LED elements with different colors forming the display panel will inevitably cause non-uniform brightness of the display panel, and the corresponding on-resistance of the Micro-LED elements with relatively low light emitting efficiency is relatively large, if the voltage or current provided by the display panel to each element is consistent, the heating of the display panel is not uniform, and the power consumption of the display panel is also relatively large, so it is urgently needed that technical staff can provide a display panel and a display device with uniform display brightness and device heating.

Disclosure of Invention

In view of this, embodiments of the present invention provide a display panel, a driving method thereof, and a display apparatus, which can make display brightness and device heat of the display panel and the display apparatus more uniform.

In a first aspect, the present application provides a display panel comprising:

the pixel unit at least comprises a first color sub-pixel, a second color sub-pixel and a third color sub-pixel;

the display device comprises a plurality of driving circuit units, a plurality of driving circuit units and a control unit, wherein the driving circuit units at least comprise a first driving circuit, a second driving circuit and a third driving circuit, in a display stage, the first driving circuit provides a first driving voltage for a first color sub-pixel, the second driving circuit provides a second driving voltage for a second color sub-pixel, and the third driving circuit provides a third driving voltage for a third color sub-pixel;

the luminous efficiency of the first color sub-pixel is lower than that of the second color sub-pixel and the third color sub-pixel, and the duty ratio of the first driving voltage is larger than that of the second driving voltage and the third driving voltage.

In a second aspect, the present application provides a display device including the display panel.

In a third aspect, the present application provides a driving method of a display panel, applied to the display panel provided in the first aspect and the display device provided in the second aspect, the driving method comprising:

the display panel comprises a plurality of pixel units, each pixel unit at least comprises a first color sub-pixel, a second color sub-pixel and a third color sub-pixel, and the luminous efficiency of the first color sub-pixel is lower than that of the second color sub-pixel and the third color sub-pixel;

the display panel comprises a plurality of driving circuit units, wherein the driving circuit units at least comprise a first driving circuit, a second driving circuit and a third driving circuit, in the display stage, the first driving circuit provides a first driving voltage for the first color sub-pixel, the second driving circuit provides a second driving voltage for the second color sub-pixel, and the third driving circuit provides a third driving voltage for the third color sub-pixel;

in the display phase, the duty ratio of the first driving voltage is larger than the duty ratios of the second driving voltage and the third driving voltage.

The duty ratio of the first driving voltage is set to be larger than the duty ratios of the second driving voltage and the third driving voltage, so that the light-emitting duration of the first color sub-pixel is larger than that of the second color sub-pixel and the third color sub-pixel, and the phenomenon that the light-emitting efficiency of the first color sub-pixel is low can be compensated, so that the light-emitting luminance of the first color sub-pixel, the light-emitting luminance of the second color sub-pixel and the light-emitting luminance of the third color sub-pixel are basically consistent, the resistance corresponding to the light-emitting element of the first color sub-pixel is larger, the light-emitting power of the first color sub-pixel, the light-emitting power of the second color sub-pixel and the light-emitting power of the third color sub-pixel are equivalent and the heat-emitting power is basically consistent by increasing the time that the first driving voltage is an effective signal, so that the display panel has the more consistent luminance and heat-emitting degree, and is beneficial to reducing the whole power consumption of the display panel, and the driving method only needs to change the duty ratio of the voltage, the manufacturing process and the driving circuit do not need to be changed, so that the display panel can obtain better mass production.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that are required in the description of the embodiments will be briefly introduced, the drawings described herein are provided to provide further understanding of the present invention and constitute a part of the present invention, and the exemplary embodiments and descriptions thereof of the present invention are provided for explaining the present invention and do not constitute a limitation of the present invention.

Fig. 1 is a schematic top view of a display panel according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a driving circuit according to an embodiment of the invention;

FIG. 3 is a timing diagram of one of the driving circuits shown in FIG. 2;

FIG. 4 is a schematic diagram of the driving voltage provided by the different driving circuits shown in FIG. 2 varying with driving time;

FIG. 5 is another schematic diagram of the driving voltage provided by the different driving circuits shown in FIG. 2 varying with driving time;

FIG. 6 is a schematic diagram of the driving voltage provided by the different driving circuits shown in FIG. 2 varying with driving time;

FIG. 7 is a further schematic diagram of the driving voltage provided by the different driving circuits shown in FIG. 2 as a function of driving time;

FIG. 8 is a schematic top view of another display panel according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of a driving timing sequence of a display panel according to an embodiment of the present invention;

FIG. 10 is a schematic top view of another display panel according to an embodiment of the present invention;

FIG. 11 is a schematic top view of another display panel according to an embodiment of the present invention;

FIG. 12 is a schematic top view of another display panel according to an embodiment of the present invention;

FIG. 13 is a schematic diagram of the driving voltage provided by the driving circuit for different display partitions according to the embodiment of the present invention;

FIG. 14 is another schematic diagram of the driving voltage provided by the driving circuit for different display partitions according to the embodiment of the invention;

FIG. 15 is a schematic diagram illustrating the variation of the driving voltage provided by the driving circuit for different display partitions with time according to an embodiment of the present invention;

fig. 16 is a top view of a display device according to an embodiment of the invention.

Detailed Description

The embodiments of the present invention will be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In recent years, Micro-LEDs have become a new display panel technology in the display market and are receiving attention because of their superior performance in technical dimensions, such as brightness, color, viewing angle, contrast, resolution, and lifetime.

The prior Micro-LED display panel needs to realize real mass production, and needs to overcome some technical difficulties, because the prior Micro-LED elements with different colors have certain differences in materials and processes, the differences exist in the aspects of materials such as semiconductor materials, multiple quantum well structures in a luminescent layer, doping degrees and the like, the differences exist in the aspects of processes such as different material growth temperatures, required gas environments, different electrode structures and the like, and the differences can influence the luminous efficiency among different Micro-LED elements, if the Micro-LED elements are selected one by one, huge workload can be caused, and the requirement of mass production can not be met. The skilled person finds that generally, the Micro-LED elements of the same color have the same growth material and the same manufacturing process, so that the relative difference between the Micro-LED elements of the same color is reduced, and therefore, on the display panel, if the Micro-LED elements of different colors are uniformly controlled, the display panel has the uniform brightness, and the light emitting powers of the Micro-LED elements of different colors are also uniform, so that the overall heating degree of the display panel is also uniform.

Referring to fig. 1, fig. 1 is a schematic top view of a display panel according to an embodiment of the present invention; the display panel 1 according to the embodiment of the present invention includes a plurality of pixel units 10, where each pixel unit 10 at least includes a first color sub-pixel 101, a second color sub-pixel 102, and a third color sub-pixel 103, and it should be noted that the present invention does not limit the number of light emitting elements included in the sub-pixels, and does not limit the connection manner of the light emitting elements in the sub-pixels, for example, the light emitting elements may be connected in series or in parallel. A plurality of driving circuit units 11, the driving circuit units 11 including at least a first driving circuit 111, a second driving circuit 112, and a third driving circuit 113.

Referring to fig. 2, fig. 2 is a schematic diagram of a driving circuit according to an embodiment of the present invention, optionally, as shown in fig. 2, the first driving circuit 111, the second driving circuit 112 and the third driving circuit 113 may be configured in the same structure, and optionally, transistors included in the driving circuit may be P-type transistors or N-type transistors; for convenience of description, the first driving circuit 111 is exemplified herein, and the first driving circuit 111 includes first to seventh thin film transistors T1 to T7, the first to seventh thin film transistors T1 to T7 are P-type transistors, a storage capacitor Cst, scan signal input terminals S1 and S2, a light emission signal control terminal Emit, a restart signal terminal Vref, a data signal terminal Vd1, and a driving voltage high level input terminal VDD1, and a driving voltage low level input terminal VEE 1.

Control terminals of the fifth thin film transistor T5 and the seventh thin film transistor T7 are electrically connected to the scan signal input terminal S1, first terminals of the fifth thin film transistor T5 and the seventh thin film transistor T7 are electrically connected to the restart signal terminal Vref, a second terminal of the fifth thin film transistor T5 is electrically connected to a control terminal of the third thin film transistor T3, and a second terminal of the seventh thin film transistor T7 is electrically connected to a second terminal of the sixth thin film transistor T6; control terminals of the second thin film transistor T2 and the fourth thin film transistor T4 are electrically connected to the scan signal input terminal S2, a first terminal of the second thin film transistor T2 is electrically connected to the data signal terminal Vd1, and a second terminal of the second thin film transistor T2 is electrically connected to a first terminal of the third thin film transistor T3; a first terminal of the fourth thin film transistor T4 is electrically connected to a second terminal of the third thin film transistor T3, a second terminal of the fourth thin film transistor T4 is electrically connected to one terminal of the storage capacitor Cst, and the other terminal of the storage capacitor Cst is electrically connected to the driving voltage high level input terminal VDD 1; control terminals of the first thin film transistor T1 and the sixth thin film transistor T6 are electrically connected to the light emission signal control terminal Emit, a first terminal of the first thin film transistor T1 is electrically connected to the driving voltage high level input terminal VDD1, a second terminal of the first thin film transistor T1 is electrically connected to a first terminal of the third thin film transistor T3, a first terminal of the sixth thin film transistor T6 is electrically connected to a second terminal of the third thin film transistor T3, a second terminal of the sixth thin film transistor T6 is electrically connected to an anode of the light emitting element L1, and a cathode of the light emitting element L1 is electrically connected to the driving voltage low level input terminal VEE 1. A second terminal of the fifth thin film transistor T5 is electrically connected to a second terminal of the fourth thin film transistor T4, and an electrically connected point of the second terminal of the fifth thin film transistor T5, the control terminal of the third thin film transistor T3 and the second terminal of the fourth thin film transistor T4 is an N1 node; the second terminals of the first thin film transistor T1 and the second thin film transistor T2 are electrically connected to the first terminal of the third thin film transistor T3 at the N2 node; a second terminal of the third tft T3 is electrically connected to the first terminal of the fourth tft T4 and to the first terminal of the sixth tft T6, and the electrical connection point is an N3 node; the electrical connection between the second terminal of the seventh tft T7 and the second terminal of the sixth tft T6 is an N4 node.

Referring to fig. 3, fig. 3 is a timing diagram of one of the driving circuits shown in fig. 2; taking the first driving circuit 111 as an example for explanation, the operation period of the first driving circuit 111 includes: a first phase D1, a second phase D2, and a light emitting phase D3, wherein in the first phase D1: when a low-level signal is input from the scan signal input terminal S1, the fifth thin film transistor T5 and the seventh thin film transistor T7 are turned on, and a low-level signal input from the restart signal terminal Vref passes through the fifth thin film transistor T5 and the seventh thin film transistor T7 and reaches the N1 node and the N4 node, respectively; the low signal at the node N1 turns on the third tft T3, and the low signal at the node N4 resets the light emitting element L1. In the second stage D2: when the scan signal input terminal S2 inputs a low level signal, the second thin film transistor T2 and the fourth thin film transistor T4 are turned on, the scan signal input terminal S1 inputs a high level signal, the fifth thin film transistor T5 and the seventh thin film transistor T7 are turned off, the high level signal input from the data signal terminal Vd1 reaches the N2 node through the second thin film transistor T2, at this time, because the third thin film transistor T3 is turned on, the high level signal input from the data signal terminal Vd1 reaches the N3 node through the third thin film transistor T3 and reaches the N1 node through the fourth thin film transistor T4, thereby compensating for the shift of the threshold voltage of the third thin film transistor T3, the active level signal input from the data signal terminal Vd1, for example, the positive frame is a high level signal, the negative frame is a low level signal, and for example, the active level signal input from the data signal terminal Vd1 passes through the second thin film transistor T2, the gate potential of the third thin film transistor T3 is charged to Vdata- | Vth | by writing from the first end of the third thin film transistor T3, where Vdata is a high-level signal voltage input from the data signal terminal Vd1, and Vth is a threshold voltage of the transistor T3. In the lighting phase D3: when a low-level signal is input to the emission signal control terminal Emit, the first thin film transistor T1 and the sixth thin film transistor T6 are turned on, a high-level signal is input to the scan signal input terminal S2, the second thin film transistor T2 and the fourth thin film transistor T4 are turned off, a high-level signal is input to the driving voltage high-level input terminal VDD1, a low-level signal is input to the driving voltage low-level input terminal VEE1, and the absolute values of the voltage values of the high-level and low-level signals are the same, the high-level signal input to the driving voltage high-level input terminal VDD1 reaches the N2 node through the first thin film transistor T1, reaches the N3 node through the third thin film transistor T3, and reaches the N4 node through the sixth thin film transistor T6, so that an emission driving voltage is provided to the light emitting element L1, and the emission driving voltage Vth 1 is (VDD- (Vdata- |) -VDD-ata), vdd is a high level signal voltage inputted from the driving voltage high level input terminal Vdd1, and Vdata is a high level signal voltage inputted from the data signal terminal Vd 1. As can be seen, the light emission driving voltage of the light emitting element L1 is independent of the threshold voltage Vth of the third thin film transistor T3, and the light emission driving voltage of the light emitting element L1 does not change with the shift of the threshold voltage Vth of the third thin film transistor T3. It should be noted that fig. 3 is only a timing diagram corresponding to the driving circuit, and does not show the actual length of the effective signal input time of each signal terminal and the actual length of the effective signal input interval time of each signal terminal, which can be adjusted according to the specific requirements of the driving timing of the display panel.

Referring to fig. 1 and fig. 2, the driving sequence is described by taking the first driving circuit 111 as an example, and the second driving circuit 112 and the third driving circuit 113 are also identical, so that in the display phase, the first driving circuit 111 provides the first driving voltage V1 for the first color sub-pixel 101, the second driving circuit 112 provides the second driving voltage V2 for the second color sub-pixel 102, and the third driving circuit 113 provides the third driving voltage V3 for the third color sub-pixel 103; the first driving voltage V1 includes a high level signal voltage inputted from the high level input terminal VDD1 of the driving voltage of the first driving circuit 111, which is set as the first positive side driving voltage VDD1, and a low level signal voltage inputted from the low level input terminal VEE1, which is set as the first negative side driving voltage VDD1 ', so that the absolute values of the first positive side driving voltage VDD1 and the first negative side driving voltage VDD 1' are equal; similarly, the second driving voltage V2 includes a high-level signal voltage inputted from the high-level driving voltage input terminal VDD2 of the second driving circuit 112, which is set as the second positive-side driving voltage VDD2, and a low-level signal voltage inputted from the low-level driving voltage VEE2, which is set as the second negative-side driving voltage VDD2 ', and the absolute values of the second positive-side driving voltage VDD2 and the second negative-side driving voltage VDD 2' are equal, and the third driving voltage V3 includes a high-level signal voltage inputted from the high-level driving voltage input terminal VDD3 of the third driving circuit 113, which is set as the third positive-side driving voltage VDD3, and the low-level signal voltage inputted from the low-level driving voltage VEE3, which is set as the third negative-side driving voltage VDD3 ', and the absolute values of the third negative-side driving voltage VDD3 and the third negative-side driving voltage VDD 3' are equal. For convenience of illustration, fig. 4-7 are shown as schematic diagrams of the positive terminal driving voltage VDD inputted from the driving voltage high level input terminal VDD.

When the first color sub-pixel 101 has lower luminous efficiency than the second color sub-pixel 102 and the third color sub-pixel 103, the duty ratio of the first driving voltage V1 may be set to be greater than the duty ratios of the second driving voltage V2 and the third driving voltage V3. Referring to fig. 4, fig. 4 is a schematic diagram illustrating a variation of driving voltages provided by different driving circuits shown in fig. 2 with driving time; the first positive terminal driving voltage Vdd1 includes a plurality of driving periods TV1, the second positive terminal driving voltage Vdd2 and the third positive terminal driving voltage Vdd3 includes a plurality of driving periods TV2, the driving periods TV1 and TV2 are identical in duration and are t0, and the voltage amplitudes of the first positive terminal driving voltage Vdd1, the second positive terminal driving voltage Vdd2 and the third positive terminal driving voltage Vdd3 are a; during a driving period time t0, the duty ratio of the first positive side driving voltage Vdd1 is greater than the duty ratios of the second positive side driving voltage Vdd2 and the third positive side driving voltage Vdd3, i.e., the ratio t1/t0 of the time t1 when the first positive side driving voltage Vdd1 is at a high level to the time t0 of a driving period TV1, and is greater than the ratio t2/t0 of the time t2 when the second positive side driving voltage Vdd2 and the third positive side driving voltage Vdd3 are at a high level to the time t0 of a driving period TV2, i.e., the time t1 when the first positive side driving voltage Vdd1 is at a high level is greater than the time t2 when the second positive side driving voltage Vdd2 and the third Vdd3 are at a high level. Optionally, the duty ratio of the first driving voltage V1 is set to be greater than the duty ratios of the second driving voltage V2 and the third driving voltage V3, the first color sub-pixel 101 is made to emit light for a longer period of time than the second color sub-pixel 102 and the third color sub-pixel 103, so that it is possible to compensate for the phenomenon that the first color sub-pixel 101 has low luminous efficiency due to materials, processes, etc., so that the light emitting brightness of the first color sub-pixel 101, the second color sub-pixel 102 and the third color sub-pixel 103 are substantially consistent, in one driving period, the three have equal luminous power and basically consistent heating degree, so that the display panel has more consistent brightness and heating degree, meanwhile, the whole power consumption of the display panel is reduced, and the driving method only needs to change the duty ratio of the driving voltage and does not need to change the manufacturing process and the driving circuit, so that the display panel can obtain better mass production.

Optionally, if there is a difference between the light emitting efficiencies of the second color sub-pixel 102 and the third color sub-pixel 103, for example, the light emitting efficiency of the first color sub-pixel 101 is smaller than that of the second color sub-pixel 102, and the light emitting efficiency of the second color sub-pixel 102 is smaller than that of the third color sub-pixel 103, the duty ratio of the first driving voltage V1 may be set to be larger than that of the second driving voltage V2, and the duty ratio of the second driving voltage V2 is larger than that of the third driving voltage V3, as shown in fig. 5, fig. 5 is another schematic diagram of the driving voltages provided by different driving circuits shown in fig. 2 along with the driving time; the first positive side drive voltage Vdd1 includes a plurality of drive periods TV1, the second positive side drive voltage Vdd2 includes a plurality of drive periods TV2, the third positive side drive voltage Vdd3 includes a plurality of drive periods TV3, the driving periods TV1, TV2 and TV3 have the same duration, which is t0, the voltage amplitudes of the first positive side driving voltage Vdd1, the second positive side driving voltage Vdd2 and the third positive side driving voltage Vdd3 are also the same, which is a, however, in a driving period time t0, the duty ratio of the first positive side driving voltage Vdd1 is greater than the duty ratio of the second positive side driving voltage Vdd2, the duty ratio of the second positive side driving voltage Vdd2 is greater than the duty ratio of the third positive side driving voltage Vdd3, that is, the time t1 when the first positive side driving voltage Vdd1 is at a high level is greater than the time t2 when the second positive side driving voltage Vdd2 is at a high level, and the time t2 when the second positive side driving voltage Vdd2 is at a high level is greater than the time t3 when the third positive side driving voltage Vdd3 is at a high level; according to the difference of the luminous efficiency among the first color sub-pixel 101, the second color sub-pixel 102 and the third color sub-pixel 103, the duty ratios of the first driving voltage V1, the second driving voltage V2 and the third driving voltage V3 are set to be different, so that the color sub-pixel with lower luminous efficiency can compensate the deficiency of the luminous efficiency among the sub-pixels with different colors caused by materials, processes and the like by increasing the time length of the driving voltage at a high level, the luminous brightness of the first color sub-pixel 101, the second color sub-pixel 102 and the third color sub-pixel 103 is basically consistent, the heating degree is basically consistent, the display panel has more consistent brightness and heating degree, and simultaneously, the whole power consumption of the display panel is reduced, and the driving method only needs to change the duty ratio of the driving voltage without changing the manufacturing process and the driving circuit, therefore, the display panel can obtain better mass production. It should be noted that, for specific duty ratio settings of different driving voltages, corresponding adjustments may be performed based on the average luminance values of the sub-pixels with different colors before the adjustments are not performed; the brightness range of the sub-pixels with different colors can be set correspondingly according to the preset duty ratio value corresponding to the brightness range, and the specific duty ratio setting mode is not limited in the present invention.

Optionally, in addition to adjusting based on duty ratios of driving voltages corresponding to subpixels of different colors, the amplitude of the driving voltage corresponding to the subpixels of different colors may also be adjusted, where the amplitude refers to a value of the driving voltage corresponding to the subpixels of different colors when displaying the same gray scale, as shown in fig. 6, and fig. 6 is another schematic diagram of the driving voltage provided by the different driving circuits shown in fig. 2 changing with driving time; the first positive side driving voltage Vdd1 includes a plurality of driving periods TV1, the second positive side driving voltage Vdd2 and the third positive side driving voltage Vdd3 includes a plurality of driving periods TV2, and the driving periods TV1 and TV2 are identical in duration and are t 0; within a driving period time t0, the duty ratio of the first positive side driving voltage Vdd1 is greater than the duty ratios of the second positive side driving voltage Vdd2 and the third positive side driving voltage Vdd3, that is, the ratio t1/t0 of the time t1 when the first positive side driving voltage Vdd1 is at a high level to the time t0 of a driving period TV1, is greater than the ratio t2/t0 of the time t2 when the second positive side driving voltage Vdd2 and the third positive side driving voltage Vdd3 are at a high level to the time t0 of a driving period TV2, the voltage amplitude of the first positive side driving voltage Vdd1 is a, and the voltage amplitudes of the second positive side driving voltage Vdd2 and the third positive side driving voltage Vdd3 are both B, a is greater than B; by setting the duty ratio and magnitude of the first driving voltage V1 to be greater than those of the second driving voltage V2 and the third driving voltage V3, the light emitting duration and the obtained voltage value of the first color sub-pixel 101 are both made larger than the second color sub-pixel 102 and the third color sub-pixel 103, so that it is possible to compensate for a phenomenon that the first color sub-pixel 101 has low luminous efficiency due to materials, processes, etc., so that the light emitting brightness of the first color sub-pixel 101, the second color sub-pixel 102 and the third color sub-pixel 103 are substantially consistent, the heat emitting degree is substantially consistent, thereby the display panel has more consistent brightness and heating degree, simultaneously, the whole power consumption of the display panel is reduced, in addition, the driving method only needs to change the duty ratio and the amplitude of the driving voltage, and does not need to change the manufacturing process and the driving circuit, so that the display panel can obtain better mass production. In addition, since the adjustment of the duty ratio of the driving voltage is difficult to realize a fine adjustment of the luminance of the sub-pixels, assuming that the luminance difference Δ L caused by the difference of the light emitting efficiency between the sub-pixels of different colors includes a numerical difference of more than ten digits and a numerical difference of one digit, a large-range adjustment effect can be achieved by using an adjustment mode of the duty ratio of the voltage corresponding to the sub-pixels of different colors, and if the luminance difference Δ L is reduced to a numerical difference of the remaining one digit through the adjustment of the duty ratio of the driving voltage, the numerical difference of the one digit of the luminance difference Δ L is further reduced through the adjustment of the amplitude of the driving voltage, so that the light emitting luminances of the sub-pixels 101 of the first color, the sub-pixels 102 of the second color and the sub-pixels 103 of the third color are substantially identical. It should be noted that, for the above illustration, the duty ratio and the amplitude of the driving voltage for adjusting the luminance range of the sub-pixel need to be comprehensively evaluated according to the architecture of the driving circuit and the overall driving scheme of the display panel, which is not limited in the present invention; it should be noted that, if there is a difference between the light emitting efficiencies of the second color sub-pixel 102 and the third color sub-pixel 103, the duty ratio and/or the amplitude of the second driving voltage V2 and the third driving voltage V3 may be set to be different, which is not limited in the present invention.

Optionally, in addition to the adjustment based on the duty ratios of the driving voltages corresponding to the sub-pixels with different colors, the driving frequency of the driving voltage corresponding to the sub-pixels with different colors may also be adjusted. As shown in fig. 7, fig. 7 is another schematic diagram of the driving voltage provided by the different driving circuits shown in fig. 2 varying with the driving time; the first positive side driving voltage Vdd1 includes a plurality of driving periods TV1, the second positive side driving voltage Vdd2 and the third driving voltage Vdd3 also include a plurality of driving periods TV2, and the voltage amplitudes of the first positive side driving voltage Vdd1, the second positive side driving voltage Vdd2 and the third positive side driving voltage Vdd3 are all a; for the first positive side driving voltage Vdd1, the time of one driving cycle is t01, for the second positive side driving voltage Vdd2 and the third positive side driving voltage Vdd3, the time of one driving cycle is t02, then t01 is less than t02, the driving cycle time t01 of the first positive side driving voltage Vdd1 is set less than the time t02 of the driving cycles of the second positive side driving voltage Vdd2 and the third positive side driving voltage Vdd3, that is, the driving frequency of the first positive side driving voltage Vdd1 is set greater than the second positive side driving voltage Vdd2 and the third positive side driving voltage Vdd 3; and in one driving cycle time t01, the duty ratio of the first positive side driving voltage Vdd1 is the ratio t1/t01 of the time t1 when the first positive side driving voltage Vdd1 is high level to the time period t01 of one driving cycle TV 1; during a driving period time t02, the duty ratio of the second positive side driving voltage Vdd2 and the third positive side driving voltage Vdd3 is t1/t02, which is the ratio of the time t2 that the second positive side driving voltage Vdd2 and the third positive side driving voltage Vdd3 are at high level to the time t02 of a driving period TV2, then t1/t01 is much larger than t2/t 02. By setting the duty ratio and frequency of the first driving voltage V1 to be greater than those of the second driving voltage V2 and the third driving voltage V3, the first color sub-pixel 101 is made to emit light for a longer period of time than the second color sub-pixel 102 and the third color sub-pixel 103, so that it is possible to compensate for a phenomenon that the first color sub-pixel 101 has low luminous efficiency due to materials, processes, etc., so that the light emitting brightness of the first color sub-pixel 101, the second color sub-pixel 102 and the third color sub-pixel 103 are substantially consistent, the heat emitting degree is substantially consistent, thereby the display panel has more consistent brightness and heating degree, simultaneously, the whole power consumption of the display panel is reduced, in addition, the driving method only needs to change the duty ratio and the frequency of the driving voltage, and does not need to change the manufacturing process and the driving circuit, so that the display panel can obtain better mass production. In addition, the duty ratio of the driving voltage and the adjustment mode of the frequency are combined, the mode of changing the duty ratio of the driving voltage is not singly adopted to adjust the brightness of the sub-pixels, so that the brightness adjustment mode of the sub-pixels is flexible and various, the brightness difference caused by the difference of the luminous efficiency among the sub-pixels with different colors can be well matched, the duty ratio adjustment amplitude of the driving voltage cannot be too large, and the influence on the signal stability of the display panel is avoided. It should be noted that, the three methods for adjusting the driving voltage may be combined in pairs or may be combined to make the brightness and the heat generation uniformity of the display panel better.

Optionally, the first color is red, the second color is green, and the third color is blue, or the second color is blue and the third color is green. Due to the limitation of growth material factors between the red micro light emitting diode and the blue and green micro light emitting diodes, the red micro light emitting diode is generally difficult to achieve the light extraction efficiency consistent with that of the blue and green micro light emitting diodes; a light emitting element such as a red micro light emitting diode generally grows a light emitting material on a GaAs substrate, but the GaAs energy gap is relatively small and has an absorption effect on light emitted from the light emitting material, thereby limiting the light extraction efficiency of the red micro light emitting diode. In addition, compared with the green light, the human eye has lower sensitivity to the red light, so in order to ensure the uniformity of the display brightness of the display panel, by adjusting the driving voltage corresponding to the red sub-pixel to a certain extent, as in the above method, compared with the green and blue sub-pixels, the duty ratio, or the duty ratio and the voltage amplitude, or the duty ratio and the driving frequency, or the three are adjusted and controlled at the same time, the perceived brightness difference among the red sub-pixel, the green sub-pixel and the blue sub-pixel can be improved, so that the display panel obtains uniform brightness, and the luminous power of the sub-pixels of different colors is more uniform, so that the whole display panel generates heat uniformly.

Optionally, the first driving voltage V1, the second driving voltage V2, and the third driving voltage V3 are all pulse width modulation signals, and the first driving voltage V1, the second driving voltage V2, and the third driving voltage V3 may be turned on at a second stage of the working period of the corresponding driving circuit, or may be turned on simultaneously with the input signal of the data signal terminal Vd1, so as to ensure the stability of the signal.

Optionally, referring to fig. 8, fig. 8 is a schematic top view of another display panel according to an embodiment of the present invention; the display panel 1 provided by the embodiment of the invention comprises a display area AA and a non-display area PA, wherein the display area AA comprises a plurality of n display subareas A which are arranged along a second direction Y, and n is a positive integer which is more than or equal to 1; the ith display partition Ai includes at least one pixel unit row PH, where i is greater than or equal to 1 and less than or equal to n, i is also a positive integer, the pixel unit row PH includes a plurality of pixel units 10 and a plurality of driving circuit units 11, where the plurality of driving circuit units 11 are in one-to-one correspondence with the plurality of pixel units 10, the driving circuit units 11 further include a plurality of driving circuits 110, the pixel units 10 include a plurality of sub-pixels 100, and the plurality of driving circuits 110 are in one-to-one correspondence with the plurality of sub-pixels 100 and are electrically connected thereto.

The display area AA further includes n light-emitting signal control buses E, and the n light-emitting signal control buses E correspond to the n display partitions a one to one, and if the ith light-emitting signal control bus Ei corresponds to the ith display partition Ai; the ith display subarea Ai comprises m luminous signal control sub-lines e, wherein m is a positive integer greater than or equal to 1, and along the second direction Y, if the jth luminous signal control sub-line of the ith display subarea Ai is eij, wherein j is greater than or equal to 1 and less than or equal to m, and j is also a positive integer; as shown in fig. 8, the display section a1 includes light emission signal control sub-lines e11, e12, etc., and the light emission signal control sub-line eij is electrically connected to the drive circuit 110 corresponding to the sub-pixel 100 in the corresponding pixel cell row PH, i.e., to the light emission signal control terminal Emit.

The display area AA further includes r scan lines SS, where r is 2nm, that is, each pixel unit row PH includes 2 scan lines SS, one of which is electrically connected to the driving circuit 110 corresponding to the sub-pixel 100 in the pixel unit row PH corresponding thereto, that is, connected to the scan signal input terminal S1, and the other of which is electrically connected to the driving circuit 110 corresponding to the sub-pixel 100 in the pixel unit row PH corresponding thereto, that is, connected to the scan signal input terminal S2.

The non-display area PA comprises a first shift register circuit 13 and a second shift register circuit 14, one end of each light-emitting signal control bus of the n light-emitting signal control buses E is electrically connected with the first shift register circuit 13, and the other end of each light-emitting signal control bus is electrically connected with a plurality of light-emitting signal control sub-lines E of the corresponding display subarea A; as shown in fig. 8, one end of the light-emission signal control bus line E1 corresponding to the first display section a1 is electrically connected to the first shift register circuit 13, and the other end is electrically connected to the light-emission signal control sub-lines E11, E12, and the like.

One end or both ends of each of the r scan lines SS are electrically connected to the second shift register circuit 14, and it should be noted that, in fig. 8, the second shift register circuit 14 includes a second shift register circuit 141 and a second shift register circuit 142, which are located at two sides of the display area AA along the first direction X, and are a scanning circuit for dual-side driving, alternatively, the second shift register circuit 14 may include only one shift register circuit, which is located at one side of the display area AA along the first direction X, and is a single-side driving circuit, optionally, the second shift register circuit 14 includes a second shift register circuit 141 and a second shift register circuit 142, the second shift register circuit 141 is electrically connected to the scan line SS of the odd-numbered row or the even-numbered row, and the second shift register circuit 142 is electrically connected to the scan line SS of the even-numbered row or the odd-numbered row, which is the scan circuit cross drive; the present invention is not limited thereto.

Referring to fig. 8 and 9, fig. 9 is a schematic diagram of a driving timing sequence of a display panel according to an embodiment of the present invention; in the second direction Y, the second shift register circuit 14 sequentially provides the effective scan signals s to the scan lines SS, i.e., r scan lines SS, connected to the respective pixel unit rows PH, and the first shift register circuit 13 sequentially provides the effective emitting signals E0 to the respective emitting signal control buses E. For any display subarea A, before the second shift register circuit 14 provides the effective scan signal s for the third scan line SS of the display subarea A, after the effective scan signal s on the second scan line SS is turned off, the first shift register circuit 13 provides the effective light-emitting signal E0 for the light-emitting signal control bus E corresponding to the display subarea A, until after the effective scan signals s on all the scan lines SS included in the display subarea A are turned off, the effective light-emitting signal E0 is turned off, when the effective light-emitting signal E0 is provided to the light-emitting signal control bus E corresponding to the display subarea A, the effective light-emitting signal E0 is provided to the sub-pixels 100 of each pixel cell row PH in turn through the light-emitting signal control sub-line E along with the effective scan signal s provided by the second shift register 14 to the pixel cell row PH of the display subarea A, so as to complete the driving of one period of the whole display panel; as will be exemplified below with reference to the display partition a1, for the display partition a1, before the second shift register circuit 14 provides the effective scan signal s3 to the scan line SS3 of the display partition a1 and after the effective scan signal s2 on the scan line SS2 is turned off, the first shift register circuit 13 provides the effective light signal E01 to the light-emitting signal control bus E1 corresponding to the display partition a1, and until the effective scan signal s2m on the last scan line SS2m corresponding to the display partition a1 is turned off, the effective light signal E01 is turned off; when the effective light emission signal E01 is supplied to the light emission signal control bus E1 corresponding to the display partition a1, as the second shift register 14 sequentially supplies the effective scanning signal s to the scanning lines SS corresponding to the pixel cell rows PH of the display partition a1, the effective light emission signal E01 is sequentially supplied to the sub-pixels 100 of the pixel cell rows PH through the light emission signal control sub-lines E11, E12, and the like, all the sub-pixels 100 in the display partition a1 are lit, and the second shift register 14 sequentially supplies the effective scanning signals s (2m +1) and s (2m +2) to the scanning lines SS (2m +1) and SS (2m +2) corresponding to the next pixel cell row PH, respectively, and then enters driving of the next display partition a 2; it should be noted that, for the time with the effective light emitting signal E0 on the different light emitting signal control buses E, there may be an overlapping time period or no overlapping time period, as shown in fig. 9, the time with the effective light emitting signal E01 on the light emitting signal control bus E1 and the time with the effective light emitting signal E02 on the light emitting signal control bus E2 do not overlap, and optionally, the time for which the effective light emitting signal E01 on the light emitting signal control bus E1 is turned off is prolonged until the effective light emitting signal E02 on the light emitting signal control bus E2 is provided for a certain time and then turned off, so that the time of the effective light emitting signal E01 on the light emitting signal control bus E1 and the time for which the effective light emitting signal E02 on the light emitting signal control bus E2 overlap; in addition, fig. 9 only illustrates a timing diagram of related signals on the scan line S and the light-emitting signal control bus E, and the driving timing of the remaining signals may be designed according to the requirements of the display panel, which is not limited in the present invention.

Through dividing into a plurality of display subareas A to the display panel, each display subarea A corresponds a luminous signal control bus E, luminous signal control sub-lines E corresponding to each pixel unit row PH in the display subareas A are all electrically connected to the luminous signal control bus E, and then are uniformly electrically connected to the first shift register circuit 13 through the luminous signal control bus E, so that the luminous signal control lines corresponding to each pixel unit row PH are prevented from being directly and electrically connected to the first shift register circuit 13, the winding of lines in a non-display area is intensive, the preparation of lines in the process is facilitated, the width of the non-display area is facilitated to be reduced, and the realization of a narrow frame is facilitated.

Optionally, as shown in fig. 10, fig. 10 is a schematic top view of another display panel according to an embodiment of the present invention; the display panel 1 further includes a driving chip 15, and the display area a far from the driving chip 15 points to a direction close to the display area a of the driving chip 15 along the second direction Y, as shown in fig. 10, the display area a1 points to a direction of the display area An, and a projection area of the pixel unit 10 in the display area a on the vertical display panel 1 gradually decreases, where the projection area refers to a light emitting area of the pixel unit 10. As in the display partition a1, the projection area of the pixel unit 10 on the vertical display panel 1 is G1, including the projection area G10 of each sub-pixel 100 in the pixel unit 10; in the display partition a2, the projection area of the pixel unit 10 on the vertical display panel 1 is G2, including the projection area G20 of each sub-pixel 100 in the pixel unit 10; by analogy, in the display sub-area Ai, the projection area of the pixel unit 10 on the vertical display panel 1 is Gi, including the projection area Gi0 of each sub-pixel 100 in the pixel unit 10; in the display sub-area An, the projection area of the pixel unit 10 on the vertical display panel 1 is Gn, including the projection area Gn0 of each sub-pixel 100 in the pixel unit 10; the values of the projected area G1 to the projected area Gn0 are from large to small. Data lines (not shown) on the display panel 1 extend along a second direction Y, the first direction X is arranged, scanning lines (not shown) extend along the first direction X, and the second direction Y is arranged, because signal lines electrically connecting the data lines and the driving chip 15 and signal lines electrically connecting the scanning lines and the driving chip 15 have certain impedance, a load on one end of the data lines far away from the driving chip 15 is larger than a load on one end of the data lines close to the driving chip 15, and similarly, a load on the scanning lines far away from one end of the driving chip 15 is larger than a load on the scanning lines close to one end of the driving chip 15, so that luminance of sub-pixels in the pixel units 10 far away from one end of the driving chip 15 is smaller than luminance of sub-pixels in the pixel units 10 close to one end of the driving chip 15; optionally, by setting the projection area G of the pixel unit 10 on the vertical display panel 1 in the display partition a far from the driving chip 15, compared with the projection area G of the pixel unit 10 on the vertical display panel 1 in the display partition a near to the driving chip 15, the projection area G is larger, so as to optimize the problem that the sub-pixel 100 far from the driving chip 15 generates heat greatly and the luminance of the pixel decreases due to the larger distance from the driving chip 15 and the larger load on the data line and the scanning line, thereby making the luminance of the display panel 1 more uniform, and generating heat more uniform, and simultaneously reducing the overall power consumption of the display panel 1.

Optionally, with reference to fig. 10, in the same display partition a, different pixel unit rows PH arranged along the second direction Y have a pixel unit row PH far away from the driving chip 15 and a pixel unit row PH close to the driving chip 15, and optionally, may be arranged in the same display partition a, where the pixel unit row PH far away from the driving chip 15 points to the direction of the pixel unit row PH close to the driving chip 15, and projection areas G of the pixel units 10 in the different pixel units PH on the vertical display panel 1 gradually decrease, so that the luminance of the display panel 1 is uniform, the heat generation is uniform, and the overall power consumption of the display panel 1 is further reduced; the pixel units 10 can also be arranged in the same display subarea a, and the projected areas of the pixel units 10 on the vertical display panel 1 are consistent, so that the arrangement is convenient for the process preparation of the display panel 1 and the driving arrangement in the display subarea a.

Optionally, as shown in fig. 11, fig. 11 is a schematic top view of another display panel according to an embodiment of the present invention; in the same display area a, in the direction perpendicular to the display panel 1, the projected area G101 of the first color sub-pixel 101 may be larger than the projected area G102 of the second color sub-pixel 102 and larger than the projected area G103 of the third color sub-pixel 103, where the projected area is the light emitting area of the sub-pixel. By setting the projection area G101 of the first color sub-pixel 101 to be larger than the projection area G102 of the second color sub-pixel 102 and simultaneously larger than the projection area G103 of the third color sub-pixel 103, the light-emitting area of the first color sub-pixel 101 is larger than the light-emitting areas of the second color sub-pixel 102 and the third color sub-pixel 103, so that the phenomenon of low light-emitting efficiency of the first color sub-pixel 101 due to materials, processes and the like can be compensated, the light-emitting luminances of the first color sub-pixel 101, the second color sub-pixel 102 and the third color sub-pixel 103 are basically consistent, the heat-emitting degrees are basically consistent, the display panel has more consistent luminance and uniform heat emission, and the overall power consumption of the display panel is reduced.

Optionally, referring to fig. 12 and fig. 13, fig. 12 is a schematic top view of another display panel according to an embodiment of the present invention, and fig. 13 is a schematic diagram of a variation of a driving voltage provided by a driving circuit of different display partitions with time according to an embodiment of the present invention; in the display phase, the driving voltage corresponding to the sub-pixel 100 in the display partition a1 is VA1, the driving voltage corresponding to the sub-pixel 100 in the display partition a2 is VA2, the driving voltage corresponding to the sub-pixel 100 in the display partition Ai is VAi, and so on, the driving voltage corresponding to the sub-pixel 100 in the display partition An is VAn; the duty ratio of the driving voltage VA1 to the driving voltage VAn is gradually decreased from the display partition a1 far from the driving chip 15 to the display partition An near to the driving chip 15; for convenience of illustration, fig. 13 is a schematic diagram showing the positive side driving voltage VP input by the high level driving voltage input terminal VDD corresponding to the sub-pixel 100, as shown in fig. 13, the positive side driving voltage VPA1 includes a plurality of driving periods TVA1, the positive side driving voltage VPA2 includes a plurality of driving periods TVA2, and so on, the positive side driving voltage VPAn includes a plurality of driving periods TVAn, the time lengths of the driving periods TVA1 to TVA2 are all d0, and the voltage amplitudes of the positive side driving voltage VPA1 to the positive side driving voltage VPAn are all a; however, the duty ratio of the positive side driving voltage VPA1 to the positive side driving voltage VPAn gradually decreases, i.e., the ratio d1/d0 of the time d1 when the positive side driving voltage VPA1 is at a high level to the time d0 of one driving period TVA1, and the ratio dn/d0 of the time dn when the positive side driving voltage VPAn is at a high level to the time d0 of one driving period TVAn gradually decreases, i.e., the time d1 when the positive side driving voltage VPA1 is at a high level to the time dn when the positive side driving voltage VPAn is at a high level. Optionally, the display partition a1 far away from the driving chip 15 is arranged to point to the display partition An close to the driving chip 15, and the duty ratio of the driving voltage VA1 to the driving voltage VAn is gradually reduced, so that the problems of large device heat generation and pixel brightness reduction caused by large load on the data line and the scanning line due to large distance from the driving chip 15 of the sub-pixel 100 far away from the driving chip 15 can be optimized, and thus the brightness of the display panel 1 can be more uniform, the heat generation is more uniform, and the overall power consumption of the display panel 1 is also reduced.

Optionally, the duty ratios of the driving voltages corresponding to the sub-pixels 100 in the same display partition a may be set to be the same, so that the driving voltages of the sub-pixels 100 in the display partition a are conveniently and uniformly regulated.

Optionally, referring to fig. 12 and fig. 14, fig. 14 is another schematic diagram of a variation of the driving voltage provided by the driving circuit of different display partitions with time according to the embodiment of the present invention; in the display phase, the amplitude of the driving voltage VA1 to the driving voltage VAn is gradually reduced from the display partition a1 far away from the driving chip 15 to the display partition An near to the driving chip 15; for convenience of illustration, fig. 14 is a schematic diagram showing the positive side driving voltage VP inputted from the high level driving voltage input terminal VDD corresponding to the sub-pixel 100, as shown in fig. 14, the positive side driving voltage VPA1 includes a plurality of driving periods TVA1, the positive side driving voltage VPA2 includes a plurality of driving periods TVA2, and so on, the positive side driving voltage VPAn includes a plurality of driving periods TVAn, and the durations of the driving periods TVA1 to TVA2 are all d 0; the duty cycles from the positive side driving voltage VPA1 to the positive side driving voltage VPAn are also the same, i.e., the time from the positive side driving voltage VPA1 to the positive side driving voltage VPAn being high (active signal) is d; the voltage amplitude of the positive side driving voltage VPA1 is AM1, the voltage amplitude of the positive side driving voltage VPA2 is AM2, and so on, and the voltage amplitude of the positive side driving voltage VPAn is AMn, and the voltage amplitudes AM1 to AMn are gradually reduced. Optionally, the display partition a1 far from the driving chip 15 is arranged to point to the display partition An close to the driving chip 15, and the amplitude of the driving voltage VA1 to the driving voltage VAn is gradually reduced, so that the problems of large device heat generation and pixel brightness reduction caused by large load on the data line and the scanning line due to large distance from the driving chip 15 of the sub-pixel 100 far from the driving chip 15 can be optimized, and thus the brightness of the display panel 1 can be more uniform, the heat generation is more uniform, and the overall power consumption of the display panel 1 is also reduced.

Alternatively, referring to fig. 12 and fig. 15, fig. 15 is another schematic diagram of a variation of the driving voltage provided by the driving circuit of different display partitions with time according to the embodiment of the present invention; in the display stage, the display partition a1 far away from the driving chip 15 points to the display partition An near the driving chip 15, the frequency from the driving voltage VA1 to the driving voltage VAn is gradually reduced, and in one driving period, the time when the driving voltages corresponding to the sub-pixels 100 of different display partitions a are valid signals is consistent; or, the frequencies of the driving voltages VA1 to VAn are gradually decreased, and the time when the driving voltages corresponding to the sub-pixels 100 of different display partitions a are valid signals is also gradually decreased in one driving period; for convenience of illustration, fig. 15 also shows the positive side driving voltage VP inputted from the high level driving voltage input terminal VDD corresponding to the sub-pixel 100, as shown in fig. 15, the voltage amplitudes of the positive side driving voltage VPA1 to the positive side driving voltage VPAn are all a; the positive side drive voltage VPA1 includes a plurality of drive periods TVA1, the positive side drive voltage VPA2 includes a plurality of drive periods TVA2, and so on, the positive side drive voltage VPAn includes a plurality of drive periods TVAn; for the display sub-areas a1 to An, in a driving period corresponding to each display sub-area a, the time when the positive terminal driving voltage VP is at the high level (active signal) is d; however, the time d01 of the driving period TVA1 to the time d0n of the driving period TVAn is gradually increased, that is, the frequency of the driving voltage VA1 to the driving voltage VAn is gradually decreased. Alternatively, the time for the positive side driving voltage VP to be at the high level (active signal) gradually decreases from the display partition a1 to the display partition An in one driving period corresponding to each display partition a. Optionally, the display partition a1 far from the driving chip 15 is arranged to point to the display partition An close to the driving chip 15, the frequency from the driving voltage VA1 to the driving voltage VAn is gradually reduced, and in one driving period, the driving voltages corresponding to the sub-pixels 100 of different display partitions a are valid for the same time; or, the frequencies of the driving voltages VA1 to the driving voltage VAn are gradually reduced, and in one driving period, the time that the driving voltages corresponding to the sub-pixels 100 of different display partitions a are effective signals is also gradually reduced, so that the time that the sub-pixels 100 far away from the driving chip 15 obtain effective driving voltages can be longer, and thus the problems of larger device heat generation and pixel brightness reduction caused by larger distance from the driving chip 15 and larger loads on the data lines and the scan lines of the sub-pixels 100 far away from the driving chip 15 can be optimized, so that the brightness of the display panel 1 can be more uniform, the heat generation is more uniform, and the overall power consumption of the display panel 1 is also reduced.

Optionally, the amplitudes and frequencies of the driving voltages corresponding to the sub-pixels 100 in the same display area a may be set to be the same, so that the driving voltages of the sub-pixels 100 in the display area a are conveniently and uniformly regulated.

The above method for regulating and controlling the driving voltage corresponding to the sub-pixel in the display area a far from the driving chip 15 and pointing to the display area a close to the driving chip 15 can be used independently or in combination, as long as the display panel 1 can uniformly generate heat, obtain uniform brightness, and have lower power consumption.

Referring to fig. 16, fig. 16 is a top view of a display device according to an embodiment of the invention; the embodiment of the present invention further provides a display device 2, where the display device 2 includes a display terminal product such as a smart phone, a flat panel display device, and a notebook display device, the display device 2 includes the display panel 1, and the beneficial effects generated by the display device 2 are also the beneficial effects described in the above embodiment, which are not described herein again.

The foregoing description shows and describes several preferred embodiments of the present application, but as aforementioned, it is to be understood that the application is not limited to the forms disclosed herein, but is not to be construed as excluding other embodiments and is capable of use in various other combinations, modifications, and environments and is capable of changes within the scope of the inventive concept as expressed herein, commensurate with the above teachings, or the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the application, which is to be protected by the claims appended hereto.

Claims

1. A display panel, comprising:

a plurality of pixel units including at least a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel;

a plurality of driving circuit units, wherein the driving circuit units at least comprise a first driving circuit, a second driving circuit and a third driving circuit, in a display stage, the first driving circuit provides a first driving voltage for the first color sub-pixel, the second driving circuit provides a second driving voltage for the second color sub-pixel, and the third driving circuit provides a third driving voltage for the third color sub-pixel;

the luminous efficiency of the first color sub-pixel is lower than that of the second color sub-pixel and that of the third color sub-pixel, and the duty ratio of the first driving voltage is larger than that of the second driving voltage and that of the third driving voltage.

2. The display panel according to claim 1,

and when the sub-pixels with different colors display the same gray scale, the amplitude of the first driving voltage is larger than the amplitudes of the second driving voltage and the third driving voltage.

3. The display panel according to claim 1,

the first driving voltage drives the first color sub-pixel at a first frequency, the second driving voltage drives the second color sub-pixel at a second frequency, and the third driving voltage drives the third color sub-pixel at a third frequency;

the first frequency is greater than the second frequency and the third frequency.

4. The display panel according to any one of claims 1 to 3,

the first color is red, the second color is green, and the third color is blue.

5. The display panel according to claim 1,

the first, second, and third driving voltages are pulse width modulation signals.

6. The display panel according to claim 1,

the display panel includes:

a plurality of display partitions arranged along a second direction, each of the display partitions includes at least one pixel unit row, the pixel unit row includes a plurality of the pixel units and a plurality of the driving circuit units, the plurality of the driving circuit units correspond to the plurality of the pixel units one by one, each of the driving circuit units includes a plurality of driving circuits, each of the pixel units includes a plurality of sub-pixels, and the plurality of the driving circuits correspond to the plurality of the sub-pixels one by one and are electrically connected;

a first shift register circuit;

each light-emitting signal control bus corresponds to the display subarea one by one, the display subareas comprise a plurality of light-emitting signal control sub-lines, and each light-emitting signal control sub-line is electrically connected with the driving circuit corresponding to the sub-pixel of each pixel unit row; one end of each light-emitting signal control bus is electrically connected with the first shift register circuit, and the other end of each light-emitting signal control bus is electrically connected with the plurality of light-emitting signal control sub-lines in the corresponding display subarea.

7. The display panel according to claim 6,

the display panel comprises a driving chip, and the projection area of the pixel units in the display subareas is gradually reduced along the second direction and is pointed to the direction of the display subareas close to the driving chip by the display subareas far away from the driving chip.

8. The display panel according to claim 7,

in the same display subarea, the projected areas of the pixel units on the display panel are consistent.

9. The display panel according to claim 7,

in the same display partition, in a direction perpendicular to the display panel, a projection area of the first color sub-pixel is larger than projection areas of the second color sub-pixel and the third color sub-pixel.

10. A display device comprising the display panel according to any one of claims 1 to 9.

11. A driving method of a display panel is characterized in that,

the display panel comprises a plurality of pixel units, wherein each pixel unit at least comprises a first color sub-pixel, a second color sub-pixel and a third color sub-pixel, and the luminous efficiency of the first color sub-pixel is lower than that of the second color sub-pixel and the third color sub-pixel;

the display panel comprises a plurality of driving circuit units, wherein the driving circuit units at least comprise a first driving circuit, a second driving circuit and a third driving circuit, in a display stage, the first driving circuit provides a first driving voltage for the first color sub-pixel, the second driving circuit provides a second driving voltage for the second color sub-pixel, and the third driving circuit provides a third driving voltage for the third color sub-pixel;

in the display phase, the duty ratio of the first driving voltage is greater than the duty ratios of the second driving voltage and the third driving voltage.

12. The driving method according to claim 11,

in the display stage, when the sub-pixels of different colors display the same gray scale, the amplitude of the first driving voltage is greater than the amplitudes of the second driving voltage and the third driving voltage.

13. The driving method according to claim 11,

in the display phase, the first driving voltage drives the first color sub-pixel at a first frequency, the second driving voltage drives the second color sub-pixel at a second frequency, and the third driving voltage drives the third color sub-pixel at a third frequency;

14. The driving method according to any one of claims 11 to 13,

the first color is red, the second color is green, and the third color is blue.

15. The driving method according to claim 11,

16. The driving method according to claim 11,

the display panel includes:

a first shift register circuit;

each light-emitting signal control bus corresponds to the display subarea one by one, the display subareas comprise a plurality of light-emitting signal control sub-lines, and each light-emitting signal control sub-line is electrically connected with the driving circuit corresponding to the sub-pixel of each pixel unit row; one end of each light-emitting signal control bus is electrically connected with the first shift register circuit, and the other end of each light-emitting signal control bus is electrically connected with the plurality of light-emitting signal control sub-lines in the corresponding display subarea;

in the display stage, the first shift register circuit sequentially provides effective light-emitting signals for the light-emitting signal control bus, and the light-emitting signal control bus provides the effective light-emitting signals for the sub-pixels of each pixel unit row through each light-emitting signal control sub-line.

17. The driving method according to claim 16,

the display panel further comprises a driving chip;

in the display stage, the display subarea far away from the driving chip points to the display subarea close to the driving chip, and the duty ratios of the driving voltages corresponding to the sub-pixels of different display subareas are gradually reduced.

18. The driving method according to claim 17,

and the duty ratios of the driving voltages corresponding to the sub-pixels of the same display partition are consistent.

19. The driving method according to claim 16,

in the display stage, the display subarea far away from the driving chip points to the display subarea close to the driving chip, and the amplitudes of the driving voltages corresponding to the sub-pixels of different display subareas are gradually reduced.

20. The driving method according to claim 16,

in the display stage, the display partition far away from the driving chip points to the display partition close to the driving chip, the frequency of the driving voltage corresponding to the sub-pixels of different display partitions is gradually reduced, and in one driving period, the time when the driving voltage corresponding to the sub-pixels of different display partitions is an effective signal is consistent;

or, the display partition far from the driving chip points to the display partition close to the driving chip, the frequency of the driving voltage corresponding to the sub-pixels of different display partitions is gradually reduced, and in one driving period, the time when the driving voltage corresponding to the sub-pixels of different display partitions is an effective signal is also gradually reduced.