CN113760473A

CN113760473A - Priority processing method, processor, processing chip, circuit board and electronic equipment

Info

Publication number: CN113760473A
Application number: CN202010495647.1A
Authority: CN
Inventors: 李刚
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2020-06-03
Filing date: 2020-06-03
Publication date: 2021-12-07

Abstract

The embodiment of the application provides a priority processing method, a processor, a processing chip, a circuit board and an electronic device, wherein the priority processing method comprises the following steps: acquiring the current quantity of request information to be sent in a request queue of the processor; setting the request information to be sent firstly in the request queue as target request information, and acquiring the waiting time and the emergency level of the target request information; and determining the target priority of the target request information according to the current number, the waiting time and the emergency level. The target priority of the target request information is dynamically adjusted according to the current quantity, the waiting time and the emergency level, so that the obtained target priority is more consistent with the current situation of the target request information, and the target request information can obtain more reasonable response according to the dynamically adjusted target priority.

Description

Priority processing method, processor, processing chip, circuit board and electronic equipment

Technical Field

The present disclosure relates to the field of electronic technologies, and in particular, to a priority processing method, a processor, a processing chip, a circuit board, and an electronic device.

Background

The processing chip comprises a plurality of processors, and the plurality of processors are all mounted on the system bus. When a processor needs to access memory through the system bus, a request message is sent to the system bus. The system bus arbitrates the request information of each processor according to the priority of the request information of each processor, and the higher the priority is, the more the request information can be satisfied preferentially. The priority of the request information of each processor is fixedly configured, and the priority of the request information of the processor cannot be well adjusted under different use scenes.

Disclosure of Invention

The embodiment of the application provides a priority processing method, a processor, a processing chip, a circuit board and electronic equipment, which can dynamically adjust the priority of request information according to the parameters of the processor.

In a first aspect, an embodiment of the present application provides a priority processing method applied to a processor, the method including:

acquiring the current quantity of request information to be sent in a request queue of the processor;

setting the request information to be sent firstly in the request queue as target request information, and acquiring the waiting time and the emergency level of the target request information; and

and determining the target priority of the target request information according to the current number, the waiting time and the emergency level.

In a second aspect, an embodiment of the present application further provides a processor configured to:

acquiring the current quantity of request information to be sent in a request queue of a processor;

setting request information of a first sending position in a request queue as target request information, and acquiring waiting time and emergency level of the target request information;

In a third aspect, an embodiment of the present application further provides a processing chip, which includes:

a system bus;

a memory connected to the system bus; and

a processor connected to the system bus, the processor being as described above;

the system bus acquires target request information and target priority of the processor, and when the system bus responds to the target request information according to the target priority, the processor stores data into a memory or reads data from the memory through the system bus.

In a fourth aspect, an embodiment of the present application further provides a processing chip, which includes:

a system bus;

a memory connected to the system bus;

the processor is connected with the system bus and sends the associated target request information and the target priority to the system bus; and

the system comprises a system bus, a preset processor and a control module, wherein the system bus is connected with the preset processor, and the preset processor sends associated preset request information and preset priority to the system bus;

when the priority level of the target priority level is higher than the preset priority level, the system bus responds to the target request information and enables the processor to store data into the memory or read data from the memory through the system bus;

and when the priority level of the preset priority level is higher than the target priority level, the system bus responds to the preset request information, and the preset processor stores data into the memory or reads data from the memory through the system bus.

In a fifth aspect, an embodiment of the present application further provides a circuit board, on which a processing chip is integrated, where the processing chip is as described above.

In a sixth aspect, an embodiment of the present application further provides an electronic device, which includes:

an image sensor for acquiring image data;

the processing chip is connected with the image sensor and is used for processing the image data acquired by the image sensor to obtain a processing result; and

and the application processing chip is connected with the processing chip and is used for acquiring the processing result of the processing chip and processing the image of the processing result.

In the embodiment of the application, the number of the request information to be sent in the request list in the processor at different time points is different, the waiting time of the target request information is also different at different time points, and the urgency level of the target request information is different due to the importance of the target request information, so that the target priority of the target request information can be dynamically adjusted according to the current number, the waiting time and the urgency level, the obtained target priority is more consistent with the current situation of the target request information, and the target request information can obtain more reasonable response according to the dynamically adjusted target priority.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below.

Fig. 1 is a first flowchart of a priority processing method according to an embodiment of the present application.

Fig. 2 is a second flowchart of a priority processing method according to an embodiment of the present application.

Fig. 3 is a schematic structural diagram of a digital signal processor according to an embodiment of the present application.

Fig. 4 is a schematic diagram of a first structure of a processing chip according to an embodiment of the present disclosure.

Fig. 5 is a schematic diagram of a second structure of a processing chip according to an embodiment of the present disclosure.

Fig. 6 is a schematic diagram of a third structure of a processing chip according to an embodiment of the present application.

Fig. 7 is a schematic structural diagram of a circuit board according to an embodiment of the present application.

Fig. 8 is a schematic structural diagram of a first electronic device according to an embodiment of the present application.

Fig. 9 is a schematic structural diagram of a second electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without inventive step, are within the scope of the present application.

The embodiment of the present application provides a priority processing method, and an execution subject of the priority processing method may be the processor provided in the embodiment of the present application, or a processing chip, a circuit board, or an electronic device in which the processor is integrated. The electronic device may be a portable device such as a cellular phone, a media player, a tablet computer, a Personal Digital Assistant (PDA), or other portable computing device, among others.

The following is a detailed description of the analysis.

Referring to fig. 1, fig. 1 is a first flowchart illustrating a priority processing method according to an embodiment of the present application, where the priority processing method includes the following steps:

101, obtaining the current quantity of request information to be sent in a request queue of a processor.

The processor may be one of the processors within the processing chip. The Processor may be one of a Central Processing Unit (CPU), a Digital Signal Processor (DSP), a Neural-Network Processing Unit (NPU), an Image Signal Processor (ISP), and the like.

The digital signal processor is provided with a request list, and the request list can be set according to needs, such as a First-in First-out (FIFO) request list, that is, request information enters the FIFO request list firstly and exits from the FIFO request list firstly.

The request list may store a plurality of request messages to be sent. It can be understood that the processor needs to frequently access the memory through the system bus, a request message is correspondingly generated before each access, and the processor can access the memory only after the request message is sent to the system bus and the system bus is required to respond to the request message. The system bus receives a plurality of request messages and then responds to the plurality of request messages in sequence according to the priority of the plurality of request messages. If the last request message sent to the system bus by the processor is not responded, other request messages of the processor are not sent to the system bus immediately and are stored in the request list.

The request list has a certain storage capacity, for example, the request list may store 6, 8 or other numbers of request information. All the request information to be sent is stored in the request list.

The processor accesses the memory through the system bus, which may be understood as the processor storing data to or reading data from the memory through the system bus.

And 102, setting the request information to be sent firstly in the request queue as target request information, and acquiring the waiting time and the emergency level of the target request information.

The plurality of request information in the request list are transmitted in a certain order. For example, the plurality of request messages are transmitted in a first-in first-out order. The plurality of request messages may be transmitted in other orders, such as in accordance with the priority level, in accordance with the urgency level, and so on.

And according to the sending sequence of the plurality of request information, determining the request information to be sent first in the request list, and setting the request information as target request information.

And acquiring the waiting time of the target request information. The waiting time is the time after the target request information enters the request list, and may also be the time after the target request information becomes the request information to be sent first.

When each request message is generated, the processor sets a corresponding emergency level according to the emergency state of the request message. For example, if the information currently processed by the processor is important, the urgency level of the requested information is set to a high urgency level. For another example, if the information currently being processed by the processor is not important, the urgency level of the requested information is set to a low urgency level. It is understood that the urgency level of the request message can be set to a plurality of levels as needed, such as 3 or 5 levels, and the number of urgency levels is not limited herein.

In the present embodiment, the order of the step corresponding to 102 and the step corresponding to 101 is not limited, and it is to be understood that the step corresponding to 102 may be performed after the step corresponding to 101 is performed, the step corresponding to 101 may be performed after the step corresponding to 102 is performed, or the steps corresponding to 101 and 102 may be performed simultaneously.

And 103, determining the target priority of the target request information according to the current number, the waiting time and the emergency level.

After the current quantity of the request information to be sent in the request queue, the waiting time and the emergency level of the target request information are obtained, the corresponding target priority can be obtained by dynamic calculation according to the current quantity, the waiting time and the emergency level. If a reference priority is preset, the reference priority has a corresponding number threshold of the request information to be sent, a waiting time threshold of the request information to be sent first and an emergency level threshold, and then the reference priority is dynamically adjusted according to the current number, the waiting time and the emergency level to obtain a target priority.

It should be noted that, the target priority of the target request information is obtained, the target request information and the corresponding target priority thereof are sent to the system bus, and the system bus determines the response sequence of the target request information according to the target priority, so that the target request information can obtain a reasonable response sequence according to the target priority matched with the target request information. If the priority level of the target priority level is high, the target request information can be responded by the system bus more quickly, so that the processor can access the memory timely, and the efficiency of the processor is improved. If the priority level of the target priority level is low, the target request information is responded slowly by the system bus, the request information with high priority levels of other processors cannot be influenced, and the cooperative work among a plurality of processors is facilitated.

The more the current number of the request information to be sent is, the more the unprocessed request information in the processor is, the more the processor has backlog of the request information, the processor is accessing a large amount of the memory, the processor needs to process the backlog of the request information as soon as possible, otherwise, the efficiency of the processor is affected, therefore, the priority of the current request information can be set to be higher, so as to process the request information more quickly. On the contrary, if the current number of the request information to be sent is smaller, it indicates that the request information that the processor needs to process is smaller, and the priority of the current request information may be set to a lower priority level.

The longer the waiting time of the target request information is, the longer the time of delaying the target request information of the processor is, the longer the operation time of the processor corresponding to the target request information is not realized, the processing efficiency of the processor is reduced, and the priority of the target request information can be set to a higher priority level so as to be processed more quickly. On the contrary, if the waiting time of the target request information is shorter, it indicates that the time length of the target request information of the processor is not long, and the priority of the current target request information may be set to a lower priority level.

The higher the urgency level of the target request information is, the more urgent the operation corresponding to the target request information is for the processor, the more priority processing is required, and the priority level of the target request information can be set to be higher so as to enable faster processing. On the contrary, if the urgency level of the target request message is lower, it indicates that the urgency level of the target request message of the processor is not high, and the priority level of the current target request message may be set to be lower.

Referring to fig. 2, fig. 2 is a second flowchart of the priority processing method provided in the embodiment of the present application, where the priority processing method may include the following steps:

201, obtaining the current quantity of the request information to be sent in the request queue of the processor.

Specifically, reference may be made to the steps corresponding to the foregoing step 101, which are not described herein again.

202, setting the request information to be sent first in the request queue as target request information, and obtaining the waiting time and the emergency level of the target request information.

Specifically, reference may be made to the steps corresponding to the above step 102, which is not described herein again.

203, obtaining a first priority and a second priority of the request information to be sent in the request queue, where the first priority is the maximum priority of the request information, and the second priority is the minimum priority of the request information.

The request information to be sent in the request list has a first priority and a second priority, the first priority is the maximum possible priority of the request information, and the second priority is the minimum possible priority of the request information.

In the present embodiment, the order of the step corresponding to 203, the step corresponding to 202, and the step corresponding to 201 is not limited, and it is also understood that the order of performing the step corresponding to 203, the step corresponding to 202, and the step corresponding to 201 may be selected as necessary.

And 204, determining the preset priority of the target request information according to the current quantity, the waiting time and the emergency level.

After the current quantity of the request information to be sent in the request queue, the waiting time and the emergency level of the target request information are obtained, the corresponding preset priority can be obtained by dynamically calculating according to the current quantity, the waiting time and the emergency level. For example, a reference priority is preset, the reference priority has a corresponding number threshold of the request information to be sent, a waiting duration threshold and an emergency level threshold of the request information to be sent first, and then the reference priority is dynamically adjusted according to the current number, the waiting duration and the emergency level to obtain the preset priority.

The preset priority may be obtained in other ways besides the above. Exemplarily, the current number is converted into a first coefficient, the waiting duration is converted into a second coefficient, and the urgency level is converted into a third coefficient; and determining the preset priority of the target request information according to the first coefficient, the second coefficient and the third coefficient.

A first mapping table or a first mapping proportional relationship between the number of request information to be sent in the request queue and the first coefficient may be preset. And after the current quantity is obtained, searching a first mapping table according to the current quantity to obtain a corresponding first coefficient, or multiplying the current quantity by the first mapping proportional relation to obtain the first coefficient. The second mapping table or the second mapping proportional relationship of the waiting duration and the second coefficient may also be preset, and after the waiting duration of the target request information is obtained, the second mapping table is searched according to the waiting duration to obtain the second coefficient, or the waiting duration and the second mapping proportional relationship are multiplied to obtain the second coefficient. The third mapping table or the third mapping proportional relation of the emergency level and the third coefficient may also be preset, and after the emergency level of the target request information is obtained, the third mapping table is searched for the third coefficient according to the emergency level, or the emergency level and the third mapping proportional relation are multiplied to obtain the third coefficient.

It should be noted that the first mapping table, the first mapping proportional relationship, the second mapping table, the second mapping proportional relationship, the third mapping table, and the third mapping proportional relationship may be obtained through big data calculation, or may be obtained through neural network training. It should be noted that different processors may use a common first mapping table, a first mapping proportional relationship, a second mapping table, a second mapping proportional relationship, a third mapping table, and a third mapping proportional relationship, or different processors may use a single first mapping table, a first mapping proportional relationship, a second mapping table, a second mapping proportional relationship, a third mapping table, and a third mapping proportional relationship.

The first coefficient, the second coefficient and the third coefficient can also be obtained in other manners.

In some embodiments, the first factor is obtained by dividing the current number by the maximum number of requests queued. For example, assuming that the request queue can store a total of N requests, and that m requests have been stored in the request queue, the first factor is m/N.

In some embodiments, a count corresponding to the waiting duration is obtained, and the count is divided by a preset count threshold to obtain a second coefficient. For example, the waiting duration is converted into a count n (e.g., the waiting duration is divided by a reference duration to obtain the count n), and the count n is divided by a preset count threshold T to obtain a second coefficient n/T, where T is a preconfigured value. For another example, when a request message is changed from a request message not sent first to a target request message sent first, the corresponding counter is started and starts to count, the value corresponding to the current count is represented by n, and the count n is divided by a preset count threshold T to obtain a second coefficient n/T, where T is a preset value. It is contemplated that the second coefficient may be greater than 1 when the target request message has not been responded to.

In some embodiments, the difference between the emergency level and the preset level threshold is converted into a first intermediate coefficient; and obtaining a second intermediate coefficient corresponding to the preset grade threshold, and adding the second intermediate coefficient and the first intermediate coefficient to obtain a third coefficient. For example, when the processor sends a request message, it sends out its corresponding emergency message (latency) or the request message carries the emergency message (latency). The processor configures a basic preset grade threshold value, and the preset grade threshold value corresponds to a second intermediate coefficient I (base). Converting the difference value between the emergency grade of the emergency information (latency) and the I (base) of the preset grade threshold value into a first intermediate coefficient I (dynamic), and adding the second intermediate coefficient I (base) I (dynamic) and the first intermediate coefficient I (dynamic) to obtain a third coefficient. For another example, when the processor sends the request message, it sends the corresponding emergency message (latency) at the same time, or the request message carries the emergency message (latency). The emergency information (latency) includes a first intermediate coefficient i (dynamic), the processor further configures a basic preset level threshold, the preset level threshold corresponds to a second intermediate coefficient i (base), and the third coefficient is the second intermediate coefficient i (base) plus the first intermediate coefficient i (dynamic).

In some embodiments, after the first coefficient, the second coefficient, and the third coefficient are obtained, the first coefficient, the second coefficient, and the third coefficient may be directly added to obtain the preset priority of the target request information.

In other embodiments, the first sub-priority may be obtained by multiplying the first coefficient by a first weight, the second sub-priority may be obtained by multiplying the second coefficient by a second weight, and the third sub-priority may be obtained by multiplying the third coefficient by a third weight. And then adding the first sub-priority, the second sub-priority and the third sub-priority to obtain a preset priority. The values of the first weight, the second weight, and the third weight may be dynamically adjusted as needed. For example, the first weight, the second weight, and the third weight may be 0.2, 0.4, and 0.4 or 0.2, 0.5, and 0.3, etc.

Under different use scenarios, different proportions of the first weight, the second weight and the third weight may be adopted. For example, when the processor processes the video image, if the video image is a 30-frame video image, the ratio of the first weight, the second weight, and the third weight may be 0.2, 0.4, and 0.4. If the video image is a 60-frame video image, the ratio of the first weight, the second weight, and the third weight may be 0.2, 0.5, and 0.3.

205, adjusting the preset priority according to the first priority and the second priority to obtain the target priority of the target request information.

After the preset priority is obtained, the preset priority can be adjusted according to the first priority and the second priority to obtain the target priority.

In some embodiments, adjusting the preset priority according to the first priority and the second priority, and obtaining the target priority of the target request information may include: acquiring a first difference value between a preset priority and a second priority; acquiring a second difference value between the first priority and the second priority; dividing the first difference value by the second difference value to obtain a proportional value; and multiplying the first difference value by a proportional value, and adding the second priority to obtain the target priority. The preset priority of the target request information can be adjusted through the first priority and the second priority, so that the obtained target priority is more accurate and better meets the actual requirement of the target request information.

For ease of understanding, the manner in which the target priority is obtained can be seen in the following equation:

normalize_ratio＝(Qos(raw)-Qos(min))/(Qos(max)–Qos(min))；

Qos＝Qos(min)+(Qos(raw)–Qos(min))*normalize_ratio。

wherein, the normal _ ratio is a proportional value, Qos (raw) is a preset priority, Qos (max) is a first priority, Qos (min) is a second priority, and Qos target priority.

It will be appreciated that other ways of calculating the target priority may be used. For example:

normalize_ratio＝(Qos(raw)-Qos(mean))/(Qos(max)–Qos(min))；

Qos＝Qos(mean)+(Qos(raw)–Qos(mean))*normalize_ratio。

wherein, the normal _ ratio is a proportional value, Qos (raw) is a preset priority, Qos (mean) is an average value of historical request information in a request list, Qos (max) is a first priority, Qos (min) is a second priority, and Qos target priority.

And 206, sending the target request information and the target priority to the system bus.

And after the target priority of the target request information is obtained, the target request information and the target priority are sent to the system bus together. The target priority may be set in the target request information, or may be sent to the system bus together or sequentially as the associated information of the target request information.

When the system bus responds to the target request message according to the target priority, the processor stores data into or reads data from the memory through the system bus 207.

And after receiving the target request information and the target priority, the system bus determines the response sequence of the target request information according to the target priority. It can be understood that the system bus is connected with other processors besides the processor for sending the target request information, and after receiving the plurality of request information sent by different processors, the system bus performs sorting according to the priorities of the plurality of request information to determine the response order of the plurality of request information. When the system bus responds to the target request message according to the target priority, the processor sending the target request message stores data into the memory or reads data from the memory through the system bus.

It should be noted that the bandwidth of the memory is limited, and one processor has a large bandwidth requirement, and the bandwidth requirement of other processors is crowded. Therefore, the target priority of the target request information of the processors needs to be reasonably set, so that the processors can be more reasonably matched with each other to work, the really urgent request information can be processed as soon as possible, the non-urgent request information can be processed later, and the overall working efficiency of the system bus and the processors is improved.

It should be noted that the accessing to the memory includes reading and writing request information, the same method may be used to obtain the target priorities corresponding to the read request information and the write request information, and different methods may be used to obtain the target priorities corresponding to the read request information and the write request information. For example, the first weight, the second weight, and the third weight of the target priority corresponding to the read request information and the write request information are acquired to set different parameters. For another example, the preset priority may be adjusted according to the first priority and the second priority, and another method may be adopted to obtain the target priority of the target request information.

For ease of understanding, the following description will take a Digital Signal Processor (DSP) as an example. Referring to fig. 3 in detail, fig. 3 is a schematic structural diagram of a digital signal processor according to an embodiment of the present disclosure. The DSP has a Core processing unit (Core Engine) inside, during the operation of the Core processing unit, read-write request information (Rd/wr request) to the system bus and the memory is generated, the request information is stored in a request queue (request _ fifo), and then the request information in the request _ fifo reaches the system bus and is arbitrated by Qos information (target priority).

The digital signal processor is internally provided with a Fifo _ mon _ entry module which generates a Fifo _ factor used for representing the degree of fullness of the request queue. Assuming that the request queue can store N requests in total, and m requests are already stored in the request queue, the Fifo _ factor is m/N. The request list in the figure has a depth of 6, where 4 read/write requests have been deposited.

The digital signal processor is internally provided with a fifo _ mon _ req module which generates an Aging _ factor used for representing the waiting time of the request information of the first position of the request list. The fifo mon req module monitors the request information of the first location in the request fifo. When the first location has not been updated, meaning that the request information of request _ fifo has not been sent onto the system bus, the counter inside the fifo _ mon _ req block starts to start. And the Aging _ factor is n/T, wherein n is the counting value of the counter, and T is preconfigured for the digital signal processor. It is expected that the aging _ factor will be greater than 1 when the request information in the request _ fifo has not been responded to.

The digital signal processor is internally provided with a base _ Latency _ config module which generates a Latency _ factor used for representing the emergency level of the request information of the first position of the request list. The base _ latency _ config module monitors the request information of the first location in the request _ fifo. The digital signal processor sends out read/write request information with latency information I (dynamic), the more urgent the request I is, and the digital signal processor can be configured with a basic latency information I (base). The final Latency _ factor ═ i (base) + i (dynamic).

The digital signal processor is internally provided with a Qos normalization module, and the Qos normalization module can obtain a preset priority Qos (raw) through a Qos (raw) ═ P0, Fifo _ factor + P1, Aging _ factor + P2, Latency _ factor. The first coefficient P0, the second coefficient P1, and the third coefficient P2 may be configured as needed, and the weights of the Fifo _ factor, the Aging _ factor, and the tension _ factor may be adjusted by configuring different values. This can be flexibly adjusted dynamically according to the usage scenario of the digital signal processor. For example, when the digital signal processor processes video data, if the video is 30 frames of video, the first coefficient P0, the second coefficient P1 and the third coefficient P2 are selected to be 0.2, 0.4 and 0.4. If the video is 60 frames, the first coefficient P0, the second coefficient P1 and the third coefficient P2 are selected to be 0.2, 0.5 and 0.3.

The target priority Qos can also be obtained by normalizing (normalization) the preset priority Qos (raw). Exemplarily, assuming that the maximum allowed Qos in the digital signal processor is Qos (max) and the minimum allowed Qos is Qos (min), a specific calculation method for obtaining the target priority Qos is as follows:

normalize_ratio＝(Qos(raw)-Qos(min))/(Qos(max)–Qos(min))；

Qos＝Qos(min)+(Qos(raw)–Qos(min))*normalize_ratio。

the corresponding Qos (raw) can be obtained by dynamic calculation of the Fifo _ factor, the Aging _ factor and the Latency _ factor, and then the Qos (raw) is normalized to obtain the best target priority Qos. The request information of the digital signal processor can be reasonably responded by the system bus, so that the digital signal processor can reasonably access the memory, and the reasonable access of the memory by other processors is not influenced. The processors connected with the system bus can be matched with each other more reasonably, so that real urgent request information is processed as soon as possible, non-urgent request information is processed later, and the overall working efficiency of the system bus and the processors is improved.

An embodiment of the present application further provides a processor, configured to: acquiring the current quantity of request information to be sent in a request queue of a processor; setting request information of a first sending position in a request queue as target request information, and acquiring waiting time and emergency level of the target request information; and determining the target priority of the target request information according to the current number, the waiting time and the emergency level.

In some embodiments, before determining the target priority of the target request message based on the current amount, the wait time, and the urgency level, the processor may further perform the following steps:

acquiring a first priority and a second priority of request information to be sent in a request queue, wherein the first priority is the maximum priority of the request information, and the second priority is the minimum priority of the request information;

determining the target priority of the target request information according to the current number, the waiting duration and the emergency level comprises:

determining the preset priority of the target request information according to the current quantity, the waiting time and the emergency level;

and adjusting the preset priority according to the first priority and the second priority to obtain the target priority of the target request information.

In some embodiments, in determining the preset priority of the target request information according to the current amount, the waiting time and the urgency level, the processor may further perform the following steps:

converting the current number into a first coefficient, converting the waiting time into a second coefficient, and converting the emergency level into a third coefficient;

and determining the preset priority of the target request information according to the first coefficient, the second coefficient and the third coefficient.

dividing the current number by the maximum accommodating number of the request queue to obtain a first coefficient;

acquiring a count corresponding to the waiting time length, and dividing the count by a preset count threshold value to obtain a second coefficient;

converting the difference value between the emergency grade and a preset grade threshold value into a first intermediate coefficient;

obtaining a second intermediate coefficient corresponding to the preset grade threshold, and adding the second intermediate coefficient and the first intermediate coefficient to obtain a third coefficient;

In some embodiments, in determining the preset priority of the target request information according to the first coefficient, the second coefficient and the third coefficient, the processor may further perform the following steps:

multiplying the first coefficient by the first weight to obtain a first sub-priority, multiplying the second coefficient by the second weight to obtain a second sub-priority, and multiplying the third coefficient by the third weight to obtain a third sub-priority;

and adding the first sub-priority, the second sub-priority and the third sub-priority to obtain a preset priority.

In some embodiments, in adjusting the preset priority according to the first priority and the second priority to obtain the target priority of the target request information, the processor may further perform the following steps:

acquiring a first difference value between a preset priority and a second priority;

acquiring a second difference value between the first priority and the second priority;

dividing the first difference value by the second difference value to obtain a proportional value;

and multiplying the first difference value by the proportional value and then adding the second priority to obtain the target priority.

In some embodiments, after determining the target priority of the target request message based on the current quantity, the wait time, and the urgency level, the processor may further perform the steps of:

sending the target request information and the target priority to a system bus;

when the system bus responds to the target request message according to the target priority, the processor stores data into the memory or reads data from the memory through the system bus.

Referring to fig. 4, fig. 4 is a schematic view illustrating a first structure of a processing chip according to an embodiment of the present application. The processing chip 200 includes a system bus 250, a memory 270, and a processor 282.

The memory 270 and the processor 282 are each coupled to the system bus 250. The processor 282 may be the processor in any of the above embodiments, and will not be described herein.

Referring to fig. 5, fig. 5 is a schematic diagram illustrating a second structure of a processing chip according to an embodiment of the present application. The processing chip 200 includes a system bus 250, a memory 270, a processor 282, and a default processor 284. The memory 270, processor 282, and pre-set processor 284 are all coupled to the system bus 250. The processor 282 may be the processor in any of the above embodiments, and will not be described herein. The processor 282 sends the associated target request information and target priority to the system bus 250. The preset processor 284 transmits preset request information and a preset priority to the system bus 250.

Wherein, when the priority level of the target priority is higher than the preset priority level, the system bus 250 responds to the target request message to enable the processor 282 to store data into the memory 270 or retrieve data from the memory 270 through the system bus 250.

When the priority level of the preset priority level is higher than the target priority level, the system bus 250 responds to the preset request message, so that the preset processor 284 stores data into the memory 270 or acquires data from the memory 270 through the system bus 250.

The system bus 250 reasonably arranges the response sequence according to the priority of the request information of different processors, so that the request information of the processors can be reasonably responded by the system bus, the processors can more reasonably cooperate with each other to process the really urgent request information as soon as possible, the non-urgent request information is processed later, and the overall working efficiency of the system bus and the processors is improved.

It will be appreciated that the default processor and the processor may be different processors of the processing chip.

The embodiment of the present application further provides a processing chip, specifically referring to fig. 6, and fig. 6 is a schematic diagram illustrating a third structure of the processing chip according to the embodiment of the present application. The Processing chip 200 may include an Image Signal Processing (ISP) 210, a Neural-Network Processing Unit (NPU) 220, a Digital Signal Processing (DSP) 230, and a Central Processing Unit (CPU) 240. It can be understood that at least one of the image signal processor 210, the neural network processor 220, the digital signal processor 230, and the master processor 240 may adopt the structure and/or method of the processor in the foregoing embodiments to set a corresponding target priority for the target request information sent to the system bus, which may specifically refer to the priority processing method or the processor in any of the foregoing embodiments, and will not be described herein again. It is also understood that the processor in the above embodiments may be any one of an image signal processor, a neural network processor, a digital signal processor, and a master processor. The preset processor in the above embodiment is another one of the image signal processor, the neural network processor, the digital signal processor, and the master processor.

The image signal processor 210 is configured to perform processing such as dead pixel removal, stats statistics, and linearization on image data, such as RAW data, acquired by the processing chip 200. The neural network processor 220 is configured to perform enhancement processing on the image data processed by the image signal processor 210, and may run an artificial intelligence training network to process an image algorithm, so as to improve image quality while improving efficiency of processing the image data. The digital signal processor 230 is mainly used to assist the image signal processor 210 and the neural network processor 220. However, the digital signal processor 230 may also process image data with a small amount of calculation. A Central Processing Unit (CPU) 240 may control operations of the Processing chip 200 system, such as interrupt response, peripheral parameter configuration, and the like.

The processing chip 200 may also include registers 260, memory 270, a system bus 250, a first interface 201, a second interface 202, and an interconnect bus interface 203.

The system bus 250 is electrically connected to the various components of the processing chip 200, such as the system bus 250 to the image signal processor 210, the neural network processor 220, the digital signal processor 230, the master processor 240, the registers 260, the memory 270, and the interconnect bus interface 203.

The registers 260 may be used for communication between any two of the image signal processor 210, the neural network processor 220, the digital signal processor 230, and the master processor 240. Specifically, the first processor sends communication information to register 260 via system bus 250, and the second processor obtains communication information stored in register 260 via system bus 250. The first processor, the second processor and the register 260 are all connected to the same system bus 250, the first processor and the second processor transmit communication information through the system bus 250 and the register 260, the system bus 250 with high transmission speed can be fully utilized to transmit the communication information, and the information transmission efficiency between the first processor and the second processor is improved. And the method can not conflict with information transmitted through the mailbox, reduce the problem of information transmission delay caused by information transmission blockage, and improve the stability of information transmission. The first processor and the second processor may be any two of the image signal processor 210, the neural network processor 220, the digital signal processor 230, and the master processor 240.

It should be noted that, in the related art, different processors in a processing chip communicate through a mailbox (mailbox). For example, a CPU and a DSP within the same processing chip communicate via mailbox. Specifically, when the CPU needs to send a message to the DSP, the CPU needs to write the message to be written into the mailbox first, and then the DSP receives an interrupt and then reads the message from the mailbox. It will be appreciated that the mailbox is used not only for communication between the CPU and the DSP, but also for communication between the CPU, the DSP and external chips. Due to the limited capacity of the Mailbox, such as 32bit or 64bit, the communication is easy to jam and delay. The system bus 250 with high transmission speed can be used for transmitting communication information, and the information transmission efficiency between the first processor and the second processor is improved. And the method can not conflict with information transmitted through the mailbox, reduce the problem of information transmission delay caused by information transmission blockage, and improve the stability of information transmission.

The register 260 is configured to generate an interrupt after receiving the communication information, and after the interrupt is generated, the second processor is configured to obtain the communication information stored in the register 260 according to the interrupt. The register 260 may preset a corresponding relationship between the communication information and the interrupt, that is, the register 260 generates the interrupt after receiving the communication information of the first processor, the second processor receives the interrupt to indicate that the first processor has information to transmit to the second processor, and at this time, the second processor obtains the communication information stored in the second processor from the register 260 through the system bus 250.

It will be appreciated that the interrupt of register 260 may correspond to the second processor, i.e., the interrupt may be received by the second processor immediately after the interrupt is generated by register 260.

Register 260 may generate a number of different interrupts, with different interrupts corresponding to different processors. It will also be appreciated that the first processor may communicate with a different processor via registers 260. Specifically, register 260 includes a plurality of interrupt flags, with different interrupt flags corresponding to different processors. The register 260 may be configured to determine an interrupt flag bit from a plurality of interrupt flag bits as a target flag bit according to the communication information, and generate a corresponding interrupt according to the target flag bit, where a processor corresponding to the target interrupt flag bit is a second processor, and the second processor is configured to respond to the interrupt and obtain the communication information stored in the register 260 through the system bus 250.

It should be noted that in the embodiment of the present application, communication between different processors, that is, communication between processors such as a CPU, a DSP, a GPU, and an ISP, may be implemented through multiple interrupt flag bits of the register 260.

It is understood that the plurality of different interrupts generated by register 260 may be generated by a plurality of interrupt flag bits in one register 260, or a plurality of different interrupts may be generated for a plurality of registers 260, that is, each register 260 generates one interrupt and is fixed to correspond to one processor, so that the plurality of different interrupts generated by the plurality of different registers 260 correspond to a plurality of different processors. The first processor stores the communication information to the different registers 260 to generate interrupts corresponding to the different processors to enable communication between the first processor and the plurality of different processors.

The memory 270 may store various data of the processing chip 200, such as image data, system data, and the like. The memory 270 may also be understood as the memory of the processing chip 200. The memory 270 may also cooperate with the registers 260 for communication between any two of the image signal processor 210, the neural network processor 220, the digital signal processor 230, and the master processor 240.

In some embodiments, the first processor may also calculate a data amount of the target data to be transmitted to the second processor; if the data size is not larger than the storage capacity of register 260, which indicates that the data size of the target data is small, and register 260 can hold the target data, the target data may be determined as communication information, that is, the target data is directly stored in register 260. The second processor is configured to obtain the communication information stored in the register 260 through the system bus 250, and it is also understood that the second processor obtains the target data stored in the register 260 through the system bus 250. The first processor and the second processor may complete the transfer of information quickly through the register 260.

For example, the storage capacity of the register 260 is 32 bits, the data size of the target data is less than 32 bits, and all the communication information determined by the target data can be stored in the register 260. In other embodiments, the storage capacity of register 260 may be other values, such as 16 bits, 64 bits, etc.

It is understood that the target data smaller than the storage capacity of the register 260 may be simple data, and may also be command data. Such as controlling the second processor to turn on a function.

If the data size of the target data to be transmitted to the second processor by the first processor is larger than the storage capacity of the register 260, which indicates that the data size of the target data is larger and the register 260 cannot store the target data with larger data size, the first processor may store the target data in the memory 270 in the processing chip 200 and store the target data in the storage address of the memory 270 to form the communication information. After the second processor obtains the communication information, the target data stored in the memory 270 may also be obtained through the system bus 250 according to the storage address in the communication information.

The first processor and the second processor can also transmit target data with a larger data volume through the register 260 and the memory 270, the first processor and the second processor transmit a storage address and generate an interrupt through the register 260, and the target data with a larger data volume is transmitted through the storage address and the memory 270 without being limited by the capacity of the register 260 and the mailbox.

It is understood that the first processor may store target data with different data size to different registers, so that the second processor can know whether the target data to be transmitted by the first processor is stored in the register or the memory after receiving the interrupt of the different register.

It should be noted that the second processor may determine whether the target data or the big data information is to be transmitted by using a type flag bit in the register 260, so as to determine whether to obtain the target data from the register 260 or the memory 270.

The first processor calculates the data volume of the target data to be transmitted to the second processor; if the data size is not larger than the storage capacity of register 260, which indicates that the data size of the target data is small, and register 260 can hold the target data, the target data is determined as communication information, that is, the target data is directly stored in register 260, and the type flag bit of register 260 is set to the first value. If the data size is larger than the storage capacity of the register 260, which indicates that the data size of the target data is large and the register 260 cannot store the target data with large data size, the target data is stored in the memory 270, the storage address of the memory 270 is stored with the target data to form communication information, and the type flag bit of the register 260 is set to the second value.

After the second processor receives the interrupt of register 260, the second processor may first obtain the value of the type flag bit of register 260. If the value of the type flag bit is the first value, the second processor is configured to retrieve the target data stored by register 260 via system bus 250. If the value of the type flag bit is the second value, the second processor is further configured to obtain the storage address stored in the register 260 through the system bus 250, and obtain the target data stored in the memory 270 according to the storage address.

For example, the storage capacity of the register is 32 bits, wherein bit0 is a type flag bit, which can be used to indicate the type to be transmitted. A bit0 of 0 indicates that target data with a small data volume needs to be transmitted, such as command data and the like, the memory does not need to be read and written in the communication, and the specific command data represented by bits 1 to bit31, such as commands similar to mailbox communication, are higher in efficiency. bit0 is 1, which indicates that the target data with larger data size needs to be transmitted, and needs to participate in the memory, bits 1 to bit31 can be the starting address of the memory and the size of the target data, and the data of the starting address of the memory stores the target data of the data format agreed by the first processor and the second processor.

The first processor and the second processor may also transmit target data with a smaller data amount through the register 260, and may also transmit target data with a larger data amount through the register 260 and the memory 270 in cooperation. The first processor and the second processor transmit the memory address and generate the interrupt through the register 260, and transmit the target data with a larger data volume through the memory address and the memory 270 without being limited by the capacity of the register 260 and the mailbox.

The first processor, the second processor, the register 260 and the memory 270 in the processing chip 200 are all connected to the same system bus 250, and the transmission speed between the processors is fast. The first processor and the second processor can also transmit target data with smaller data volume through the register 260, do not need the participation of the memory 270, have very high efficiency, are not influenced by the communication of the processing chip 200 with other chips through the mailbox, and have higher efficiency and stability. For example, the first processor of the processing chip 200 may also communicate with other chips through the mailbox. The first processor and the second processor can also cooperate with the register 260 and the memory 270 to transfer target data with a relatively large data volume, the transfer speed is high, the size of the target data stored in the memory 270 can be dynamically allocated, and the size of the target data stored in the memory 270 can be much larger than the data capacity of the mailbox.

The first Interface 201 and the second Interface 202 may be Mobile Industry Processor Interfaces (MIPI). The first interface 201 may receive image data such as RAW data, such as RAW data acquired from an image sensor, for example. The image data such as RAW data received by the first interface 201 may be original image data, that is, the image data received by the first interface 201 is unprocessed image data, and specifically, the original image data may be understood as image data unprocessed by the image processor. The first interface 201 may transmit image data such as raw image data to the image signal processor 210 after receiving the image data.

The second interface 202 may receive a result of the image signal processor 210 processing the image data, the second interface 202 may also receive a result of the neural network processor 220 processing the image data, and the second interface 202 may also receive a result of the digital signal processor 230 processing the image data. For example, the processing chip 200 may transmit the preview data to the second interface 202 when performing preview processing on the image data. The second interface 202 may be connected with an application processing chip to transmit image data such as preview data received by the second interface 202 to the application processing chip. For example, when an image preview is required, the data processed by the image preview may be transmitted to the application processing chip through the second interface 202.

A Peripheral Component Interconnect Express (PCIE) 250, which may also be referred to as a pci Express (peripheral component Interconnect) interface, an external device Interconnect bus interface, is an interface of a high-speed serial computer expansion bus standard. The interconnection bus interface 203 can receive the result of the image signal processor 210 processing the image data, the interconnection bus interface 203 can also receive the result of the neural network processor 220 processing the image data, and the interconnection bus interface 203 can also receive the result of the digital signal processor 230 processing the image data. For example, the processing chip 200 may transmit the photographing data to the interconnection bus interface 203 when the photographing process is performed on the image data. The interconnect bus interface 203 may be connected with an application processing chip to transmit image data such as photographing data received by the interconnect bus interface 203 to the application processing chip. For example, when it is necessary to take an image or a video, the data to be taken may be transmitted to the application processing chip through the interconnection bus interface 203.

The interconnection bus interface 203 can transmit image data in real time or off line, and can also transmit data such as configuration parameters, and the interconnection bus interface 203 has high efficiency of transmitting data. Based on this, the embodiment of the present application may allocate different data to the second interface 202 and the interconnect bus interface 203 for transmission. Such as data processing of taking a photograph or a taken image may be transmitted to the application processing chip through the interconnection bus interface 203, and data processing of a preview image may be transmitted to the application processing chip through the second interface 202.

The embodiments of the present application further provide a circuit board, on which a processing chip is integrated, where the processing chip may be the processing chip in any of the embodiments, and specific structures and functions of the processing chip may refer to the embodiments, which are not described herein again.

Other components, such as other chips such as an application processing chip and the like, can be integrated on the circuit board, and the application processing chip and the processing chip are communicated with each other, so that more functions are realized. For example, the application processing chip controls the processing chip to process the image, and the application processing chip obtains the processing result of the control chip to process the image, thereby reducing the operation amount of the application processing chip. Referring to fig. 7, fig. 7 is a schematic structural diagram of a circuit board according to an embodiment of the present disclosure. Circuit board 22A may include a processing chip 200 and an application processing chip 400.

The Application Processing chip 400 may include an Application Processor (AP) 410, an Image Signal Processing (ISP) 420, a memory 430, a system bus 440, a third interface 450, and an interconnection bus interface 460.

The third Interface 450 may be a Mobile Industry Processor Interface (MI PI). The third interface 450 may be connected to the second interface 202 using a signal line. The electrical connection of the second interface 202 and the third interface 450 may enable the transmission of the results processed by the processing chip 200 to the application processing chip 400 for further processing of the results processed by the processing chip 200 by the image signal processor 420 of the processing chip 400.

The Peripheral Component Interconnect Express (PCIE) 460 may also be referred to as a pci Express, peripheral component Interconnect interface, which is an interface of a high speed serial computer expansion bus standard. Interconnect bus interface 460 may be electrically connected to interconnect bus interface 203 with signal lines. The electrical connection of the interconnection bus interface 460 and the interconnection bus interface 203 can enable the transmission of the results processed by the processing chip 200 to the application processing chip 400 for further processing of the results processed by the processing chip 200 by the image signal processor 420 of the processing chip 400.

The memory 430 may store various data of the application processing chip 400, such as image data transmitted from the processing chip 200 to the application processing chip 400 through the interconnection bus interface 203 and the second interface 202. The memory 430 may also store an operating system of the application processing chip 400, and the memory 430 may also store intermediate data or results processed by the image signal processor 420. Memory 430 may also store computer programs such as instructions executed in application processor 410. Of course, the memory 430 may also store other data, which is not illustrated here.

Referring to fig. 8, fig. 8 is a schematic view illustrating a first structure of an electronic device according to an embodiment of the present application. The electronic device 20A may include the processing chip 200, the application processing chip 400, and the image sensor 600, wherein the processing chip 200 and the application processing chip 400 may be the processing chip and the application processing chip in any of the above embodiments, and are not described herein again.

The image sensor 600 may be a Complementary Metal-Oxide-Semiconductor (CMOS) image sensor, a Charge Coupled Device (CCD) image sensor, or the like. The image sensor 600 may be electrically connected with the processing chip 200, such as the image sensor 600 being electrically connected with the first interface 201 of the processing chip 200. The image sensor 600 may acquire RAW image data such as RAW image data and transmit the RAW image data to the processing chip 200 through the first interface 201 for processing by image processors inside the processing chip 200 such as the image signal processor 210 and the neural network processor 220.

The processing chip 200 is used for processing the image data acquired by the image sensor 600 to obtain a processing result.

The application processing chip 400 is connected to the processing chip 200, and the application processing chip 400 is configured to obtain a processing result of the processing chip 200 and perform image processing on the processing result. It can be understood that the processing chip 200 performs a preliminary image processing on the image data to obtain a processing result, and the application processing chip 400 performs a further image processing on the processing result of the image processing chip 200 to obtain final image information, and displays the image information to the user. The image information is displayed, for example, by a display screen of the electronic device.

The application processing chip 400 is a control center of the electronic device 20A, connects various parts of the whole electronic device 20A by using various interfaces and lines, and performs various functions and processes of the electronic device 20A by running or calling a computer program stored in the memory 430 and calling data stored in the memory 430, thereby performing overall monitoring of the electronic device 20A. Such as the application processor 410, controls the image sensor 400 of the electronic device 20A to acquire raw image data and controls the processing chip 200 to perform image quality enhancement processing on the raw image data acquired by the image sensor 400 to obtain a pre-processing result. Then, the application processor 410 controls the image signal processor 420 of the application processing chip 400 to further process the pre-processing result, and then displays the result processed by the image signal processor 420 through the display screen of the electronic device 20A.

The electronic device 20A may be a portable device such as a cellular phone, a media player, a tablet computer, a Personal Digital Assistant (PDA), or other portable computing device, among others.

In the following, an electronic device is taken as a mobile phone as an example, and the electronic device includes a housing and a circuit board. The circuit board is mounted on the housing, the circuit board may be the circuit board of any one of the above embodiments, and the specific structure and function of the circuit board may refer to the above embodiments, which are not described herein again.

An electronic device is further provided in the embodiment of the present application, referring to fig. 9 specifically, and fig. 9 is a second structural schematic diagram of the electronic device provided in the embodiment of the present application. The electronic device 20A includes a housing 292 and a circuit board 22A. The circuit board 22A is mounted on the housing 292, the circuit board 22A may be a circuit board according to any of the above embodiments, and the specific structure and function of the circuit board 22A may refer to the above embodiments, which are not described herein again.

The housing includes a rear cover and a bezel. The electronic device 20A also includes a midplane, a display 294, a battery 296, and a camera 298. A bezel is disposed around the midplane, wherein bezel 330 may form a middle frame of electronic device 300 with the midplane. The middle plate and the bezel 330 each form a receiving cavity on both sides of the middle plate, one of which receives the display device 294, and the other of which receives the battery 296 and other electronic components or functional modules of the electronic device 20A, such as the circuit board 22A.

The display screen 294 forms a display surface of the electronic device 20A for displaying information such as images, text, and the like. The display screen 294 may be a full-screen, i.e., substantially all of the front surface of the display screen 294 is a display area. It should be noted that a camera 294 and/or some other optical sensor, such as a proximity sensor, an infrared sensor, etc., may be disposed below the display screen 294. In other embodiments, the display screen 294 may be a shaped screen, and the display screen 294 may include a display area and a non-display area. Wherein the display area performs the display function of the display screen 294 for displaying information such as images, text, etc. The non-display area does not display information. A camera and/or other sensors, such as at least one of a proximity sensor, an infrared sensor, an acoustic sensor, etc., are disposed below the non-display area.

Embodiments of the present application also provide a storage medium storing a computer program, which when running on a computer, causes the computer to execute the priority processing method in any of the above embodiments, such as: acquiring the current quantity of request information to be sent in a request queue of a processor; setting request information to be sent firstly in a request queue as target request information, and acquiring the waiting time and the emergency level of the target request information; and determining the target priority of the target request information according to the current number, the waiting time and the emergency level.

In the embodiment of the present application, the storage medium may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like.

In the description of the present application, it is to be understood that terms such as "first", "second", and the like are used merely to distinguish one similar element from another, and are not to be construed as indicating or implying relative importance or implying any indication of the number of technical features indicated.

The priority processing method, the processor, the processing chip, the circuit board and the electronic device provided by the embodiment of the application are described in detail above. The principles and implementations of the present application are described herein using specific examples, which are presented only to aid in understanding the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. A priority processing method applied to a processor, the method comprising:

2. The priority processing method of claim 1, wherein before determining the target priority of the target request message according to the current number, the waiting duration, and the urgency level, further comprising:

acquiring a first priority and a second priority of request information to be sent in the request queue, wherein the first priority is the maximum priority of the request information, and the second priority is the minimum priority of the request information;

the determining the target priority of the target request information according to the current number, the waiting duration and the emergency level comprises:

determining a preset priority of the target request information according to the current quantity, the waiting time and the emergency level;

3. The priority processing method of claim 2, wherein the determining the predetermined priority of the target request information according to the current quantity, the waiting duration and the urgency level comprises:

converting the current number into a first coefficient, converting the waiting duration into a second coefficient, and converting the emergency level into a third coefficient;

4. The priority processing method of claim 2, wherein the determining the predetermined priority of the target request information according to the current quantity, the waiting duration and the urgency level comprises:

obtaining a count corresponding to the waiting time length, and dividing the count by a preset count threshold value to obtain a second coefficient;

converting the difference value between the emergency grade and the preset grade threshold value into a first intermediate coefficient;

5. The priority processing method according to claim 3 or 4, wherein the determining the preset priority of the target request information according to the first coefficient, the second coefficient, and the third coefficient comprises:

multiplying the first coefficient by a first weight to obtain a first sub-priority, multiplying the second coefficient by a second weight to obtain a second sub-priority, and multiplying the third coefficient by a third weight to obtain a third sub-priority;

6. The priority processing method of claim 2, wherein the adjusting the preset priority according to the first priority and the second priority to obtain the target priority of the target request information comprises:

acquiring a first difference value between the preset priority and the second priority;

7. The priority processing method according to claim 1, wherein after determining the target priority of the target request message according to the current number, the waiting duration, and the urgency level, the method further comprises:

sending the target request information and the target priority to a system bus;

when the system bus responds to the target request information according to the target priority, the processor stores data into a memory or reads data from the memory through the system bus.

8. A processor, configured to:

setting the request information of a first sending position in the request queue as target request information, and acquiring the waiting time and the emergency level of the target request information;

9. A processing chip, comprising:

a system bus;

a memory connected to the system bus; and

a processor coupled to the system bus, the processor according to claim 8;

the system bus acquires target request information and target priority of the processor, and when the system bus responds to the target request information according to the target priority, the processor stores data into the memory or acquires data from the memory through the system bus.

10. A processing chip, comprising:

a system bus;

a memory connected to the system bus;

a processor coupled to the system bus, the processor according to claim 8, the processor to send the associated target request information and target priority to the system bus; and

the system comprises a system bus, a preset processor and a control module, wherein the system bus is connected with the preset processor, and the preset processor sends preset request information and preset priority to the system bus;

when the priority level of the target priority level is higher than the preset priority level, the system bus responds to the target request information so that the processor stores data into the memory or acquires data from the memory through the system bus;

and when the priority level of the preset priority level is higher than the target priority level, the system bus responds to the preset request information so that the preset processor stores data into the memory or acquires data from the memory through the system bus.

11. A circuit board having integrated thereon a processing chip, the processing chip being as claimed in claim 9 or 10.

12. An electronic device, comprising:

an image sensor for acquiring image data;

a processing chip connected to the image sensor, the processing chip according to claim 8 or 9, the processing chip being configured to process the image data acquired by the image sensor to obtain a processing result; and