CN1137492C - Semiconductor integrated circuit device - Google Patents

Abstract

A memory macro (MM) is composed of the following functional modules: for example: a main amplifier module (13), memory body modules (11), a power supply circuit (14), etc., wherein each memory body in the memory body modules (11) works independently, the memory capacity of the memory macro (MM) can be changed from large to small simply by changing the number of the memory body modules (11), a control circuit (BKCONTH) in each of the memory body modules (11) in the memory macro (MM) is provided with an additional address comparing function (COMP), so the same page can be accessed in high speed without any control circuit out of the memory macro (MM). In addition, the present invention provides a module (17) with the functions of sequence control of memory access, and an identification information (ID) is generated when an address or data is input/output when memory access is carried out. Thus, by using ID for verifying the consistency between the data and the address and controlling the access order of the memory, the order of address input and the order of data output can be changed, and high-speed memory access can be realized.

Description

Semiconductor device

Technical field

The present invention relates to a kind of for example semiconductor device of high integration storer such as DRAM (dynamic RAM) device, particularly a kind of effective technology that is applicable to the quick access of high integration storer of comprising.

Background technology

In recent years, along with the progress of semiconductor fabrication, the Highgrade integration of LSI (large scale integrated circuit) device has become possibility.This also makes and mass storage and extensive logical circuit might be integrated on the semi-conductor chip together.With regard to this semi-conductor chip, be easy to increase the quantity of I/O data line, thereby improve the data traffic between storer and the extensive logical circuit.This also makes might reduce the power consumption that data I/O operates greatly, and the transmission data are than provide faster under the I/O situation that lead-in wire drives in the semi-conductor chip outside.Therefore, the advantage of this semi-conductor chip is expected be used more and more from now on.

A kind of semi-conductor chip that the cache memory of mass storage, extensive logical circuit and high-speed cruising is integrated is arranged, and this semi-conductor chip attempts to adopt cache memory to reduce mass storage and the operating rate between the logical circuit is poor on a large scale.For example, in " Toru Shimizu. etc.; " A Multimedia 32b RISC Microprocessorwith 16Mb DRAM "; 1966IEEE International Solid-State CircuitsConference, Digest of Technical Papers pp.216-217 (hereinafter as prior art example 1) ", such semi-conductor chip has been described.Be connected to each other by the wide internal bus of 128-bit according to 1, one 32-bit microprocessor of this prior art example, 2MB DRAM and 2KB cache memory.When transmitting the 128-bit data, operating in five cycles between microprocessor and DRAM finishes, and operating in the one-period between microprocessor and cache memory finishes.Therefore, when cache-hit, the data transfer cycle number can reduce to 1/5.

For example, the storer on the semi-conductor chip of being assembled in for adopting that prior art 1 realized all is absolutely necessary as various functions such as continuous read out function, caches function, accessing control functions.How the capacity of semi-conductor chip also must use according to semi-conductor chip changes.Yet mass storage and cache memory all adopt mimic channel respectively in the zone that high speed operation requires.Therefore, when the function and the capacity of storer will change (even very little variation), the design of storer itself must be done very big modification.

And under the situation of the semi-conductor chip that adopts prior art 1 to make, the TAT (transformation time) between decision-making of shortening technical plan and product are finished is very important.Therefore, for meeting this requirement, enhancement function, be easy to the change capacity and shorten these 3 requirements of TAT and must reach simultaneously.

In addition, when cache memory is used as high-speed memory access on such semi-conductor chip, the problem below having occurred.When cache-hit, high-speed memory access is secure.In case can not hit, then accessing main memory will be spent the long time, and this will make the work of CPU (center processing unit) be very limited.

In general, if in the single page or leaf of DRAM the access continuation address, DRAM can be by access at a good pace.If but access (page fault occurring) in different another page or leaf, because inevitably the precharge of destination address etc. is former thereby make access slack-off in this case.For addressing this problem the method that has proposed to adopt multiple alternate configuration, thereby avoided this DRAM page fault.This method is to propose in the former application of the application's several inventors (Japanese Patent No.08-301538 (filed on November 13,1996)).

Yet the method that proposes in the above-mentioned application in the past can not be avoided this page fault when ram access.

Summary of the invention

In this case, a target of the present invention will make design have various functions and the variable-displacement memory macro is more prone to exactly, is integrated in the extensive logical circuit that resembles microprocessor and the presentation manager.

Another target of the present invention is exactly that a kind of storer that can be easy to the such extensive logical circuit interface of microprocessor and presentation manager will be provided.

It is exactly that the storer that can reduce as losses such as page faults will be provided that the present invention also has another target.

According to an aspect of the present invention, provide a kind of semiconductor device that has storer on semiconductor chip, described storer comprises: a kind of memory cell array; A kind of sense amplifier piece that is connected to described memory cell array; A kind of line decoder that is connected to described memory cell array; A kind of column decoder that is connected to described sense amplifier piece; And a kind of controller that is used for controlling described memory cell array, described line decoder, described column decoder and described sense amplifier piece; Wherein said controller another address in the next memory cycle enters a back address of preserving in the memory cycle; Wherein said controller compares another address with the next memory cycle, the address in the memory cycle, when mate by described comparative result two addresses, make the data that are kept in the described sense amplifier piece output to the outside of described storer and reading of data from described memory array not, and wherein said controller also exports a signal, indicates the outside of described storer to prepare to read data or described storer is write data from described storer.

According to another aspect of the present invention, provide a kind of semiconductor device that has a plurality of storeies on semiconductor chip, described storer comprises: a kind of memory cell array; A kind of sense amplifier piece that is connected to described memory cell array; A kind of line decoder that is connected to described memory cell array; A kind of column decoder that is connected to described sense amplifier piece; And a kind of controller that is used for controlling described memory cell array, described line decoder, described column decoder and described sense amplifier piece; Wherein said controller another address in the next memory cycle enters the address of back in one memory cycle of preservation; Wherein said controller comprises a kind of comparer, and this comparer compares another address with the next memory cycle, the address in the memory cycle, and wherein said controller also comprises a kind of output circuit, one first signal of described output circuit output, this signal indicates the outside of described storer to prepare to read data or described storer is write data from described storer.

According to another aspect of the present invention, a kind of semiconductor device on semiconductor chip is provided, comprise: first kind of storer and second kind of storer, every kind all has a kind of memory cell array, a kind of sense amplifier piece that is connected to described memory cell array, a kind of line decoder that is connected to described memory cell array, a kind of column decoder that is connected to described sense amplifier piece, and a kind of controller that is used for controlling described memory cell array, described line decoder, described column decoder and described sense amplifier piece; And a kind of control module that is connected to described first and second storeies; No matter wherein said control module can be from described first and second kinds of memory read datas and the storage access order, wherein said controller unit is exported an identifying information corresponding to Input Address when certain Input Address enters, and exports described identifying information when reading an information according to Input Address.

According to another aspect of the present invention, a kind of semiconductor device on semiconductor chip is provided, comprise: first kind of storer and second kind of storer, every kind all has a kind of memory cell array, a kind of sense amplifier piece that is connected to described memory cell array, a kind of line decoder that is connected to described memory cell array, a kind of column decoder that is connected to described sense amplifier piece, and a kind of controller that is used for controlling described memory cell array, described line decoder, described column decoder and described sense amplifier piece; And a kind of control module that is connected to described first and second storeies; No matter wherein said control module can be from described first and second kinds of memory read datas and the storage access order, the address that wherein said controller will newly enter compares with the pairing address of information that is kept in the described sense amplifier piece by last storage access, and when the described comparative result of two addresses mates, then export the information of preserving in the described sense amplifier piece, and from described memory cell array, do not read information.

According to another aspect of the present invention, a kind of semiconductor device on semiconductor chip is provided, comprise: first kind of storer and second kind of storer, every kind all has a kind of memory cell array, a kind of sense amplifier piece that is connected to described memory cell array, a kind of line decoder that is connected to described memory cell array, a kind of column decoder that is connected to described sense amplifier piece, and a kind of controller that is used for controlling described memory cell array, described line decoder, described column decoder and described sense amplifier piece; A kind of control module that is connected to described first and second storeies; No matter wherein said control module can be from described first and second kinds of memory read datas and the storage access order; The common bit lines of the sense amplifier piece of a kind of sense amplifier piece that is connected to described first memory and described second memory; And a kind of first circuit that comprises amplifier, the signal from described sense amplifier in the described common bit lines is amplified, and a kind of circuit that passes the signal to described sense amplifier by described common bit lines.

According to another aspect of the present invention, provide a kind of semiconductor device that has a plurality of storeies on semiconductor chip, every kind of described a plurality of storeies comprise: a kind of memory cell array; A kind of sense amplifier piece that is connected to described memory cell array; A kind of line decoder that is connected to described memory cell array; A kind of column decoder that is connected to described sense amplifier piece; And a kind of controller that is used for controlling described memory cell array, described line decoder, described column decoder and described sense amplifier piece; Wherein said semiconductor device also comprises a kind of common bit lines and a kind of sense amplifier that is connected to described common bit lines that is connected to described a plurality of storeies; And wherein said controller enters X address and the Y address of back in the preservation memory cycle in the address of next memory cycle.

According to another aspect of the present invention, provide a kind of semiconductor device on semiconductor chip, comprising: first kind of storer and second kind of storer, every kind comprises a storage array; A kind of sense amplifier piece that is connected to described memory cell array; A kind of line decoder that is connected to described memory cell array; A kind of column decoder that is connected to described sense amplifier piece; And a kind of control circuit that is used for controlling described memory cell array, described line decoder, described column decoder and described sense amplifier piece; A kind of control module that is connected to described first and second storeies; And a kind of processor that is connected to described control module; When Input Address entered, wherein said control module was exported an identifying information according to Input Address to described processor.Wherein said processor is preserved and is sent the relevant described identifying information in address; Wherein said control module outputs to described processor with described identifying information with sense information according to the described address that enters; And wherein said processor is to detecting in company with identifying information and the match condition between the identifying information of this preservation that information receives together according to the address.

The present invention above-mentioned, other and further target and new features will be high-visible in the application's description and accompanying drawing.

Below some the representative clause of the present invention that discloses among the application is made brief description.

For constituting a memory macro (MM) that is assembled in the semiconductor device (chip), be equipped with a database (1).This database (1) comprises as memory bank module (10,11 and 12), main amplifier module (13), and power module (14), controller modules (15) etc. are some functional blocks like this.The formation of each functional block that is equipped with for database (1) will make when this functional block is close to other unit and places, its power lead and signal wire energy automatic butt.Like this, only model and the number by the change functional block constitutes mass storage and cache memory respectively, just might design easily to have various functions and variable-displacement memory macro.

Controller (BKCONTH) in the memory bank module (11) is furnished with address comparing function (COMP), constitutes memory macro (MM3) therefrom.This just might constitute a kind ofly need not provide any controller beyond itself and can high speed access storage grand in that storage is grand when to the single page access.

Storing grand (MM4) is used for the controller (17) of control store phantom piece by many banks of memory modules (11) and one and forms.The composition of controller module (17) will make it to come in correspondence with each other management address and data by giving the additional ID (identifier word) of each address and data.This just might change address input order and data output order, even can earlier export early stage preparation data when when page fault occurring the address being entered after the data of correspondence, makes storage access become faster.

Description of drawings

Fig. 1 is the grand structure of storage and stores grand how the composition.

Fig. 2 is the structure of DRAM memory bank module.

Fig. 3 is the structure of DRAM memory bank module controller.

Fig. 4 shows DRAM memory bank module work wave

Fig. 5 is the example that DRAM memory bank module is connected with SRAM memory bank intermodule.

Fig. 6 is the structure of cache memories store phantom piece.

Fig. 7 is a calcspar that is included in hitting in the cache memories store phantom piece/error judging circuit and control circuit.

Fig. 8 is illustrated in the work wave that operation judges is a cache memories store phantom piece when hitting.

The work wave of cache memories store phantom piece when Fig. 9 is illustrated in operation judges and is mistake.

Figure 10 is the calcspar of main amplifier module.

Figure 11 is the calcspar of power circuit module.

Figure 12 is the connection example between write data buffer module and the main amplifier module.

Figure 13 is the calcspar that adopts the storage grand (first stores grand example) of DRAM memory bank module.

Figure 14 is the calcspar of memory bank control circuit module.

Figure 15 shows the waveform of storing grand first example.

Figure 16 shows the example of storing grand first address assignment.

Figure 17 shows the work wave of the storage of adopting SRAM memory bank module grand (second grand example of storage).

Figure 18 is the calcspar of the storage of employing cache memories store phantom piece grand (the 3rd the grand example of storage).

Figure 19 is the calcspar of cache controller.

Figure 20 shows the grand work wave of storage in the 3rd example.

Figure 21 shows the grand address assignment example of storage in the 3rd example.

Figure 22 shows the grand execution time of storage in the 3rd example.

Figure 23 is storage grand (the 4th an example) calcspar of being furnished with band ID access time sequence controller.

Figure 24 is the calcspar of the access time sequence controller of band ID.

Figure 25 shows the grand work wave of storage in the 3rd example.

Figure 26 shows the work wave of the 3rd the grand example high speed buffer memory stores phantom piece of storage.

Figure 27 is the calcspar of band ID access time sequence controller in another example.

Figure 28 is the process flow diagram that sends address ID signal AID data stream when address signal ADDIN enters.

Figure 29 is the process flow diagram that sends data ID signal DID data stream when data are exported.

Figure 30 is the calcspar of form MM-TABLE.

Figure 31 is the calcspar of multicomputer system.

Figure 32 is the process flow diagram that sends address ID signal AID data stream when address signal ADDIN enters.

Figure 33 sends the process flow diagram of data ID signal DID data stream when being data output.

Figure 34 is the calcspar of form M-TABLE.

Figure 35 is the process flow diagram that adopts the address ID signal control processor.

Figure 36 is the process flow diagram that adopts the data ID signal control processor.

Figure 37 is the calcspar of form CPU-TABLE.

Embodiment

(store grand structure and how to constitute grand)

Fig. 1 represents that the present invention stores grand structure and how to form this storage grand.A center processing unit CPU (example of extensive logical circuit) and the grand MM of storage (example of mass storage) are integrated in semiconductor chip (being chip) and go up on the semiconductor device CHIP that forms.This semiconductor device CHIP adopts technology such as for example CMOS (complementary metal oxide semiconductor (CMOS)) technology manufacturing and employing resin moulding-die to carry out plastic encapsulation.According to similar this chip and size and the model integrated logical circuit of the grand MM of storage, it is very big to store needed capacity of grand MM and velocity variations, but the design of storing grand MM must be finished rapidly.

Be used for constituting the database 1 of storing grand MM the functional block (module) that realizes various functions is housed.In other words, integrated multiple functional block in database 1 comprises: the DRAM memory bank module 10 that adopts respectively DRAM (dynamic RAM) storage unit that is made of a transistor and electric capacity; Has the caches memory bank module 11 of hitting/makeing mistakes arbitration functions with DRAM memory bank module 10 formations; Adopt respectively the SRAM memory bank module 12 of SRAM (static RAM) storage unit that constitutes by four or six transistors; Be used in the main amplifier module 13 of memory bank (DRAM memory bank 10, caches memory bank 11, SRAM memory bank 12 etc.) with the grand MM external devices swapping data of storage; Be used for to forming the power circuit module 14 of each module for power supply of storing grand MM; Memory bank control module 15; Cache memory control module 16; The access sequence control module 17 of band ID; Write data buffer module 18, etc.

These functional blocks are placed side by side, and the data input/output line that makes required power lead and signal wire and these functional blocks is from being dynamically connected.

Because database 1 is by preparation as mentioned above, thereby the grand MM of storage that capacity and function change respectively can very fast formation.

In addition, neither need to revise any memory access requests device, also need not to redesign any interface circuit, because in the target storage is grand, prepared the interface circuit that is used between storer and the memory access requests device.Storing the storer that comprises in grand has, for example, and memory bank control module 15, director cache module 16, the access sequence control module 17 of band ID, write data buffer module 18 etc.

Therefore, for form this have predetermined function the grand MM of storage, only need from database 1, to select required functional block and these functional blocks of rational deployment.To simply introduce shown in Figure 1 each below and store grand MM1, MM2, MM3 and MM4.

(1) stores grand MM1

Store grand MM1 and comprise DRAM memory bank module 10, main amplifier module 13, power circuit module 14, memory bank control module 15 and the write data buffer module of choosing from database 1 respectively 18.These function block design become when their just automatic connectings on demand during placement side by side.So,, adopt the grand MM1 of storage of DRAM to be easy to form if these functional blocks are pressed layout as shown in Figure 1.

For example, the power lead of DRAM memory bank module 10, main amplifier module 13 and power circuit module 14 all is general to their functional block, thus when they during by predetermined reasonable placement shown in Figure 1, the power lead of these functional blocks can be dynamically connected certainly.

The I/O data line of these functional blocks is also respectively by being placed on the precalculated position so that the global bit line GBL (also being referred to as common bit lines or common data line) that connects is continuous.This line connects will retouch explanation below in more detail.

Be easier to increase or revise each functional block because the versatility of this cloth line position makes, also be easy to change the capacity of (for example) storer.In Fig. 1, are 256K positions if be used in the memory capacity of the DRAM memory bank module 10 of the grand MM1 of storage, the total volume of then storing grand MM10 is the 1M position.Therefore, the storage of 2M bit capacity is grand if desired, then stores grand can the be made up of 8 DRAM memory bank modules 10.If the grand memory capacity that only needs the 512K position of target storage then only needs with 2 DRAM memory bank modules 10.

Store grand MM1 and comprise three types the such mode of module (DRAM memory bank module 10, power circuit module 14 and main amplifier module 13), thereby the structure of the grand MM1 of this storage can diminish, thereby its memory capacity is easy to change.Such storage macrostructure will be suitable for the storer of high capacity, small size.

(2) store grand MM2

Store grand MM2 and comprise the DRAM memory bank module of choosing from database 1 respectively 10, SRAM memory bank module 12,

Main amplifier module 13, power circuit module 14, memory bank control module 15 and write data buffer module 18.

Because SRAM memory bank module 12 operating speeds are fast, just might adopt SRAM memory bank module 12 to form mass storage with speed buffering function.Since access is integrated in different address areas than SRAM is regional faster with the slow DRAM zone of access, then the SRAM zone constitutes the so-called cache memory function of zero access.If increase memory capacity, only need increase the number of DRAM memory bank module 10.In the time of will reducing chip area if reduce cache memory capacity, only need that 2 SRAM memory bank modules 12 are kept to 1 and get final product.Store grand MM2 and have this caches function, and be easy to change the caches capacity.

(3) store grand MM3

It is grand to store grand MM3 and be a kind of storage of being furnished with the caches function.Store grand MM3 and comprise caches memory bank module 11, main amplifier module 13, power circuit module 14, caches control module 16 and the write data buffer module of choosing from database 1 respectively 18.

Store grand MM3 and utilize caches control module 16 to control caches module 11, thereby realize the caches function.In other words, when data were positioned at same word line (same page), these data can quick access.

As DRAM memory bank module 10, caches phantom piece 11 is the memory bank modules that adopt the DRAM storage unit.So caches phantom piece 11 can be described as a kind of DRAM memory module of being furnished with and being stored in hitting in its memory bank/error judging circuit, and adopt sense amplifier module SA as cache memory.Because this also is stored in hitting in its memory bank/error judging circuit, and caches control module 16 sizes are reduced.Therefore, this caches is deposited phantom piece 11 to be particularly suitable for the be absolutely necessary low capacity storage of caches function grand.Compare with the grand MM2 of storage that comprises DRAM memory bank module 10 and SRAM memory bank module 12, this grand MM3 of storage with caches function can form on a littler chip area.So have the grand MM3 of the storage of this caches function be well suited for newly-designed computing circuit integrated, thereby avoided existing system with caches function integrated on chip.

(4) store grand MM4

The grand MM4 of this storage is furnished with the caches function, and comprises the caches memory bank module of choosing from database 1 respectively 11, main amplifier module 13, power circuit module 14, band ID access sequence control module 17 and write data buffer module 18.

The grand MM4 of this storage sends identifying information ID for each address that enters, so that this ID exports with corresponding data.By receiving ID, center processing unit CPU just knows the corresponding relation between receiver address and the data.This this processing procedure will be described in detail below.Store grand MM4 and change address input sequence and data output sequence, make the data output of handling earlier earlier.Even making, this processing when mistake (when do not find data on same line) appears hitting in speed buffering, also can transmit data effectively.

As above to storing grand MM1, MM2, MM3 and MM4 are described, are provided in the storage in the composition data storehouse 1 various functional blocks in grand by combination by predetermined application target, and the quantity that changes these functional blocks, it is grand just can to form the storage with various predetermined functions and predetermined volumes.Can also in database 1, be equipped with the various functional blocks except that above-mentioned functions.Describe in detail below and form some grand representational functional block of this storage.

" DRAM memory bank module "

Figure 2 shows that the calcspar of this DRAM memory bank module 10.DRAM memory bank module 10 comprises memory cell array CA, sense amplifier piece SA, Y code translator YD, X code translator AD, controller BKCONT, electric source line interface PL, word line WD and global bit line GBL.

Memory cell array CA comprises many word line WD, multiple bit lines to and a plurality of dynamic storage cells (DRAM storage unit) of being positioned at each right point of crossing of these word lines and bit line.Each storage unit comprises a transistor and an electric capacity.Each bit line is to all being connected on the sense amplifier module SA.

Although in Fig. 2, do not show, sense amplifier module SA comprises that one is used for the voltage that each bit line is right and reduces to the pre-charge circuit of half supply voltage, a compensating circuit that is used for compensating the bit line pairs current potential, and be used for amplifying respectively the sense amplifier of bit line to current potential.

Although show in Fig. 2, the Y code translator comprises the decoding scheme that is used for selecting the row switch (Y switch) of sense amplifier piece SA output and produces control row switch selection signal.Decoding scheme receives a part (Y address) address signal ADD.

X code translator AD receives a part (X address) address signal ADD, through being used for selecting word line WD after the decoding.

Fig. 3 is the calcspar of controller BKCONT.Controller BKCONT comprises timing generator circuit TIM, X-to control circuit XCONT and Y-to control circuit YCONT.Control signal CBANK comprises clock signal clk, bank selection signal BS, and read/write is selected signal RW, regeneration request signal REF or the like.Timing sequence generating circuit TIM receive clock signal CLK, bank selection signal BS, read/write are selected signal RW or the like, produce thus X-to control circuit XCONT and Y-to the required clock signal of control circuit YCONT.Timing sequence generating circuit TIM also produces ready signal RDY, is used for notifying each external devices: data are just being prepared read/write or the regeneration period finishes.X-is to making it to produce respectively required control signal XSIG and the YSIG of DRAM memory bank module 10 internal operations with Y-to the formation of control circuit XCONT and YCONT.

At least, arrange some power lead that links to each other with electric source line interface and global bit line GBL to make it by memory cell array CA.

Fig. 4 is used for reading the sequential chart that is stored in the data the predetermined storage unit from DRAM memory bank module 10.With address signal ADD and control signal CBANK decoding, the address that enters from the outside by address wire ADD is by the X decoder for decoding, when data are then chosen a word line WD (being set to " height " level) when target storage volume is read.For the DRAM storage unit in the memory cell array CA, its signal is read from the storage unit that word line WD selectes, and amplifies and maintenance by the predetermined sense amplifier of choosing in sense amplifier module SA then.In addition, ready signal RDY is changed to " height " level.For the data read of the sense amplifier of choosing in sense amplifier module SA, the data of being selected by Y code translator YD output to the outside from DRAM memory bank module 10 by global bit line GBL.

Writing also of data carried out in the same way.The signal that device outside memory bank enters is sent to sense amplifier module SA through global bit line GBL, and the word line WD corresponding to Input Address is driven then, makes data write Destination Storage Unit.

For selected in sense amplifier module SA and from by the sense amplifier that keeps data read the storage unit of selecting bit line WD to activate, data write storage unit also as shown in Figure 4 read operation is carried out like that.The write data that obtains by global bit line GBL is sent to the predetermined sense amplifier of being chosen by the Y code translator subsequently, therefrom data is write corresponding storage unit.

Controller BKCONT controls this a series of aforesaid operations according to the signal that receives by control signal wire CBANK.

Global bit line GBL for the I/O data is arranged in the precalculated position, makes it to link to each other automatically with another main amplifier module 13 with another DRAM memory bank module 10 that is close to.

Electric source line interface PL is arranged in a precalculated position, so that provide external power source to predetermining circuit in the memory bank and with other functional modules of its next-door neighbour.Because global bit line GBL and electric source line interface PL layout by this way are shared for all functions module, when they just in time are close to when placing, but just automatic connecting of functional module.This makes and constitutes the grand possibility that becomes of storage rapidly.

Especially, since the DRAM storage unit is used for DRAM memory bank module 10, thereby the feasible chip area that might reduce mass storage of the standardized arrangement of this functional module.Particularly when computing circuit and memory circuit are integrated on the chip, the DRAM memory bank module 10 of the DRAM storage unit that the integrated characteristic of this use is splendid will be only, because in this case, it is inevitable increasing chip area.

" SRAM memory bank module "

SRAM memory bank module 12 can constitute by DRAM memory bank module 10 same methods.Yet under the situation of this SRAM memory bank module 12, the SRAM storage unit is as memory cell array CA.A SRAM storage unit comprises four or six transistors.Because each storage unit all can be self-driven, so the sense amplifier among the sense amplifier piece SA all can omit.In addition because the varying in size of each storage unit between DRAM memory bank module 10 and the SRAM memory bank module 12, be difficult to memory bank module 10 and 12 both layouts between public global bit line GBL by aligned.Yet if with SRAM storage unit SMC alinement between public global bit line GBL, this problem just can be avoided.Fig. 5 provides the example that connects like this between DRAM memory bank module 10 and the SRAM memory bank module 12.

In DRAM memory bank module 10 shown in Figure 5, only showed memory cell array CA, sense amplifier module SA and Y switch YSW.Memory cell array CA comprises many word line WL, and many pairs of bit line are to DL and DLB, and lays respectively at the DRAM storage unit DMC on each right point of crossing of these word lines and bit line.For each pairs of bit line provides a sense amplifier module SA to DL and DLB.For per four pairs of bit line to a pair of global bit line of the corresponding placement of DL with DLB to GBL and GBLB.In other words, Y switch YSW makes it might be optionally four pairs of bit line to be linked to each other with GBLB to GBL with a pair of and a pair of global bit line among the DLB to DL.Control the signal of this Y switch YSW exports from Y code translator YD from four signal wires.

In SRAM memory bank module 12 shown in Figure 5, only showed memory cell array CA, sense amplifier module SA and Y switch YSW.Memory cell array CA comprises many word line WL, many pairs of bit line DL and DLB and lay respectively at these word lines and the SRAM storage unit SMC of each point of crossing that bit line is right.For each bit line provides a sense amplifier module SSA to DL and DLB.These sense amplifier pieces SSA is omissible.Be two pairs of bit line to a pair of global bit line of the corresponding placement of DL with DLB to GBL and GBLB.In other words, Y switch YSW makes it might be optionally two pairs of bit line to be linked to each other with GBLB to GBL with a pair of and a pair of global bit line among the DLB to DL.Control the signal of such Y switch YSW exports from Y code translator YD from two signal line.

As shown in Figure 5, the bit line that with global bit line GBL is linked to each other with GBLB in SRAM memory bank module 12 is less than number in the DRAM memory bank module 10 to the number of DL and DLB.So adjusting module 10 and this number difference of 12 make and adopt the SRAM memory bank module 12 of big storage unit to link to each other with GBLB to GBL with global bit line with identical spacing with DRAM memory bank module 10.

Although memory bank module 10 is identical with 12 both memory capacity, the required chip area of SRAM memory bank module 12 is bigger than DRAM memory bank module 10.Yet the travelling speed of SRAM memory bank module 12 is faster than DRAM module 10.If the capacity of SRAM memory bank module 12 reduces (for example, its capacity reduces to 1/4), it is almost identical with DRAM memory bank module 10 that required chip area becomes.So when being used for constituting storage when grand, if think that the grand travelling speed of target storage is most important, perhaps if with storing the grand cache memory of doing, it will be more obvious then adopting the effect of SRAM memory bank module 12.

" caches memory bank module "

Figure 6 shows that the calcspar of this caches phantom piece 11.This caches phantom piece 11 comprises memory cell array CA, sense amplifier module SA, Y code translator YD, X code translator AD, controller BKCONT, electric source line interface PL, word line WL, global bit line GBL and hitting/error judging circuit HM.Except hit/error judging circuit HM and controller BKCONT, every structure of caches phantom piece 11 is identical with DRAM memory bank module 10.

The calcspar of shown in Figure 7 hitting/error judging circuit HM and controller BKCONT.Hit/error judging circuit HM comprises the register REG that is used for preserving final access address and the address that is used for newly entering and be kept at the comparator C OMP that the address among the register REG compares.Controller BKCONT comprises timing sequence generating circuit TIME, X-to control circuit XCONT and Y-to control circuit YCONT.Control signal CBANKH comprises clock signal clk, bank selection signal BS, and read/write is selected signal RW, regeneration request signal REFS, regeneration look-at-me REFE, busy signal BSY etc.Timing sequence generating circuit TIME receive clock signal CLK, bank selection signal BS, read/write are selected signal RW, regeneration request signal REFS, busy signal BSY etc., thus produce X-to Y-to control circuit XCONT and the required clock signal of YCONT.Timing sequence generating circuit TIME also produces ready signal RDY and notifies external devices-data to prepare read/write or regeneration period end.X-to Y-to control circuit XCONT and YCONT constitute respectively so that produce required control signal XSIG and the YSIG of caches memory bank module 11 internal operations.

Illustrate below to hit/error judging circuit HM and controller BKCONTH.Bank selection signal BS is input into timing sequence generating circuit TIME, and this timing sequence generating circuit TIME judges whether target storage volume is selected, and according to judged result control signal HMAC is arranged on predetermined state.If judge that memory bank is selected, just control signal HMAC activates comparator C OMP.One address AD D is input into comparator C OMP and register REG.Register REG then outputs to the last access address that itself is preserved among the comparator C OMP.If it is selected to judge that memory bank does not have, control signal HMAC will not activate comparator C OMP.So this address AD D does not enter comparator C OMP and register REG.

Comparator C OMP compares the old and new address.If new address and old X matching addresses, this just judges is once to hit, and this hiting signal HIT is set to " height " level.If new, old X, Y address mate in this way, then hiting signal HITC is set to " height " level.So the new address that enters register REG is just preserved, up to confirm that next address enters and compares in comparer.The address of preserving will be used for hitting judgement next time.

If hiting signal HIT is in " height " level, controller BKCONTH carries out improper access.Controller BKCONTH ready signal RDY is set to " height " level, and the data that will remain among the sense amplifier module SA output to target global bit line GBL.At this moment, controller BKCONTH only selects an address corresponding to Y address.Then, Y-activates Y code translator YD to control circuit YCONT, makes the data that are kept among the sense amplifier module SA output to target global bit line GBL.If the still unclosed busy signal BSY of a preceding storing process that is used to refer to another memory bank is in " height " level, the data that then are kept among the sense amplifier module SA just can not output to target global bit line GBL.

If be in " height " level from the hiting signal HITC that hits decision circuitry HM output, then this controller BKCONT carries out improper access.Controller BKCONTH is set to " height " level with ready signal RDY, and will output to data input/output line MAOUT by the data that main amplifier MA keeps.If the unclosed busy signal BSY of a preceding storing process that is used to refer to another storage unit is in " height " level, the data that then are kept in the main amplifier module just can not output to data input/output line MAOUT.

If the old and new address does not match, just be judged as once and make mistakes, and hiting signal HIT is set to " low " level,

Controller BKCONTH then normally carries out access to storer.In other words, the word line of last access is inoperative, and the target bit line is by precharge.So a new word line is activated, so that controller BKCONTH carries out access to target memory.Read if data are the sensitive amplification module SA by correspondence, ready signal RDY is set to " height " level.

The situation (for example sending the situation of access request for the first time after the predetermined storage unit regeneration) that is stored in the data in the predetermined storage unit and reads from caches phantom piece 11 usually will be described below.If data are to read from the target storage volume that is similar to DRAM memory bank module 10 shown in Figure 4, decipher by address decoder AD by the address that address signal line ADD enters from the outside, then a word line WD is selected.After this, read and be amplified in the signal of the DRAM storage unit of choosing by word line WD among the memory cell array CA, preserve by sense amplifier module SA subsequently.At this moment, ready signal RDY is set to " height ".

Then, Y code translator YD selects some data of being preserved by sense amplifier module SA, and by global bit line GBL selected data is outputed to the device that caches memory bank module 11 outsides provide.

On the other hand, the process of data write storage unit is as follows.The data that obtain by global bit line GBL are sent to by the selected predetermined sense amplifier of Y code translator.This time before the write operation, this sense amplifier is preserved the data of reading from owing to the storage unit of selecting word line WD to be encouraged.

Be noted that the situation hit/make mistakes the quick read/write of arbitration functions (for example, a kind of access regenerative storage by access, this storer is sent the situation of memory access requests then) that adopts below.As shown in Figure 8, the address that enters from the outside through address signal line ADD is written in the X code translator.This address also enters into simultaneously and hits/make mistakes decision circuitry HM.Hitting/make mistakes decision circuitry HM address that will newly enter and the address that enters and preserve at last compares.If this two-address coupling, then hiting signal HIT places " height ".So, judge and read and preserved this target data by the address that entered last time by sense amplifier module SA.These data of being preserved by sense amplifier module SA just output to global bit line GBL.If mate in such a way these two addresses, comparative result is judged as once and hits, and the operation of X code translator AD is by controller BKCONTH cancellation, just so not from any storage unit reading.

Equally, write operation is carried out following process.If address that newly enters and the matching addresses that enters and preserve at last, this result is judged to be once and hits, and this means that the data of corresponding presumptive address are preserved by sense amplifier module SA.Therefore, the data that obtain from global bit line module GBL are sent to the predetermined sense amplifier of being chosen by Y code translator YD, not reading from the storage unit that is encouraged by selection word line WL.

The formation of controller BKCONTH also will be set to " height " level by ready signal RDY, and the signal of hitting for the device output notice of caches phantom piece 14 outsides.Controller BKCONTH controls this a series of operation according to the signal that enters by CBANKH.

If new address does not match with old address, the result of comparison is judged to be and once makes mistakes and make the caches function invalid.Fig. 9 provides the sequential chart of this situation.If be input into an address and compare to determine to makeing mistakes with old address, then the word line of last access can not be activated, just and be connected in the bit line precharge of target sense amplifier module SA.After this, be activated corresponding to the word line of new address, so the sense amplifier of choosing among the sense amplifier module SA is activated from the predetermined storage unit reading of data.Make mistakes if write operation is judged to be, the word line of last access no longer activates, and then data write in the predetermined storage unit.

When cache storage unit module 14 is equipped with when hitting/makeing mistakes decision circuitry HM by this way, if comparing to determine to hitting between new, the old address, the part read/write operation that then goes out/advance storer can be omitted so that access quickly.

Being used for every global bit line GBL of I/O data is arranged in predetermined place, so that be connected with other main amplifier modules 13 with its contiguous other caches memory bank modules 14 of placing.

For the predetermining circuit of memory bank provides the electric source line interface PL of external power source to be arranged in the precalculated position, so that give and its contiguous other functional modules power supplies of placing.Because global bit line GBL and electric source line interface PL are arranged on the normal place of each functional module by this way, when these modules and the near placement of other modules next-door neighbour, they are automatic connecting on demand.It is grand that this just might constitute storage fast.If it is grand to form the low capacity storage with caches function, can adopts caches module 11, thereby reduce the size of caches control module 16.This storage that just might constitute littler chip area is grand.

" main amplifier module "

Figure 10 represents the calcspar of this main amplifier module 13.This main amplifier module 13 comprises a main amplifier MA, the controller MACONT of a control main amplifier MA operation, and electric source line interface PL.Main amplifier MA comprises a main amplifier/output circuit MA﹠amp; BUF and write amplifier WA.This main amplifier/output circuit MA﹠amp; BUF comprises a pre-charge circuit that is used for a pair of global bit line GBL is pre-charged to supply voltage; One is used for global bit line to the potential compensation of GBL to the compensating circuit with sample value, one is used for amplifying the sense amplifier module SA of global bit line to the data of GBL, a lock-in circuit that is used for locking the output of sense amplifier module SA, and an output buffer that is used for to data input/output line MAOUT output data.Write amplifier WA comprises that one is used for from the input buffer circuit (write amplifier) of data input/output line MAOUT reception data, and other circuit.

The data that enter from memory bank by global bit line GBL during read operation are by main amplifier/output circuit MA﹠amp; The sense amplifier that BUF provides amplifies, and is locked at lock-in circuit then, so that output to the device that the grand outside of storage provides.When being in write operation, the data by data input/output line MAOUT enters from the device of storing grand outside and providing output to corresponding global bit line GBL by the input buffer circuit that places write amplifier WA.

According to control signal CMAM, as clock signal clk, read/write is selected signal RW, main amplifier control signal MACS etc., and controller MACONT controls a series of like this operation.

Main amplifier module 13 between global bit line GBL and with the input/output line MAOUT that links to each other of the grand external devices of storage between.Because main amplifier module 13 controlled target global bit line GBL by this way, it is grand to constitute the storage that its memory capacity changes by the change of memory bank number of modules.

" power circuit module "

Figure 11 represents the calcspar of power circuit module 14.This power circuit module 14 comprises voltage generation circuit VCHC, voltage generation circuit VHFC, voltage generation circuit VBBC etc.Voltage generation circuit VCHC produces voltage VCH (as the required word line voltage of X code translator AD), and this voltage VCH is higher than the voltage VCC that is added by the grand external devices feedback of storage.Voltage generation circuit VHFC produces voltage VHF (be among the sense amplifier module SA pre-charge circuit required voltage 1/2), and this voltage VCH is lower than by the grand external devices of storage and presents the voltage VCC that adds.Voltage generation circuit VBBC produces voltage VBB (as the voltage (anti--bias voltage) of substrate in the memory cell array), and this voltage VBB is lower than the voltage VSS (earthing potential) that is added by the grand external devices feedback of storage.Voltage VCC, VSS, VCH, VHF and VBB are fed to each corresponding module by electric source line interface PL.

If only adopt SRAM memory bank module 12, then power module 14 does not need voltage generation circuit VBBC etc., so they can omit from module 14.

" write data buffer module "

Figure 12 provides the example that connects between write data buffer module 18 and the main amplifier module 13.Constitute write data buffer module 18 to make storage write the data item number and the memory bank number is identical temporarily.For example, the write buffer WB of write data buffer module 18 is made up of 4 row that are used for storing the four lines write data items, the memory array of 128 row.Each storage unit MC comprises that stores a unit, and this stores unit and is made up of the input and output of interconnected two Nverter circuits and cmos transmission gate (P-ditch metal-oxide-semiconductor and N-channel MOS pipe by mutual parallel connection are formed).Each storage unit MC is connected to pair of bit lines BWL#i (I=0-3) and data line IO#j (j=0-127).For making the memory cell area minimum, storage unit MC is placed on the zone between the data input/output line MAOUT that stores grand MM4.

" the grand example of first storage "

Figure 13 is the calcspar of the grand MM1 of expression storage, and its composition comprises storage unit BAK#0, BAK#1, BAK#2 and BAK#3 (containing DRAM memory bank module 10 respectively), and main amplifier module 13, power module 14, storage control module 15 and write data buffer module 18.Functional module places the place of contiguous these modules, and electric source line interface PL places the identical precalculated position of these modules with global bit line GBL, so that automatic connecting mutually.

Electric source line interface PL0 in the power module 14 receives the feed from the grand external devices of storage.The feed of each functional module (DRAM memory bank module 10 and main amplifier module 13) all provides by power interface PL after the lifting/lowering through power module 14 on demand at its voltage.After each DRAM memory bank module 10 and main amplifier module 13 placed, data are the global bit line GBL I/O by self-configuring just.

Memory bank BANK#0, BANK#1, BANK#2 and BANK#3 by global bit line GBL from/to main amplifier module 13 reception/output datas.Main amplifier module 13 by data input/output line MAOUT receptions/output data from/to storing grand MM1.Each memory bank BANK#0, BANK#1, BANK#2 and BANK#3 are furnished with controller BKCONT, and this controller is controlled its corresponding memory bank and is worked alone.Address signal ADD and control signal CBANK are input into each memory bank.Signal CMAN control main amplifier module 13.

Figure 14 represents the calcspar of bank controller module 15.This bank controller module 15 comprises memory buffer FIFO, buffer-stored controller FIFOC, memory bank code translator BANKDEC, memory bank control signal generation circuit CBANKGEN#i (I=0-3), refresh controller REFC, main amplifier control signal generation circuit CMAMC, ready signal controller RDYC etc.

Buffer-stored controller FIFO is furnished with the function of buffer address signals ADDIN, so that duplicate the address signal ADDIN that enters in each clock period.If another memory bank is carried out access, can in each clock period, be input into address signal.But, if same memory bank is wanted consecutive access or access repeatedly in three clocks, just impossible instantaneous storage memory bank.So the address signal ADDIN in corresponding multiple bus cycle and read/write select signal RW just to be stored temporarily among the memory buffer FIFO.

The formation of buffer-stored controller FIFOC is used for controlling memory buffer FIFO.

The formation of memory bank code translator BANKDEC is the bank information that is used for determining to be included among the address signal ADDIN, determines thus which memory bank is sent access request.After the ready signal RDY#i of memory bank (i=0-3) placed " height " and notice access procedure to finish, memory bank code translator BANKDEC is the same memory bank of access once more.

Constitute memory bank control signal generation circuit CBANKGEN#i (i=0-3) in order that when next access occurs, export address signal ADD#i (i=0-3), control signal CBANK (bank selection signal BS#i, RW#i (i=0-3) etc.) respectively and write buffer control signal CWDB#i (i=0-3) the target memory memory bank.

Constituting refresh controller REFC is for regeneration request signal REF#i (i=0-3) is outputed to each memory bank.When receiving regeneration request signal REF#i (i=0-3), each memory bank produces a refresh address in controller BKCONT, itself obtains regeneration thus.

When receiving ready signal RDY#i (i=0-3) from each memory bank, ready signal controller RDYC produces ready signal READY#i (i=0-3) that supplies the controller built-in function and the ready signal that will output to the controller external devices.Constituting memory access requests device (as CPU etc.) will make and just can not send new memory access requests when device is received ready signal READY in predetermined period.Like this, memory buffer FIFO will never overflow.

Forming main amplifier control signal generation circuit CMAMC is in order to produce main amplifier control signal CMAM.

The following describes storing the internal work of grand MM1.During preliminary work, be input into an address at first, as described in Figure 2.Then, main amplifier MA is exported and be sent to data by global bit line GBL from selected memory bank.Data among the main amplifier MA output to the outside by data input/output line MAOUT.On the contrary, when write operation, the data by data input/output line MAOUT enters output to global bit line GBL through main amplifier MA, are sent to the predetermined memory memory bank again.Control into/go out this switching of main amplifier MA read/write data with control signal CMAM.

Since storing the method for grand formation and be the controller BKCONT that is adopted as the grand separate configurations of memory stores, to control each memory stores respectively grand, and by common data I/O line (global bit line GBL) with the grand main amplifier module 14 of linking of memory stores, this just might be easy to increase/subtract the grand number of storage, and is easy to change the grand capacity of each storage.In addition, because the grand use of storage has the DRAM memory bank module 10 of DRAM storage unit, it is grand to constitute a jumbo storage in little chip area.

Each memory bank BANK#0, BANK#1, BANK#2 and BANK#3 can be with SRAM memory bank module 12 and without DRAM memory bank modules 10.If use such SRAM memory bank module 12 to obtain same memory capacity, storing grand required chip area will increase when using DRAM memory bank module 10, will become faster but store grand travelling speed.Therefore, it is grand that this SRAM memory bank module is particularly suitable for the storage that those must high-speed cruising.

Figure 15 represents from storing all memory bank BANK#0 of grand MM1, BANK#1, and BANK#2 and BANK#3 be the sequential chart of reading successively.

Bank controller 15 reading address signal ADDIN when the clock signal clk rising edge arrives, and be used for providing an address (ADD#0, ADD#1, ADD#2 and ADD#3) for the address signal line ADD of each storer.When receiving address signal ADD, memory bank was prepared reading after ready signal RDY#I of each memory bank output indicated three clocks.The data of reading from each storage unit output to global bit line GBL, and the rising edge at clock signal clk outputs to data I/O line MAOUT then.Each arrow presentation address input and data output to the corresponding relation between the global bit line GBL.The peek cycle of all readings is 5 clock period.

Since memory bank by access successively as mentioned above, can conceal each access time and from these memory banks reading of data continuously.For example, if in the cycle of t3, successively different bank is input into the address, can from store grand MM1, read all data continuously at t0 shown in Figure 15.But, if the same memory bank of consecutive access then must insert during access four cycles.

In general, (as center processing unit: when CPU) reading multinomial data, the address of these data item is continuous when processor.So for reading multinomial data fast at the address of data consecutive hours, address that should the grand MM1 of designated store is distributed like this, makes that when sequence address is input into continuously, memory bank is with regard to access successively.

Figure 16 represents an example of drawing the grand MM1 of storage address figure for consecutive access alphabetic data item.The arrow mark indicates four memory bank BANK#0 shown in address space shown in Figure 16 left side and the right, BANK#1, the corresponding relation between BANK#2 and the BANK#3.Suppose that herein DRAM memory bank module 10 contains the capacity of 256K position, so the total volume of the grand MM1 of storage is the 1M position.

It is as follows that this stores the required address of grand MM1.At first, each of four memory banks of selection needs 2.Then, if the sense amplifier number in the memory bank is 1024, global bit line GBL is 128, and then the required address space will be the 1024/128=8 piece, this means when each sense amplifier will link to each other with global bit line to select 3.In addition, the number of memory cells that contains in the memory bank is 256 * 1024, if number of memory cells is several 1024 divided by sense amplifier, and consequently 256.So the word line number is 256.Being used for selecting from this 256 word line one address space is 8.So total address is 13.Because specify 8 bit address space that the selection of a word line WD is also comprised the precharge of bit line, the running of sense amplifier, the excitation of word line WD etc., required time will be longer than the time of other operations.Why Here it is can draw the grand address figure of storage, in order that a word line WD of selection in another storage is grand and do not select the memory bank of current access, consecutive access address successively quickly in the time of will selecting the word line WD that for a change address repeatedly needed with box lunch.Figure 16 represents the example of this drafting storage wang addingress figure.For 13 bit digital altogether of an address, be used to select the eight digit number word of word line WD to be arranged in a high position, and be used to select three bit digital of Y code translator YD to be arranged in interposition, select the numeral of memory bank correspondingly to be arranged in low level for two.

For example corresponding to address 0,000,000,000,000 data are read from memory bank BANK#0.Next address 0,000,000,000,001 to indicate data be to read from the memory bank BANK#1 of memory bank BANK#0 back.The sequence arrangement address makes that the data in the address 0,000,000,000,100 are to read from memory bank BANK#0 like this.

If with the grand MM1 of storage by this method row-and-column address of address ascending order access, when a new word line drove, then another memory bank of non-current access was by access.So, comprise that the precharge apparent of destination address setup time can hide, data read can be carried out continuously.Therefore, in pressing the grand MM1 of storage of address arrangement shown in Figure 16, if continuation address is input into successively, then all data bit all are easy to read from store grand MM1.

Write operation too as mentioned above read operation equally carry out.Address signal ADDIN can enter in each cycle.So write data also is sent to the grand MM1 of storage in each cycle.But write data can not always be write into target storage volume this moment immediately.Here it is why write data to be stored in cause among the write data buffer WDB temporarily.When memory bank was prepared to receive data, write data was read from write data buffer WDB, and writes memory bank.This write operation is by writing buffer control signal CWDB#i control.In other words, choose a word line BWL who writes buffering WD, then write data writes word line.After this, when target storage volume was prepared to receive data, word line BWL was selected again, and write data outputs to data line 10.Then, write amplifier enable signal WAE is activated, and the write data that outputs to data line 10 outputs to global bit line GBL by the write amplifier among the main amplifier MA#I.

" the grand example of second storage "

If SRAM memory bank module 12 is as each unit of the grand MM1 of storage, it will be faster storing grand operating speed.Figure 17 represents from the sequential chart of the grand reading of storage of four SRAM memory bank modules, 12 compositions.Because peek only needs a clock period in this case, to compare when making memory bank with employing DRAM memory bank module 10, data are read sooner.

As shown in Figure 1, storing grand MM2 is made up of four DRAM memory bank modules 10 and two SRAM memory modules 12.In this case, store the travelling speed of grand MM2 than grand faster with the storage of six DRAM memory bank modules 10.Store the essential chip area of grand MM2 in addition than littler with the grand area of the storage of six SRAM memory modules 12.

If memory bank is made of the combination memory bank, wherein each can independently be controlled, and it is grand to be easy to the mutually different storage of composition and above-mentioned functions and performance.If prepared various memory banks, the storage of every kind of target is grand will to have stronger function.

" the grand example of the 3rd storage "

Figure 18 represents to have the block scheme of the grand MM3 of storage of caches function.Store grand MM3 and comprise four memory bank BANK#0, BANK#1, BANK#2 and BANK#3, wherein each all is a caches phantom piece 11.Store grand MM3 and also comprise main amplifier module 13, power module 14, caches control module 16 and write data buffer module 18.

The caches merit of storing grand MM3 can be from by the data that read in the storage unit that the interim word line WD that activates be activated the sense amplifier, make when next access data be on the used word line of access data last time the time, the data of preserving in the sense amplifier are just exportable and need not to encourage once more this word line.

Figure 19 represents the block scheme of caches control module 16.Caches control module 16 comprises memory buffer FIFOCA, buffer memory controller FIFOCN, memory bank code translator BANKDECC, memory bank control signal generation circuit CBANKGEC#i (i=0-3), refresh controller REFCC, main amplifier control signal generation circuit CMAMCC, ready signal controller RDYCC etc.

Memory buffer FIFOCA is furnished with the function of buffer address signals ADDIN, so that input is backed up to the address signal ADDIN in each cycle.When the access of a memory bank was chosen, its address signal ADDIN can enter in each cycle.But when the access of memory bank is not chosen, can not carry out access to memory bank immediately.So, memory buffer FIFOCA (?) store address signal ADDIN and read/write temporarily and select signal RW.Address signal ADDIN and RW are corresponding to a plurality of bus cycles.

Form buffer memory controller FIFOCN and be used for controlling memory buffer FIFOCA.

Form memory bank code translator BANKDECC and be for the bank information that is included among the address signal ADDIN is deciphered, thereby determine which memory bank is sent access request.

Forming memory bank control signal generation circuit CBANKGEC#i (i=0-3) is the address signal ADD#i (i=0-3) that the memory bank that sends access request is sent in order to export, and control signal CBANK (bank selection signal BS#i, RW#i (i=0-3), BSY#i (i=0-3) etc.) and write data buffer control signal CWDB#i (i=0-3).

Forming regeneration control signal REFC is for regeneration request signal REFS#i (i=0-3) and regeneration look-at-me REFE#i (i=0-3) are outputed to each memory bank.When receiving regeneration request signal REFS#i (i=0-3), target storage volume produces the refresh address among the controller BKCONTH, itself obtains regeneration thus.When receiving regeneration look-at-me REFE#i (i=0-3), target storage volume stops regeneration.If regeneration ending or time-out, this controller BKCONTH exports ready signal RD#i (i=0-3).

When receiving ready signal RDY#i (i=0-3) from memory bank, prepare control device RDYCC produces the ready signal READY that is used for the ready signal READY#i (i=0-3) of controller internal work and will outputs to the device of controller outside.If ready signal does not enter in predetermined period, the device (as CPU etc.) of then forbidding being subordinate to memory access requests sends any memory access requests.Therefore memory buffer FIFOCA will never overflow.

Main amplifier control signal generation circuit CMAMCC produces main amplifier control signal CMAM.

Next the work of the grand MM3 of explanation storage.Figure 20 shows the operation sequential chart of storing grand MM3.If in caches control module 16, then 16 pairs of memory banks corresponding to this address of caches control module carry out access through address of address signal line ADDIN input.In the memory bank of address, hit/make mistakes decision circuitry HM judge this address and last time the access address whether mate.If matching addresses is judged that then target data has been read and is kept at sensitive the amplification among the piece SA by old address.So judged result is through ready signal line RDY#i notice caches control module 16.Then, this caches control module 16 outputs to the target external device as ready signal READY with ready signal RDY#i.

Then, the data of preserving among the sense amplifier module SA are selected and are exported from MAOUT by global bit line GBL and main amplifier MA through the Y code translator.Yet, kept in from these data of MAOUT output by global bit line GBL and main amplifier MA, to be apprised of busy signal BSY#i up to main amplifier and to place " low ", i.e. the last access of another memory bank finishes.

If cache memory (the same one page of repeated access) is by this way chosen, just can ignore the precharge of data line and the excitation of word line etc., the result makes its operation faster than normal access.In addition, since part operation is left in the basket, power dissipation also can reduce.

Owing to when caches is chosen by this way, can do the reading duration of data output with two clock period, just may make DRAM store grand operation and accelerate, even its chip area is very little.

If misfit the address, then carry out normal access in word line removal excitation and data line precharge background storage.

Described in grand first example of above-mentioned storage, if processor (CPU) is read multinomial data, these data item addresses usually are continuous usually.Therefore, for quick reading of data from these continuation addresses, the address of answering the grand MM3 of designated store, when entering with convenient continuation address by these addresses of sequential access of memory bank.

Figure 21 be expressed as make data can be in the grand MM3 of storage consecutive access and the example of the grand MM3 of the storage address figure that draws.The line mark indicates four memory bank BANK#0 shown in the address space shown in Figure 21 left side and the right, BANK#1, BANK#2, the corresponding relation of BANK#3.In this case, suppose that DRAM memory bank module 10 contains the 256K bit capacity, the total volume of then storing grand MM3 then is the 1M position.

The required address structure of the grand MM3 of this storage is as follows.At first, need with 2 each that select in four memory banks.Then, if the sense amplifier number of configuration is 1024 in the memory bank, global bit line GBL number is 128, and the required address space will be the 1024/128=8 road, and this means as selecting each sense amplifier to be connected to global bit line needs 3.In addition, the number of memory cells that disposes in the memory bank is 256 * 1024, if number of memory cells is several 1024 divided by sense amplifier, and consequently 256.So the word line number is 256.Being used for selecting in 256 word lines one address space is 8.So total address is 13.Because specify the selection of a word line WD of 8-bit address space also to comprise the precharge of bit line, the running of sense amplifier module SA, the excitation of word line WD etc., required time will be longer than the time of other operations.Why Here it is can draw the grand address figure of storage, in order that a word line WD of selection in another storage is grand and do not select the memory bank of current access, consecutive access address successively quickly in the time of will selecting the word line WD that for a change address repeatedly needed with box lunch.

Figure 21 provides the example of drawing this storage wang addingress figure.For 13 bit digital altogether of an address, be used to select the eight digit number word of word line WD to be arranged in a high position, be used to select the two digits of memory bank correspondingly to be arranged in interposition, and be used to select three bit digital of Y code translator YD to be arranged in low level.

For example, be present in address 0,000,000,000,000 and 0,000,000,000, the data between 111 are read from memory bank BANK#0 by a word line WD.Three selections that are used for indicating the Y code translator in back.The four or five of back is used for selecting a memory bank.Be present in address 0,000,000,001,000 and 0,000,000,001, the data between 111 are on the word line WD among the next memory bank BANK#1 that follows after memory bank BANK#0.With the address appointment that so circulates, make to be present in address 0,000,000,001,000 and 0,000,000,001, the data between 111 become the data on that word line WD of memory bank BANK#0 again.

If the grand MM3 of the storage that draw by this way its address is by address access successively, then when a new word line was energized, another memory bank (memory bank that is different from current access) was by access.Like this, comprise that the precharge apparent of destination address setup time can indistinctly be hidden, continuous-reading becomes possibility therefrom.Therefore, in the address distribution grand MM3 of storage as shown in figure 16, if entering successively of sequence address then is easy to read all data from memory bank MM3.According to this method,, just all read by the data in the storage unit of this word line excitation in case word line is energized.Like this, just may will reduce to minimum from the required power dissipation of continuation address reading.

Write operation also resembles and carries out the above-mentioned read operation.Address signal ADDIN can enter in each clock period.Then, write data also is sent to the grand MM3 of storage in each clock period, yet in this case, write data always can not write each memory bank immediately.Why Here it is will be stored temporarily in write data reason among the write data buffering WDB.When memory bank was prepared to receive data, write data was read and is write in the memory bank from write data buffering WDB.This write operation is by write data buffer control signal CWDB#i control.In other words, a word line BWL who writes buffering WB is selected, and write data just outputs to this word line.After this, when being subordinate to memory bank preparation reception data, a word line BWL is selected once more, and write data outputs to data line 10.Then, write amplifier enable signal WAE is energized, and the write data that outputs to data line 10 then outputs to global bit line GBL by the write amplifier that disposes among the main amplifier MA#I.

Choose mistake (page or leaf is chosen mistake) because cache memory has taken place in the address that enters in cycle t4 shown in Figure 20, memory bank BANK#0 is just normal access after word line is eliminated excitation once, data line precharge then, the execution time is increased to seven clock period.Therefore, if hit when the cache memory like this to make mistakes as sense amplifier module SA, then word line be energized and data line by the just normally access of precharge background storage.So the problem that this running will face is the situation that will be longer than normal reading when not adopting the caches function its storage time.

In addition, the memory bank that enters the address corresponding to cycle t5, t6, t7 is chosen respectively as shown in Figure 20, and the caches function can be used to output data quickly.However, because the address failure of caches function to entering in cycle t4, the work of CPU is to being subjected to remarkable restriction corresponding to the data output that enters the address after reaching in the cycle t5, and therefore the caches function can not effectively utilize.In this example, speed buffering chooses mistake that follow-up data can not be exported, and the regeneration of DRAM storage unit running also will cause the obstruction of data output sometimes.

Figure 22 represents to store every reading duration value of grand MM3.Suppose that the reading duration shown in Figure 22 is to be in that address signal ADDIN enters and data output between data I/O line MAOUT.If the data that main amplifier MA preserves are selected, these data shown in reading duration value 1 output of " Main ".If the data of preserving among the sense amplifier SA are selected, then data shown in reading duration value 2 outputs of " Sense ".If memory bank is by normal access, data shown in reading duration value 5 outputs of " Ordinary ".If run into mistake, data shown in 7 outputs of " Mishit " reading duration value.Be in the regeneration period if be subordinate to DRAM, then the stand-by period behind the regeneration ending is got illustrated various value " Ref.E ".

Fast the enhancing system of operation can't reading behind the grand regeneration ending of the storage that contains the DRAM memory bank if one has the caches function, and then this system performance will seriously be demoted.For fear of this problem, storing grand regeneration can earlier begin.If send memory access requests at this regeneration period, then may end primary recycling, after handling the access request of storer, restart then.When stopping one time like this, regeneration will get value shown in Figure 22 " Ref.C " to the reading duration of output data.If store and grandly form, and be furnished with above-mentioned caches function by the DRAM memory bank, then store grand should corresponding various reading duration values.

In addition, if memory bank is worth accesses with the various different reading durations, then data are exported through regular meeting along with the address input sequence suspends.For example, if in another memory bank, choose the address of a sense amplifier cache memory after an address enters the memory bank of regenerating, to enter just, usually can more early export from the address that sense amplifier module SA cache memory is read, but data output must suspend, up to the data end of output of reading according to the address that early enters.

" the grand example of the 4th storage "

Shown in Figure 23 is the grand block scheme of storage of this OPADD and data ID signal.The grand MM4 of this storage has the storage order control module 17 of band ID, is substituted in the caches control module 16 that disposes among the grand MM3 of storage.2 ID signals of storage order control module 17 output of band ID like this, enter order if can not consider the address as address ID signal AID and data ID signal DID, then can more early export corresponding to after enter the address data.This feasible access memory bank quickly.

Below with the operation of this memory bank MM4 of brief description.If enter an address, then just obtain notifying determining one corresponding to ID number of entering address and export this ID number as address ID signal AID with the storage order control module 17 of ID through address signal line ADDIN.ID number of output preserved by the memory access processor and arrived up to data.On the other hand, 17 pairs of memory banks corresponding to entering address of storage order control module of band ID carry out access, the output sense data, and ID number of OPADD when input appointment is as data ID signal DID.When receiving data and ID, ID number of receiving with the companion data of ID number of will be when memory cell access receiving from the storage order control module 17 of band ID of processor compares.If two ID number couplings, processor is found out address and data in correspondence with each other.Since address can be corresponding with data by ID number like this, the sequence number that data are exported when there is no need the address input sequence with the grand access of storage is complementary, and is essential in the former technology of this point.As mentioned above, even when storage access is (this formation is comprised the DRAM memory bank and be equipped with the caches function will become problem) when carrying out continuously with the different reading durations, the data of preparing can be exported earlier regardless of the address input sequence earlier, be designated as the data output in evening possibly of big reading duration, because address and data can be corresponding one by one by the ID difference.So by the such address and the corresponding relation of data, memory bank can pass through ID number more effectively access.

Figure 24 represents the block scheme with the storage order control module 17 of ID.The storage order control module 17 of band ID comprises lock-in circuit LTCH, memory bank decoding scheme BNKDEC, memory bank control sequence number generation circuit CBNKG#i (i=0-3), refresh controller RFRSHC, ID sequence number controller IDCNT etc.

Lock-in circuit LTCH selects signal RW in rising edge difference reading address signal ADDIN and the read/write of clock sequence number CLK.

Memory bank decoding scheme BNKDEC deciphers the bank information that is included among the address signal ADDIN, determines which memory bank is sent access request thus.

Memory bank control signal generation circuit CBNKG#i (i=0-3) output indicates address signal ADD#i (i=0-3), control signal CBANKH (the bank selection signal BS#i which memory bank is sent access request, RW#i (i=0-3), BSY#i (i=0-3) etc.), memory bank request signal BR#i (i=0-3) and write data buffer control signal CWDB#i (i=0-3).When memory access requests is sent, the unconditional output of memory bank request signal BR#i (i=0-3), but bank selection signal BS#i can not export before the access of target storage volume starts.

Refresh controller RFRSHC is to each memory bank output regeneration request signal REFS#i (i=0-3) and regeneration look-at-me REFE#i (i=0-3).When receiving regeneration request signal REFS#i (i=0-3), be subordinate to memory bank and in controller BKCONTH, produce a refresh address, itself obtain regeneration.If be input into regeneration look-at-me REFE#i (i=0-3) during the regeneration running, then regeneration suspends.

ID signal controller IDCONT produces address ID signal AID and data ID signal DID from memory bank request signal BR#i (i=0-3) and ready signal RDY#i (i=0-3).Because it is grand or from the grand output of same storage that data can be input into same storage by the order that enters the address, thereby bank number and ID number can be in correspondence with each other.Therefore, just can judge by memory bank request signal BR#i (i=0-3) which memory bank is carried out access.This just might produce address ID signal AID from memory bank request signal BR#i (i=0-3).In addition, also might judge it is which memory bank is ready according to indicating the ready signal RDY#i (i=0-3) that is subordinate to memory bank preparation output/reception data.Like this, just can produce data ID signal DID by ready signal RDY#i (i=0-3).

Main amplifier control signal generation circuit CMMC produces main amplifier control signal CMAM.

Figure 25 represents the working timing figure of the grand MM4 of storage of output data as mentioned above and ID number.At first, four address a, b, c enters into address signal line ADDIN successively with d (different storage wang addingress), and then, four ID number (each enters the address corresponding to one) exports as address ID signal AID.When the read operation end and data when output, also export for these ID numbers as data ID signal DID.

For example, ID number 1 is assigned to the address a that is introduced into.If but this address a is corresponding to a memory bank of regenerating, data A exports with data ID signal DID in cycle t12 so.Be for assigned I D number that 2 address b is corresponding to the data that are kept among the sense amplifier SA.Thereby these data are in 2 outputs of reading duration value.Address c is corresponding to the data output that suspends regeneration, and address d also will export therefrom corresponding to the data that exist in main amplifier MA.

Because this example has utilized the address of using ID number respectively and the corresponding relation between the data, thereby need not to make address input order and data output order to mate.So this example makes might export the data of preparing earlier earlier, thereby allows the memory bank access to accelerate.

In addition, overlapping will appear in address input timing and data output timing, depend on the address input timing.In this case, can think and more be badly in need of, so this high priority data output corresponding to the data that are introduced into the address.Busy signal BSY#i (i=0-3) is used for controlling this running.

For example, certain operation is the access procedure at the storer of 7 o'clock reading durations data output of using " Mishit " expression as Figure 22.Data corresponding to address e are exported in cycle t11.Yet the cycle that should export corresponding to the data of address f is t12.But the output of this data has overlapping with data output corresponding to address a.Therefore, since right of priority has been given the data corresponding to address a that are introduced into, then the stand-by period of exporting corresponding to the data of address f will increase one-period.So these data are exported in cycle t13.

Figure 26 shows the inner working of each memory bank.For the purpose of simplifying narration, the operation that two memory banks are only arranged shown in Figure 26.At first, two address a and b enter, and make two memory bank BANK#0 and BANK#1 by access.Choose mistake because caches takes place in memory bank BANK#0, word line WD removes excitation immediately.This word line WD finishes the back in corresponding sense amplifier precharge and is encouraged again.Then, sense amplifier is driven.

In memory bank BANK#1, cache memory is selected.Like this, signal HIT#1 is output, and data B outputs to global bit line GBL immediately.After this, the sense amplifier among the memory bank BANK#0 finish running, sense data A also outputs to global bit line GBL.

Write operation also carries out as above read operation.Address signal ADDIN can enter in each cycle.Then, write data is sent to the grand MM4 of storage in each cycle.Yet, write number and can not always write each memory bank immediately.Therefore, for fear of this problem, write data is stored temporarily among the write data buffering WDB.When memory bank was prepared to receive data, target memory is read and outputed to write data then from write data buffering WDB.Write data buffer control signal CWDB#i is used for controlling this operation.In other words, the word line BWL of write data buffering WB is selected, and write data writes this word line.After this, when being subordinate to memory bank preparation reception data, word line BWL chooses once more, and write data outputs to data line 10.Then, write amplifier enable signal WAE is energized, and the write data that outputs to data line 10 outputs to global bit line GBL by the write amplifier among the main amplifier MA#I.At this moment, also output simultaneously of data ID signal DID.

" the another kind of structure of the access sequence control module of band ID "

Figure 27 represents the another kind of block diagram with the access sequence control module of ID.Sort controller 17 comprises that the address submits to/gather control module 17A, ID controller 17B and order to submit part 17C to.When receiver address signal ADDIN, control module 17A indication ID controller 17B OPADD ID signal AID is submitted/gathered in the address to.ID controller 17B exports an address ID as address ID signal AID with reference to a table (back description).In addition, the address submits to/gathers control module 17A to require order to submit to part 17C to send an order to entering the pairing memory bank in address.The order submission part 17C that manages each memory bank state sends to the address and submits to/gather control section 17A to send out the sequential of Input Address, and exports an order simultaneously.Order submits to part 17C also to export a control signal CMAM, and indication ID controller 17B output data ID is in order that by determining to move main amplifier MA from the order of each memory bank output data.ID control module 17B exports an address ID as data ID signal DID with reference to a table.This address ID is sent as the address of target data.

The control flow chart of Figure 28,29 expression ID control module 17B.Table MM-TABLE is used for preserving the information (effectively: after this VALID is used as effective marker) that indicates ID number (ID No.), address value (ADD) and effective corresponding relation thereof.Data are write/visit this table MM-TABLE.Table management state machine TMSM controls these and writes and accessing operation.The synoptic diagram of the information flow among Figure 28 and 29 expression central information unit (CPU), memory bank BANK#i and the table MM-TABLE.

Figure 28 represents to send the process flow diagram of address ID signal AID when address signal ADD enters.The address signal ADDIN (being expressed as address signal ADD later on) that enters from center processing unit (CPU) outputs to target storage volume BANK#i as address signal ADD.Determined corresponding to ID number of address signal ADD for one like this.Turn back to CPU as address ID signal AID this ID number.After this, operating process shown in Figure 28 will be corresponding as follows in an embodiment.

(1) CPU is sent to the address with address signal ADD (ADD=6) and submits/gather control module 17A to.

(2) address submits to/gathers control module 17A that address signal ADD (ADD=6) is outputed to target storage volume BANK#i.

(3) address submits to/gathers control module 17A that address signal ADD (ADD=6) is sent to table MM-TABLE.

(4) address signal A DD (ADD=6) is write table MM-TABLE corresponding to the space of ID number (ID=#4), make significant notation VALID come into force (being expressed as " Yes " among Figure 28).

(5) read by table MM-TABLE assignment address ID signal AID (AID=#4).

(6) the address ID signal AID (AID=#4) of assignment returns CPU.

CPU preserves the value of address ID signal AID (AID=#4), makes whether to mate the corresponding relation of learning address and data by surveying the AID value with the data ID signal DID that adds when target data is exported.

Figure 29 sends the process flow diagram of data ID signal DID when showing data output.Be input into and indicate from memory bank BANK#i

The signal of output data is deciphered the address signal ADD of memory bank in order to access then.Corresponding to ID number of address signal ADD by checking.Return CPU for this ID number as data ID signal DID.After this, operational flowchart shown in Figure 29 will be corresponding as follows in an embodiment.

(1) ready signal RDY#i submits to the memory bank BANK#i of part 17C to return from output data to order, and address signal ADD (ADD=6) submits to/gathers among the address lock-in circuit ADDLT#i the control module 17A and obtain from the access address being locked in the address thus.

(2) address signal ADD (ADD=6) is input into table MM-TABLE.

(3) in table MM-TABLE, search for ID number corresponding with address signal ADD (ADD=6).

(4) sense data ID signal DID (DID=#4) from table MM-TABLE.

(5) data ID signal DID (DID=#4) is outputed to CPU.

When receiving data and data ID signal DID (DID=#4), CPU can be worth knowing these data corresponding to address signal ADDIN (ADDIN=6) from the address ID signal AID (AID=#4) of previous reception.

The content of MM-TABLE table shown in Figure 28 is different from the content of MM-TABLE table shown in Figure 29.In MM-TABLE table shown in Figure 29, corresponding to the significant notation inefficacy (being expressed as " No " among Figure 29) of IDNo.#2, thereby address space ADD is blank.This expression is read corresponding to the data of address value 2, and #2 is sent to CPU as the data ID signal value.If significant notation VALID lost efficacy, just can be input into a new address.In MM-TABLE shown in Figure 29 table, come into force corresponding to the significant notation VALID of IDNo.#5, and write address AD D 1.More than difference between two kinds of situations show, be 0 data corresponding to address AD D value 6 store when grand as address AD D value target approach and during data output between read, 1 enter then as address value ADD.

Figure 30 shows the calcspar of MM-TABLE.Table MM-TABLE comprises content-addressed memory (CAM) CAM etc.For example, if control signal AW places " height " level, the halt circuit AINH that links ends to link, and content-addressed memory (CAM) CAM word line selects circuit WSEL to be driven, and the word line of significant notation inefficacy is selected thus.In this state, address AD D enters content-addressed memory (CAM) CAM and is kept at wherein.If one ID number corresponding with the word line of content-addressed memory (CAM) in advance, selected word line obtains address ID signal AID therefrom through encoder circuit ENDER coding.If control signal AW is changed to " low " level, the halt circuit AINH that links startup links, and the content-addressed memory (CAM) word line selects the running of circuit WSEL therefore to stop.If the address enters content-addressed memory (CAM) CAM in this state, the work that links starts, and the matched line of the row of storage appropriate address is changed to " height " level.If one ID number in advance corresponding to the matched line of content-addressed memory (CAM) CAM, selected matched line obtains data ID signal DID therefrom by coding circuit ENDER coding.In addition, if significant notation VALID is resetted on the matched line of content-addressed memory (CAM) CAM, then may lose efficacy corresponding to ID number of access end address.

Can be used to change the address for ID number and be input into the grand and data of storage from storing the order of grand output.So the data of preparing can be exported earlier earlier, thereby it is grand to form the storage with very effective caches function at an easy rate.

" application of multi-processor system "

The method that adopts ID number as previously discussed is also applicable to the multi-processor system.Shown in Figure 31 is the block scheme of this multi-processor system.In this example, two processors (CPU#1 and CPU#2) are shared a grand MM of storage.This multi-processor also comprises address bus ABUS, data bus BUS, address ID signal wire, the processor ID signal wire PID of data ID signal wire DID and instruction processorunit number.When sending the address, each processor output processor ID signal PID, notice has been sent the grand MM of storage of the processor of its address.Store the processor ID signal wire pid value of grand management, make that processor ID signal wire PID exports again when data are exported, thereby confirm the target processor that data are sent to address value.

Figure 32 represents when entering an address, from storing the process flow diagram that grand MM sends address ID signal AID and processor ID signal PID.Except at this moment processor ID signal PID being added to the management of this table, this process flow diagram is with shown in Figure 28 identical.After this, the operating process shown in Figure 32 is corresponding in an embodiment as follows.

(1) address signal ADD (ADD=6) and processor ID signal PID (PID=0) enter the address by CPU and submit/gather control module 17A to.

(2) address submits to/gathers control module 17A that address signal ADD (ADD=6) is outputed to target storage volume BAKNC#i.

(3) address submits to/gathers control module 17A that address signal ADD (ADD=6) and processor ID signal PID (PID=0) are input among the table M-TABLE.

(4) address signal ADD (ADD=6) and processor ID signal PID (PID=0) are written to the position of table M-TABLE corresponding to ID number (AID=#4), then, significant notation VALID come into force (" Yes " shown in Figure 32).

(5) the address signal AID (AID=#4) by table M-TABLE assignment reads.

(6) with address signal ADD (ADD=6) and the processor ID signal read

PID (PID=0) turns back to CPU.

Figure 33 sends the process flow diagram of data ID signal DID and processor ID signal PID when representing data output.Except at this moment management was added to processor ID signal PID on this table, this process flow diagram was with shown in Figure 29 identical.After this, the above-mentioned operation workflow shown in Figure 33 will be corresponding as follows in an embodiment.

(1) ready signal RDY#i submits to the memory bank BANK#i of part 17C to return from output data to order, thereby obtains address signal ADD (ADD=6) from the address lock-in circuit ADDLT#i that is used for submitting in the address/gather lock address the control module 17A

(2) address signal ADD (ADD=6) is input into table M-TABLE.

(3) in table M-TABLE search corresponding to ID number (ID=#4) and the processor ID signal PID (PID=0) of address signal ADD (ADD=6).

(4) sense data ID signal DID (DID=#4) and processor ID signal PID (PID=0) from table M-TABLE.

(5) data ID signal DID (DID=#4) and processor ID signal PID (PID=0) are outputed to CPU.

Figure 34 provides the block scheme of table M-TABLE.Table M-TABL comprises content-addressed memory (CAM) CAMM, random access memory ram M etc.For example, if control signal AW places " height " level, the termination circuit AINH that then links stops association, and the content-addressed memory (CAM) word line selects circuit WSEL to be driven, thus a word line choosing effective marker to lose efficacy.Control signal AW allows matched line/word line of content-addressed memory (CAM) CAMM to select circuit WMSEL to select a word line, and the word line of this word line with random access memory ram M linked to each other.Under this state, address signal ADD enters into content-addressed memory (CAM) CAMM and is stored in the there.Processor ID signal PID enters into random access memory ram M and is stored in the there.If one ID number corresponding with the word line of content-addressed memory (CAM) CAMM in advance, selected word line can be by coding circuit ENDER coding, thereby obtains address ID signal AID.If control signal AW places " low " level, the halt circuit that links startup links, and the content-addressed memory (CAM) word line selects circuit WSEL to stop its operation.Control signal AW allows matched line/word line of content-addressed memory (CAM) CAMM to select circuit WMSEL to select a matched line, and the word line of this matched line with random access memory ram M linked to each other.If address signal ADD enters into content-addressed memory (CAM) under this state, then connect running and start, and this row matched line of storage destination address is changed to " height " level.Subsequently, processor ID (PID) reads from random access memory ram M.If one ID number corresponding with the matched line of content-addressed memory (CAM) CAMM in advance, then selected matched line can be by scrambler ENDER coding, thereby obtains data ID signal DID.If effective marker VALID resets on the matched line of content-addressed memory (CAM) CAMM, then may lose efficacy corresponding to ID number of access end address.

Figure 35,36 provides management processor ID number process flow diagram.Figure 35 is the process flow diagram that reads address ID signal AID.As the grand MM of storage, CPU also be equipped with one show ID number and the address between the table CPU-TABLE of corresponding relation.Table management state machine CSMC key CPU-TABLE, thus point out ID number and the address between corresponding relation.After this, workflow shown in Figure 35 will be corresponding as follows in an embodiment.

(1) address ID signal AID (AID=#4) and processor ID signal PID (PID=0) are entered by the grand MM of storage.

(2), then address signal ADD (ADD=6) and address ID signal AID (AID=#4) are input among the table CPU-TABLE if processor ID signal PID (PID=0) indicates the ID of himself processor.

(3) address signal ADD (ADD=6) and address ID signal AID (AID=#4) are written to the position of table CPU-TABLE, make effective marker VALID come into force (" Yes " shown in Figure 35) corresponding to ID number (AID=#4).

Figure 36 represents the process flow diagram of reading of data ID signal DID, and after this, operating process shown in Figure 36 will be corresponding as follows in an embodiment.

(1) address ID signal DID (DID=#4) and processor ID signal PID (PID=0) are input into the grand MM of storage.

(2), then data ID signal DID (DID=#4) is input among the table CPU-TABLE if processor ID signal PID (PID=0) indicates the ID of himself processor.

(3) in table CPU-TABLE search corresponding to the address signal ADD (ADD=6) of data ID signal DID (DID=#4).

(4) from table CPU-TABLE, read address signal ADD (ADD=6).

(6) OPADD signal ADD (ADD=6).

Figure 37 provides the calcspar of table CPU-TABLE.Table CPU-TABL contains content-addressed memory (CAM) CAMC, random access memory ram C etc.For example, if control signal AW places " height " level, the halt circuit AINH that links stops to connect, and the content-addressed memory (CAM) word line selects circuit WSEL to be driven, thus a word line choosing effective marker to come into force.In addition, control signal AW allows matched line/word line of content-addressed memory (CAM) CAMC to select circuit WMSEL to select a word line, and the word line of this word line with random access memory ram C linked to each other.Address ID signal AID enters into content-addressed memory (CAM) CAMC and is stored in the there under this state.Address AD D enters into random access memory ram C and is stored in the there.If control signal AW is changed to " low " level, the halt circuit AINH that links starts connection, and the content-addressed memory (CAM) word line selects circuit WMSEL to stop its running.In addition, control signal AW allows matched line/word line of content-addressed memory (CAM) CAMC to select circuit WMSEL to select a matched line, and the word line of this matched line with random access memory ram C linked to each other.If data ID signal DID enters into content-addressed memory (CAM) CAMC under this state, then connect the running that links and start, and the matched line of the row of storage Target id number is changed to " height " level.Thereupon, address AD D reads from random access memory ram C.May lose efficacy because of effective marker VALID resets on the matched line of content-addressed memory (CAM) CAMC corresponding to ID number of access end address.

Owing to utilize to change the address for ID number and enter the grand order of storage and data from storing the order of grand output, thereby the data of preparing earlier can be exported earlier.It is grand that this just might form the storage that is equipped with effective caches function at an easy rate.In addition, the grand application of this storage makes and might form the shared storage system that adopts multi-processor.

Specifically described the present invention is not limited only to these examples with reference to several examples; Can freely make amendment not exceeding under the key concept condition of the present invention.

Some the representative effect of the present invention that to briefly narrate in this application below to be disclosed.

Specifically, store grand in resembling in the database that functional module is stored in these functional modules such as memory bank, main amplifier, power supply, controller etc.By combination with dispose these functional modules and can form easily and thisly be equipped with the storage of various functions or variable memory capacity grand.

Though these functions provide in extensive logical circuit (as microprocessor and presentation manager) inside or outside usually, in forming each grand memory bank of storage or in the controller of control store body, all be equipped with control function.Therefore, for the purpose of the present invention, design resembles microprocessor and the extensive logical circuit of this class of presentation manager is easily.

And, can carry out consecutive access to a plurality of memory banks, the data of preparing can be exported earlier earlier, thereby might reduce page fault and regeneration loss mistake.

Claims (20)

1. semiconductor device that on semiconductor chip, has storer, described storer comprises:

A kind of memory cell array;

A kind of sense amplifier piece that is connected to described memory cell array;

A kind of line decoder that is connected to described memory cell array;

A kind of column decoder that is connected to described sense amplifier piece; And

A kind of controller that is used for controlling described memory cell array, described line decoder, described column decoder and described sense amplifier piece;

Wherein said controller another address in the next memory cycle enters a back address of preserving in the memory cycle;

Wherein said controller compares another address with the next memory cycle, the address in the memory cycle, when mate by described comparative result two addresses, make the data that are kept in the described sense amplifier piece output to the outside of described storer and reading of data from described memory array not, and

Wherein said controller is also exported a signal, indicates the outside of described storer to prepare to read data or described storer is write data from described storer.

2. semiconductor device that on semiconductor chip, has a plurality of storeies, described storer comprises:

A kind of memory cell array;

A kind of sense amplifier piece that is connected to described memory cell array;

A kind of line decoder that is connected to described memory cell array;

A kind of column decoder that is connected to described sense amplifier piece; And

A kind of controller that is used for controlling described memory cell array, described line decoder, described column decoder and described sense amplifier piece;

Wherein said controller another address in the next memory cycle enters the address of back in one memory cycle of preservation;

Wherein said controller comprises a kind of comparer, and this comparer compares another address with the next memory cycle, the address in the memory cycle, and

Wherein said controller also comprises a kind of output circuit, one first signal of described output circuit output, and this signal indicates the outside of described storer to prepare to read data or described storer is write data from described storer.

3. according to the semiconductor device of claim 2, when to the some beginning read operations in described a plurality of storeies and in described comparer during relatively two matching addresses, wherein said controller makes and is kept at the outside that the interior data of described sense amplifier piece output to described storer, and not from described memory cell array reading of data.

4. according to the semiconductor device of claim 2, some read operations begin in to described a plurality of storeies, and when two addresses of comparing in described comparer did not match, wherein said controller read data from described memory cell array.

5. according to the semiconductor device of claim 2, also comprise the common bit lines that is connected to described a plurality of storeies, a kind of sense amplifier and a kind of write amplifier, two kinds of amplifiers all are connected on the described common bit lines.

6. according to the semiconductor device of claim 5, also comprise a kind of control module, and described control module produces second signal that will send each described multi-memory according to described first signal that sends from each described multi-memory.

7. according to the semiconductor device of claim 6, wherein each described a plurality of storer arrives described common bit lines according to the described secondary signal output data in read operation.

8. according to the semiconductor device of claim 7, wherein said control module produces the 3rd signal that is used for choosing a described multi-memory.

9. semiconductor device on semiconductor chip comprises:

First kind of storer and second kind of storer, every kind all has a kind of memory cell array, a kind of sense amplifier piece that is connected to described memory cell array, a kind of line decoder that is connected to described memory cell array, a kind of column decoder that is connected to described sense amplifier piece, and a kind of controller that is used for controlling described memory cell array, described line decoder, described column decoder and described sense amplifier piece; And

A kind of control module that is connected to described first and second storeies;

No matter wherein said control module can be from described first and second kinds of memory read datas and the storage access order, wherein said controller unit is exported an identifying information corresponding to Input Address when certain Input Address enters, and when reading an information according to Input Address, export described identifying information

10. semiconductor device on semiconductor chip comprises:

First kind of storer and second kind of storer, every kind all has a kind of memory cell array, a kind of sense amplifier piece that is connected to described memory cell array, a kind of line decoder that is connected to described memory cell array, a kind of column decoder that is connected to described sense amplifier piece, and a kind of controller that is used for controlling described memory cell array, described line decoder, described column decoder and described sense amplifier piece; And

A kind of control module that is connected to described first and second storeies;

No matter wherein said control module can be from described first and second kinds of memory read datas and the storage access order, the address that wherein said controller will newly enter compares with the pairing address of information that is kept in the described sense amplifier piece by last storage access, and when the described comparative result of two addresses mates, then export the information of preserving in the described sense amplifier piece, and from described memory cell array, do not read information.

11. according to a kind of semiconductor device of claim 10, wherein said controller can be with the described storer of certain address match notifications outside.

12. the semiconductor device on semiconductor chip comprises:

First kind of storer and second kind of storer, every kind all has a kind of memory cell array, a kind of sense amplifier piece that is connected to described memory cell array, a kind of line decoder that is connected to described memory cell array, a kind of column decoder that is connected to described sense amplifier piece, and a kind of controller that is used for controlling described memory cell array, described line decoder, described column decoder and described sense amplifier piece;

A kind of control module that is connected to described first and second storeies;

No matter wherein said control module can be from described first and second kinds of memory read datas and the storage access order;

The common bit lines of the sense amplifier piece of a kind of sense amplifier piece that is connected to described first memory and described second memory; And

A kind of first circuit that comprises amplifier amplifies the signal from described sense amplifier in the described common bit lines, and a kind of circuit that passes the signal to described sense amplifier by described common bit lines.

13. a kind of semiconductor device according to claim 12 also comprises a kind of second circuit, it contains and is used for producing for described first, second storer and the used voltage of described first circuit.

14. according to a kind of semiconductor device of claim 13, wherein said semiconductor device can by change be connected to described first or second circuit on described first or second memory number change memory span.

15., also comprise a kind of computing circuit according to each a kind of semiconductor device in the claim 9,10,12.

16. according to each a kind of semiconductor device in the claim 9,10,12, wherein said memory cell array comprises the DRAM storage unit.

17. a semiconductor device that has a plurality of storeies on semiconductor chip, every kind of described a plurality of storeies comprise:

A kind of memory cell array;

A kind of sense amplifier piece that is connected to described memory cell array;

A kind of line decoder that is connected to described memory cell array;

A kind of column decoder that is connected to described sense amplifier piece; And

A kind of controller that is used for controlling described memory cell array, described line decoder, described column decoder and described sense amplifier piece;

Wherein said semiconductor device also comprises a kind of common bit lines and a kind of sense amplifier that is connected to described common bit lines that is connected to described a plurality of storeies; And

Wherein said controller enters X address and the Y address of back in the preservation memory cycle in the address of next memory cycle.

18. according to a kind of semiconductor device as claim 17, wherein said controller comprises a kind of comparer, and described comparer is compared the X in the memory cycle, Y address with X, Y address in next memory cycle.

19. according to a kind of semiconductor device as claim 18,

Wherein after a read operation to a described multi-memory begins, when relatively X matching addresses in described comparer, described controller makes the data that are stored in the described sense amplifier piece output to described storer outside, not from described storage array reading of data, when relatively X and Y address when all mating in described comparer, the data that described controller will be stored in the sense amplifier piece output to described storer outside, not from described storage array reading of data, and X in two memory cycles and Y address be not when matching, and described controller is read data from described memory cell array.

20. the semiconductor device on semiconductor chip comprises:

First kind of storer and second kind of storer, every kind comprises a storage array; A kind of sense amplifier piece that is connected to described memory cell array; A kind of line decoder that is connected to described memory cell array; A kind of column decoder that is connected to described sense amplifier piece; And a kind of control circuit that is used for controlling described memory cell array, described line decoder, described column decoder and described sense amplifier piece;

A kind of control module that is connected to described first and second storeies; And

A kind of processor that is connected to described control module;

When Input Address entered, wherein said control module was exported an identifying information according to Input Address to described processor.

Wherein said processor is preserved and is sent the relevant described identifying information in address;

Wherein said control module outputs to described processor with described identifying information with sense information according to the described address that enters; And

Wherein said processor is to detecting in company with identifying information and the match condition between the identifying information of this preservation that information receives together according to the address.

Images