CN113746437B - Operational amplifier and DC voltage level control method - Google Patents
Operational amplifier and DC voltage level control method Download PDFInfo
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- CN113746437B CN113746437B CN202010458412.5A CN202010458412A CN113746437B CN 113746437 B CN113746437 B CN 113746437B CN 202010458412 A CN202010458412 A CN 202010458412A CN 113746437 B CN113746437 B CN 113746437B
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Abstract
An operational amplifier includes a differential amplifier circuit and a common mode feedback circuit. The differential amplifier circuit includes a bias circuit, an amplifying circuit, and a load circuit. The bias circuit is used for generating a first operation voltage. The amplifying circuit is used for receiving a pair of input signals and generating a pair of output signals according to the input signals and a first operation voltage. The common mode feedback circuit is used for generating at least one common mode feedback voltage based on the common mode voltage of the associated output signals and the reference voltage. The at least one common mode feedback voltage is used for controlling the bias circuit and the load circuit to control the DC voltage level of the operational amplifier.
Description
Technical Field
The disclosure relates to an operational amplifier, and more particularly to an operational amplifier capable of locking a dc voltage level and a dc voltage level control method.
Background
With the development of circuit technology, various amplifiers have been developed and applied in many different applications. Amplifiers in some applications have the property of high gain (gain) and high bandwidth (bandwidth). Based on this condition, the dc voltage level of the amplifier in these applications needs to be effectively controlled (locked) to allow other related circuits to function properly.
Disclosure of Invention
Some embodiments of the invention relate to an operational amplifier. The operational amplifier includes a differential amplifier circuit and a common mode feedback circuit. The differential amplifier circuit includes a bias circuit, an amplifying circuit, and a load circuit. The bias circuit is used for generating a first operation voltage. The amplifying circuit is used for receiving a pair of input signals and generating a pair of output signals according to the input signals and a first operation voltage. The common mode feedback circuit is used for generating at least one common mode feedback voltage based on the common mode voltage of the associated output signals and the reference voltage. The at least one common mode feedback voltage is used for controlling the bias circuit and the load circuit to control the DC voltage level of the operational amplifier.
Some embodiments of the invention relate to a direct current voltage level control method. The direct current voltage level control method comprises the following steps: generating a pair of output signals according to a pair of input signals and a first operation voltage by a differential amplifier circuit in the operational amplifier; generating, by a common mode feedback circuit in the operational amplifier, at least one common mode feedback voltage based on a common mode voltage of the associated output signal and a reference voltage; and controlling the bias circuit and the load circuit in the differential amplifier circuit by at least one common mode feedback voltage to control the DC voltage level of the operational amplifier.
In summary, the operational amplifier and the DC voltage level control method of the present invention can effectively control the DC voltage level of the differential amplifier circuit in the operational amplifier.
Drawings
The foregoing and other objects, features, advantages and embodiments of the invention will be apparent from the following description in which:
FIG. 1 is a schematic diagram of an operational amplifier drawn according to some embodiments of the invention;
FIG. 2 is a circuit diagram of an operational amplifier drawn according to some embodiments of the invention;
FIG. 3 is a circuit diagram of an operational amplifier drawn according to some embodiments of the invention; and
Fig. 4 is a flow chart of a method of dc voltage level control, drawn in accordance with some embodiments of the invention.
Detailed Description
The term "coupled," as used herein, may also refer to "electrically coupled," and the term "connected" may also refer to "electrically connected. "coupled" and "connected" may also mean that two or more elements co-operate or interact with each other.
Reference is made to fig. 1. Fig. 1 is a schematic diagram of an operational amplifier 100 drawn according to some embodiments of the invention.
For the example of fig. 1, the operational amplifier 100 includes a differential amplifier circuit 120 and a common mode feedback circuit 140. The differential amplifier circuit 120 is coupled to the common mode feedback circuit 140. The common mode feedback circuit 140 may be used to control (lock in) the dc voltage level of the differential amplifier circuit 120.
In some embodiments, the operational amplifier 100 may be applied in an analog circuit. Since the amplifier of the analog circuit has high gain and high bandwidth, the dc voltage level of the differential amplifier circuit 120 needs to be effectively controlled to enable the analog circuit to operate normally. It should be noted that the present invention is not limited to application in analog circuits.
In some embodiments, the dc voltage level of the differential amplifier circuit 120 may be a predetermined level. In some embodiments, the direct voltage level of the differential amplifier circuit 120 may be an input common mode level. The foregoing is merely illustrative, and the present invention is not limited thereto.
The differential amplifier circuit 120 includes a bias circuit 122, an amplifying circuit 124, and a load circuit 126. The bias circuit 122 is coupled to the amplifying circuit 124. The amplifying circuit 124 is coupled to the load circuit 126 and the common mode feedback circuit 140. The common mode feedback circuit 140 is coupled to the bias circuit 122 and the load circuit 126.
The bias circuit 122 generates an operating voltage V1 according to the power voltage VDD. The amplifying circuit 124 receives a pair of input signals VIP and VIN, and generates a pair of output signals (e.g., a pair of output signals VON and VOP in fig. 2) according to the input signals VIP and VIN, the operating voltage V1, and the operating voltage V2. The amplifying circuit 124 generates and transmits a common mode voltage VOCM to the common mode feedback circuit 140 based on the pair of output signals. The load circuit 126 is coupled between the amplifying circuit 124 and the ground voltage VSS.
In addition to the common mode voltage VOCM from the amplification circuit 124, the common mode feedback circuit 140 also receives a reference voltage VCM. The common mode feedback circuit 140 generates at least one common mode feedback voltage VFB based on the common mode voltage VOCM and the reference voltage VCM. For example, the common mode feedback circuit 140 compares the common mode voltage VOCM with the reference voltage VCM, thereby generating at least one common mode feedback voltage VFB. In some embodiments, the at least one common mode feedback voltage VFB includes a common mode feedback voltage VFB1 and a common mode feedback voltage VFB2. The common mode feedback voltage VFB1 may control the load circuit 126 and the common mode feedback voltage VFB2 may control the bias circuit 122, thereby locking the dc voltage level of the differential amplifier circuit 120.
In some related art, the common mode feedback circuit performs common mode feedback control only on the bias circuit or only on the load circuit. In the related art, in which only the bias circuit is subjected to the common mode feedback control, if the transistors in the bias circuit are changed, the common mode feedback circuit cannot effectively control (lock) the dc voltage level of the differential amplifier circuit. Similarly, in the related art in which only the common mode feedback control is performed on the load circuit, if the transistors in the load circuit are changed, the common mode feedback circuit cannot effectively control (lock) the dc voltage level of the differential amplifier circuit.
Compared to the related art, the operational amplifier 100 of the present invention can perform the common mode feedback control on the bias circuit 122 and the load circuit 126 at the same time, so the present invention can effectively control (lock) the dc voltage level of the differential amplifier circuit 120.
Reference is made to fig. 2. Fig. 2 is a circuit diagram of an operational amplifier 200, drawn according to some embodiments of the invention. For the example of fig. 2, the operational amplifier 200 includes a differential amplifier circuit 220 and a common mode feedback circuit 240. The differential amplifier circuit 220 includes a bias circuit 222, an amplifying circuit 224, and a load circuit 226. The bias circuit 222 includes a current source IS1 and a transistor M1. The amplifying circuit 224 includes transistors M2-M5 and resistors R1-R2. The load circuit 226 includes a current source IS2 and a transistor M6. Common mode feedback circuit 240 includes current source IS3 and transistors M7-M12.
In some embodiments, the transistors M1-M3, M7-M8 and M11 are implemented as P-type transistors, and the transistors M4-M6, M9-M10 and M12 are implemented as N-type transistors, but the invention is not limited thereto.
The current source IS1 and the transistor M1 receive the power voltage VDD and are coupled to the node N1. The transistor M1 and the current source IS1 generate an operation voltage V1 at the node N1 according to the power voltage VDD. The transistor M1 is controlled by the common mode feedback voltage VFB 2. The transistor M2 and the transistor M4 are coupled in series between the node N1 and the node N2. The transistor M3 and the transistor M5 are coupled in series between the node N1 and the node N2. The operating voltage V2 is generated at the node N2. The current source IS2 and the transistor M6 are coupled to the node N2 and receive the ground voltage VSS. The transistor M6 is controlled by the common mode feedback voltage VFB 1. The control terminal (e.g., gate terminal) of the transistor M2 and the control terminal of the transistor M4 receive the input signal VIP. The control terminal of the transistor M3 receives the input signal VIN. Based on the operation of the differential amplifier circuit 220, the output signal VON is generated at the connection node N3 of the transistor M2 and the transistor M4, and the output signal VOP is generated at the connection node N4 of the transistor M3 and the transistor M5. Resistor R1 and resistor R2 are coupled in series between node N3 and node N4. The common mode voltage VOCM is generated at the connection node of resistor R1 and resistor R2.
The current source IS3 receives the power voltage VDD and IS coupled to the node N5. Transistor M7 is coupled in series with transistor M9. Transistor M7 is coupled to node N5 and node N6. The transistor M9 is coupled to the node N6 and receives the ground voltage VSS. Transistor M8 is coupled in series with transistor M10. The transistor M8 is coupled to the node N5 and the node N7. The transistor M10 is coupled to the node N7 and receives the ground voltage VSS. The control terminal of the transistor M9 and the control terminal of the transistor M6 are coupled to the node N6, and the common mode feedback voltage VFB1 is generated at the node N6. The control terminal of the transistor M10 and the control terminal of the transistor M12 are coupled to the node N7. The transistor M11 receives the power voltage VDD and is coupled to the node N8. The transistor M12 is coupled to the node N8 and receives the ground voltage VSS. The connection node N8 of the transistor M11 and the transistor M12 is coupled to the control terminal of the transistor M11 and the control terminal of the transistor M1. The common mode feedback voltage VFB2 is generated at node N8.
In operation, when the common mode voltage VOCM IS higher than the reference voltage VCM, more current generated by the current source IS3 flows to the transistor M7 and the transistor M9. Accordingly, the voltage value of the node N6 increases. Equivalently, the voltage value of the common mode feedback voltage VFB1 increases, so that the turn-on degree of the transistor M6 increases. In this case, the voltage value of the common-mode voltage VOCM in the amplifying circuit 224 can be pulled down through the transistors M5, M4 and M6, so that the voltage value of the common-mode voltage VOCM is reduced and changed closer to the reference voltage VCM, thereby controlling the dc voltage level of the differential amplifier circuit 220. In some embodiments, the voltage value of the common mode feedback voltage VFB1 is higher as the difference between the common mode voltage VOCM and the reference voltage VCM is greater.
On the other hand, when the common mode voltage VOCM IS higher than the reference voltage VCM, the current generated by the current source IS3 less flows to the transistor M8 and the transistor M10. Accordingly, the voltage value of the node N7 decreases, so that the turn-on degree of the transistor M12 becomes smaller. Accordingly, the voltage value of the node N8 increases. Equivalently, the voltage value of the common mode feedback voltage VFB2 increases, so that the turn-on degree of the transistor M1 becomes smaller. In this case, the voltage value of the common-mode voltage VOCM in the amplifying circuit 224 is less likely to pull up through the transistors M3, M2 and M1, so that the voltage value of the common-mode voltage VOCM is reduced and changed closer to the reference voltage VCM, thereby controlling the dc voltage level of the differential amplifier circuit 220. In some embodiments, the voltage value of the common mode feedback voltage VFB2 is higher as the difference between the common mode voltage VOCM and the reference voltage VCM is greater.
Conversely, when the common mode voltage VOCM IS lower than the reference voltage VCM, more current generated by the current source IS3 flows to the transistor M8 and the transistor M10, and less current flows to the transistor M7 and the transistor M9. Accordingly, the voltage value of the node N6 decreases and the voltage value of the node N7 increases, so that the turn-on degree of the transistor M6 becomes smaller and the turn-on degree of the transistor M12 becomes larger. Since the turn-on degree of the transistor M12 becomes large, the voltage value of the node N8 decreases. Since the voltage value of the node N6 decreases, the voltage value of the common mode feedback voltage VFB1 decreases. Meanwhile, since the voltage value of the node N8 is also reduced, the voltage value of the common mode feedback voltage VFB2 is also reduced. In this case, the degree of conduction of the transistor M6 becomes small and the degree of conduction of the transistor M1 becomes large. Accordingly, the voltage value of the common-mode voltage VOCM in the amplifying circuit 224 is less likely to pull down through the transistors M5, M4 and M6, and is more likely to pull up through the transistors M3, M2 and M1, so that the voltage value of the common-mode voltage VOCM rises and becomes closer to the reference voltage VCM, thereby controlling the dc voltage level of the differential amplifier circuit 220.
Through the above operation, if the transistor M6 in the load circuit 226 varies, the bias circuit 222 can be controlled by the common mode feedback voltage VFB2 to control the dc voltage level of the differential amplifier circuit 220. If the transistor M1 in the bias circuit 222 is changed, the load circuit 226 is still controlled by the common mode feedback voltage VFB1 to control the dc voltage level of the differential amplifier circuit 220.
Reference is made to fig. 3. Fig. 3 is a circuit diagram of an operational amplifier 300, drawn according to some embodiments of the invention. For the example of fig. 3, the operational amplifier 300 includes a differential amplifier circuit 320 and a common mode feedback circuit 340. The differential amplifier circuit 320 includes a bias circuit 322, an amplifying circuit 324, and a load circuit 326.
The main difference between the operational amplifier 300 of fig. 3 and the operational amplifier 200 of fig. 2 is that in fig. 3, the control terminal of the transistor M4 and the control terminal of the transistor M5 of the amplifying circuit 324 receive the bias voltage VB1, the control terminal of the transistor M9 and the control terminal of the transistor M10 of the common mode feedback circuit 340 receive the bias voltage VB2, and the control terminal of the transistor M1 of the bias circuit 322 is directly coupled to the node N7 of the common mode feedback circuit 340 to receive the common mode feedback voltage VFB2.
Similarly, if the transistor M6 in the load circuit 326 varies, the bias circuit 322 can still be controlled by the common mode feedback voltage VFB2 to control the dc voltage level of the differential amplifier circuit 320. If the transistor M1 in the bias circuit 322 is changed, the load circuit 326 is still controlled by the common mode feedback voltage VFB1 to control the DC voltage level of the differential amplifier circuit 320.
Refer to fig. 4. Fig. 4 is a flow chart of a dc voltage level control method 400, drawn in accordance with some embodiments of the invention. The direct current voltage level control method 400 includes operations S420, S440 and S460.
In some embodiments, the dc voltage level control method 400 is applied to the operational amplifier 100 of fig. 1, the operational amplifier 200 of fig. 2 or the operational amplifier 300 of fig. 3, but the invention is not limited thereto. For ease of understanding, the DC voltage level control method 400 will be discussed in conjunction with the operational amplifier 100 of FIG. 1.
In operation S420, a pair of output signals VON and VOP are generated by the differential amplifier circuit 120 in the operational amplifier 100 according to the pair of input signals VIP and VIN and the operating voltage V1. In some embodiments, the input signals VIP and VIN are a pair of differential input signals, and the output signals VON and VOP are a pair of differential output signals.
In operation S440, at least one common mode feedback voltage VFB is generated by the common mode feedback circuit 140 in the operational amplifier 100 based on the common mode voltage VOCM associated with the pair of output signals VON and VOP and the reference voltage VCM. In some embodiments, the at least one common mode feedback voltage VFB includes a common mode feedback voltage VFB1 and a common mode feedback voltage VFB2.
In operation S460, the bias circuit 122 and the load circuit 126 in the differential amplifier circuit 100 are controlled by the at least one common mode feedback voltage VFB to control the dc voltage level of the differential amplifier circuit 120. In some embodiments, the common mode feedback voltage VFB1 and the common mode feedback voltage VFB2 control the load circuit 126 and the bias circuit 122, respectively. Accordingly, if the transistors in the load circuit 126 are changed, the bias circuit 122 can be controlled by the common mode feedback voltage VFB2 to control the dc voltage level of the differential amplifier circuit 120. If the transistors in the bias circuit 122 are changed, the load circuit 126 can be controlled by the common mode feedback voltage VFB1 to control the dc voltage level of the differential amplifier circuit 120.
In summary, the operational amplifier and the DC voltage level control method of the present invention can effectively control the DC voltage level of the differential amplifier circuit in the operational amplifier.
Various functional elements and blocks are disclosed herein. It will be apparent to one of ordinary skill in the art that the functional blocks may be implemented by circuits, whether special purpose circuits or general purpose circuits operating under the control of one or more processors and encoded instructions, that generally include transistors or other circuit elements to control the operation of an electrical circuit in accordance with the functions and operations described herein. It is further understood that the specific structure and interconnection of circuit elements in general may be determined by a compiler (compiler), such as a Register Transfer Language (RTL) compiler. The register transfer language compiler operates on a script (script) that is quite similar to the assembly language code (assembly language code), compiling the script into a form for layout or making the final circuit.
While the present invention has been described with respect to the above embodiments, it should be understood that the invention is not limited thereto but may be variously modified and improved by those skilled in the art without departing from the spirit and scope of the present invention, and thus the scope of the present invention should be construed as defined by the appended claims.
Description of the reference numerals
100,200,300 Operational amplifier
120,220,320 Differential amplifier circuit
122,222,322 Bias circuit
124,224,324 Amplifying circuit
126,226,326 Load circuit
140,240,340: Common mode feedback circuit
400 Direct current voltage level control method
VDD power supply voltage
VSS ground voltage
V1, V2 operating Voltage
VIP, VIN input voltage
VOP, VON, output Voltage
VOCM common mode voltage
VCM reference voltage
VFB, VFB1, VFB2 common mode feedback voltage
IS1, IS2, IS3 current source
M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12: transistors
R1, R2 resistance
N1, N2, N3, N4, N5, N6, N7, N8: nodes
VB1, VB2 bias
S420, S440, S460 operation
Claims (10)
1. An operational amplifier, comprising:
a differential amplifier circuit comprising:
A bias circuit for generating a first operating voltage;
The amplifying circuit is used for receiving a pair of input signals and generating a pair of output signals according to the pair of input signals and the first operation voltage; and
A load circuit coupled to the amplifying circuit; and
And a common mode feedback circuit for generating at least one common mode feedback voltage based on a common mode voltage associated with the pair of output signals and a reference voltage, wherein the at least one common mode feedback voltage is used for controlling the bias circuit and the load circuit to control the DC voltage level of the differential amplifier circuit.
2. The operational amplifier of claim 1, wherein the common mode feedback circuit is configured to receive the common mode voltage and compare the common mode voltage to the reference voltage to generate the at least one common mode feedback voltage.
3. The operational amplifier of claim 1, wherein the bias circuit comprises:
A first current source; and
A first transistor coupled to the first current source at a first node, wherein the first transistor and the first current source are configured to generate the first operating voltage at the first node according to a supply voltage,
Wherein the first transistor is controlled by a first common mode feedback voltage of the at least one common mode feedback voltage.
4. The operational amplifier of claim 3, wherein the load circuit comprises:
A second current source; and
A second transistor coupled to the second current source and configured to receive a ground voltage, wherein a second operating voltage is generated at the second node, wherein the amplifying circuit generates the pair of output signals according to the pair of input signals, the first operating voltage and the second operating voltage,
Wherein the second transistor is controlled by a second common mode feedback voltage of the at least one common mode feedback voltage.
5. The operational amplifier of claim 4, wherein the voltage value of the first common mode feedback voltage or the second common mode feedback voltage is higher as the difference between the common mode voltage and the reference voltage is larger.
6. The operational amplifier of claim 4, wherein the first transistor is of a different form than the second transistor.
7. The operational amplifier of claim 6, wherein the first transistor is a P-type transistor and the second transistor is an N-type transistor.
8. The operational amplifier of claim 1, wherein the load circuit comprises:
A current source; and
A transistor coupled to a node of the current source and configured to receive a ground voltage, wherein a second operating voltage is generated at the node, wherein the amplifying circuit generates the pair of output signals according to the pair of input signals, the first operating voltage and the second operating voltage,
Wherein the transistor is controlled by the at least one common mode feedback voltage.
9. A method of dc voltage level control, comprising:
Generating a pair of output signals according to a pair of input signals and a first operation voltage by a differential amplifier circuit in the operational amplifier;
Generating, by a common mode feedback circuit in the operational amplifier, at least one common mode feedback voltage based on a common mode voltage associated with the pair of output signals and a reference voltage; and
The bias circuit and the load circuit in the differential amplifier circuit are controlled by the at least one common mode feedback voltage to control the DC voltage level of the differential amplifier circuit.
10. The direct current voltage level control method as claimed in claim 9, further comprising:
The common mode voltage is received by the common mode feedback circuit and compared to the reference voltage to generate the at least one common mode feedback voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010458412.5A CN113746437B (en) | 2020-05-27 | Operational amplifier and DC voltage level control method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010458412.5A CN113746437B (en) | 2020-05-27 | Operational amplifier and DC voltage level control method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113746437A CN113746437A (en) | 2021-12-03 |
| CN113746437B true CN113746437B (en) | 2024-07-16 |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1452314A (en) * | 2002-04-12 | 2003-10-29 | 旺宏电子股份有限公司 | Automatic track feedback circuit and high-speed A/D converter therewith |
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1452314A (en) * | 2002-04-12 | 2003-10-29 | 旺宏电子股份有限公司 | Automatic track feedback circuit and high-speed A/D converter therewith |
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