CN113745053A

CN113745053A - Interlocking switching circuit and signal system

Info

Publication number: CN113745053A
Application number: CN202010464338.8A
Authority: CN
Inventors: 智笑闪
Original assignee: BYD Co Ltd
Current assignee: BYD Co Ltd
Priority date: 2020-05-27
Filing date: 2020-05-27
Publication date: 2021-12-03
Anticipated expiration: 2040-05-27
Also published as: CN113745053B

Abstract

The application provides an interlocking switching circuit, which is arranged between a first logic operation module and a second logic operation module and comprises a first interlocking unit and a second interlocking unit, wherein the input end of the first interlocking unit is connected with the output end of the first logic operation module, and the output end of the first interlocking unit is connected with the enabling end of the second interlocking unit and the input end of the first logic operation module; the input end of the second interlocking unit is connected with the output end of the second logic operation module, and the output end of the second interlocking unit is connected with the enabling end of the first interlocking unit and the input end of the second logic operation module. Implement this application, can carry out the interlocking fast and switch, can also reduce the volume of interlocking switching circuit effectively to realize the lightweight of interlocking switching circuit.

Description

Interlocking switching circuit and signal system

Technical Field

The present application relates to the field of communications circuit technologies, and in particular, to an interlock switching circuit and a signal system.

Background

The interlocking is that two or more than two loops are mutually restricted and mutually controlled, and the interlocking circuit can be applied to a responder control circuit, a positive and negative rotation control circuit of a motor, an interlocking control system of 2 by 2 and 2 in a rail transit system and the like.

In the prior art, an interlocking switching circuit is realized through an interlocking relay, the realization principle is that a coil 1 and a coil 2 generate a magnetic field through current to control the on-off of a contact 1 and a contact 2 in the relay, the sequence of the output voltages of a first logic operation module 10 and a second logic operation module 11 is confirmed according to the on-off state of the contact 1 and the contact 2, the logic operation module which outputs the voltage firstly is confirmed to be a main logic operation module and the other one is a standby logic operation module based on the sequence of the two logic operation modules, when the main logic operation module and the standby logic operation module need to be switched, for example, the first logic operation module 10 is switched from the main logic operation module to the standby logic operation module, the second logic operation module 11 is switched from the standby logic operation module to the main logic operation module, the contact 1 is switched from an open state to a closed state, and the contact 2 is switched from the closed state to the open state, therefore, the interlocking switching of the main and standby logical operation modules in the existing scheme is completed based on the mechanical structure of the contact in the interlocking relay, so that the response time of the interlocking switching is long.

Disclosure of Invention

Based on the above problem, the present application provides an interlock switching circuit, which can perform interlock switching quickly, and can also effectively reduce the volume of the interlock switching circuit, thereby realizing the light weight of the interlock switching circuit.

In one aspect, an embodiment of the present application provides an interlock switching circuit, where the interlock switching circuit is disposed between a first logic operation module and a second logic operation module, the interlock switching circuit includes a first interlock unit and a second interlock unit, and both the first interlock unit and the second interlock unit include an input end, an output end, and an enable end, where:

the input end of the first interlocking unit is connected with the output end of the first logic operation module, and the output end of the first interlocking unit is connected with the enabling end of the second interlocking unit and the input end of the first logic operation module; the first interlocking unit is used for outputting a first voltage signal according to a signal received by the self enable end and a signal of the self input end; the first logic operation module is used for determining a first identity of the first logic operation module according to the first voltage signal and carrying an identity of the first identity when information is sent;

the input end of the second interlocking unit is connected with the output end of the second logic operation module, and the output end of the second interlocking unit is connected with the enabling end of the first interlocking unit and the input end of the second logic operation module; the second interlocking unit is used for outputting a second voltage signal according to the signal received by the self enable end and the signal of the self input end; and the second logic operation module is used for determining a second identity of the second logic operation module according to the second voltage signal and carrying an identity of the second identity when sending information.

In a possible implementation manner, the interlock switching circuit further includes a first read-back unit and a second read-back unit, and the first read-back unit and the second read-back unit each include a first output end;

the output end of the first interlocking unit is connected with the enabling end of the second interlocking unit and the input end of the first logic operation module, and the output end of the first interlocking unit comprises:

the output end of the first interlocking unit is connected with the input end of the first read-back unit, the first output end of the first read-back unit is connected with the enable end of the second interlocking unit and the input end of the first logic operation module, the first output end of the first read-back unit outputs a first read-back signal according to the first voltage signal, and the first logic operation module is further used for determining the first identity according to the first read-back signal;

the output end of the second interlocking unit is connected with the enabling end of the first interlocking unit and the input end of the second logic operation module, and the output end of the second interlocking unit comprises:

the output end of the second interlocking unit is connected with the input end of the second read-back unit, the first output end of the second read-back unit is connected with the enable end of the first interlocking unit and the input end of the second logic operation module, the first output end of the second read-back unit outputs a second read-back signal according to the second voltage signal, and the second logic operation module is further used for determining the second identity according to the second read-back signal.

In one possible embodiment, the first logical operation module includes a first processor and a second processor;

the interlock switching circuit further comprises a first switching drive unit, wherein the first switching drive unit comprises a first input end and a second input end;

the input end of the first interlocking unit is connected with the output end of the first logic operation module, and the first interlocking unit comprises:

the input end of the first interlocking unit is connected with the output end of the first switching driving unit, the first input end of the first switching driving unit is connected with the output end of the first processor, the second input end of the first switching driving unit is connected with the output end of the second processor, and the first processor and the second processor are used for carrying out logical operation on a target event and sending a logical operation result to the first switching driving unit at the first time; the first switching driving unit is used for controlling the first interlocking unit to output the first voltage signal when the logic operation results of the first processor and the second processor on the target event are consistent.

Further, the second logical operation module includes a third processor and a fourth processor;

the interlock switching circuit further comprises a second switching drive unit, wherein the second switching drive unit comprises a third input end and a fourth input end;

the input end of the second interlocking unit is connected with the output end of the second logic operation module, and the second interlocking unit comprises:

the input end of the second interlock unit is connected with the output end of the second switching drive unit, the third input end of the second switching drive unit is connected with the output end of the third processor, the fourth input end of the second switching drive unit is connected with the output end of the fourth processor, the third processor and the fourth processor are used for carrying out logical operation on the target event and sending the result of the logical operation to the second switching drive unit at a second time, wherein the second time is longer than the first time; the second switching driving unit is configured to control the second interlock unit to output the second voltage signal when the first interlock unit does not output the first voltage signal and the third processor and the fourth processor have the same logical operation result on the target event.

Optionally, the first read-back unit and the second read-back unit further include a second output end;

a second output end of the first read-back unit is connected with an input end of the first logic operation module, the second output end of the first read-back unit outputs a third read-back signal according to the first voltage signal, the first read-back signal and the third read-back signal are mutually inverse, and the first logic operation module is further used for determining the first identity according to the first read-back signal and the second read-back signal;

the second output end of the second read-back unit is connected with the input end of the second logic operation module, the second output end of the second read-back unit outputs a fourth read-back signal according to the second voltage signal, the second read-back signal and the fourth read-back signal are mutually opposite, and the second logic operation module is further used for determining the second identity according to the second read-back signal and the fourth read-back signal.

In one possible implementation, the first interlock unit includes a first logic gate optical coupler, and the second interlock unit includes a second logic gate optical coupler.

Optionally, the first read-back unit includes a first phototransistor; the second read-back unit includes a second phototransistor.

In a possible implementation manner, the first switching driving unit includes a first optocoupler relay and a second optocoupler relay, an input end of the first optocoupler relay is the first input end, and an input end of the second optocoupler relay is the second input end.

In another possible implementation manner, the second switching driving unit includes a third optical coupling relay and a fourth optical coupling relay, an input end of the third optical coupling relay is the third input end, and an input end of the fourth optical coupling relay is the fourth input end.

On one hand, the embodiment of the present application further provides a signaling system, where the signaling system includes a first logic operation module, a second logic operation module, and any one of the interlock switching circuits described above, and the signaling system is used for rail transit or automobiles.

By implementing the method and the device, the identity of the logic operation module is confirmed through the transmission of the voltage signal, the interlocking switching can be rapidly carried out, the size of the interlocking switching circuit can be effectively reduced, and the light weight of the interlocking switching circuit is realized.

Drawings

FIG. 1 is a prior art interlock relay;

fig. 2 is a block diagram of an interlock switching circuit according to an embodiment of the present disclosure;

fig. 3 is a block diagram of another interlock switching circuit according to an embodiment of the present disclosure;

fig. 4 is a block diagram of a structure of another interlock switching circuit provided in the embodiment of the present application;

fig. 5 is a schematic circuit diagram of an interlock switching circuit according to an embodiment of the present disclosure;

fig. 6 is a system architecture diagram of a signaling system according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The following describes embodiments of the present application in further detail with reference to the accompanying drawings.

Referring to fig. 2, fig. 2 is a block diagram of an interlock switching circuit according to an embodiment of the present disclosure. As shown IN fig. 2, the interlock switching circuit 22 is disposed between the first logic operation module 20 and the second logic operation module 21, the interlock switching circuit 22 includes a first interlock unit 220 and a second interlock unit 221, and each of the first interlock unit 220 and the second interlock unit 221 includes an input terminal IN, an output terminal OUT, and an enable terminal EN, where:

an input end IN of the first interlock unit 220 is connected to an output end of the first logic operation module 20, and an output end OUT of the first interlock unit 220 is connected to an enable end EN of the second interlock unit 221 and an input end of the first logic operation module 20; the first interlock unit 220 is configured to output a first voltage signal according to a signal received by the self enable terminal EN and a signal of the self input terminal IN; the first logic operation module 20 is configured to determine a first identity of the first logic operation module according to the first voltage signal, and carry an identity of the first identity when sending information;

an input end IN of the second interlock unit 221 is connected to an output end of the second logic operation module 21, and an output end OUT of the second interlock unit 221 is connected to an enable end EN of the first interlock unit 220 and an input end of the second logic operation module 21; the second interlock unit 221 is configured to output a second voltage signal according to a signal received by the self enable terminal EN and a signal of the self input terminal IN; the second logic operation module 21 is configured to determine a second identity of the second logic operation module according to the second voltage signal, and carry an identity of the second identity when sending information.

Illustratively, the first interlock unit 220 includes a first logic gate optical coupler, and the second interlock unit 221 includes a second logic gate optical coupler, which can implement an interlock switching function, and can effectively isolate the input and the output of the logic operation module, thereby improving the accuracy of the interlock switching. Optionally, the model of the first logic gate optical coupler and/or the second logic gate optical coupler may be 6N 137. In the embodiment, the electronic components are adopted to realize the interlocking switching logic, so that the volume of the interlocking switching circuit can be effectively reduced, and the light weight of the interlocking switching circuit is realized.

Optionally, at least one register is disposed in the first logic operation module 20, the first logic operation module 20 executes a preset self-check program, where the self-check program includes reading a value of a certain number of bits in the at least one register, for example, the register is an 8-bit register, and reading a value of a 7 th bit in the register, for example, the value of the 7 th bit of the register represents an operation state of the logic operation module where the register is located, and if the value is 1, the operation is normal, and if the value is 0, the operation is abnormal. The first logic operation module 20 determines a signal output to the first interlock unit 220 according to the read value of the register, for example, if the first logic operation module 20 reads that the value of the register is 1, and detects that the first logic operation module operates normally, it outputs a high level signal to the first interlock unit 220, otherwise, it outputs a low level signal; similarly, at least one register is arranged in the second logic operation module 21, the second logic operation module 21 executes the preset self-checking program, and outputs a high level signal to the second interlock unit 221 when it is determined that the second logic operation module operates normally according to the read value of the register, otherwise outputs a low level signal. It can be understood that the first logic operation module 20 and the second logic operation module 21 output a low level by default, and the interlock switching circuit 22 switches the first logic operation module 20 or the second logic operation module 21 to be a main logic operation module according to the sequence of the high levels output by the first logic operation module 20 and the second logic operation module 21.

The operation principle of the interlock switching circuit 22 is as follows:

taking the example that the first logic operation module 20 outputs a high level earlier than the second logic operation module 21, the first logic operation module 20 outputs a high level earlier, before the second logic operation module 21 outputs a high level, the input terminal IN of the first interlock unit 220 is at a high level, and the enable terminal EN is high level as default, which is the same as the output terminal OUT of the second interlock unit 221, and the output terminal OUT of the first interlock unit 220 is at a low level, taking the example that the enable terminals EN and the output terminal OUT of the first interlock unit 220 and the second interlock unit 221 are connected by an inverter; the enable terminal EN of the second interlock unit 221 is at a low level, and at this time, even if the output of the second logic operation module 21 is at a high level, the input terminal IN of the second interlock unit 221 is at a high level, and the output terminal OUT of the second interlock unit 221 is still at a high level; it can be understood that, the first logic operation module 20 outputs a high level to the first interlock unit 220 first, and controls the enable terminal EN of the second interlock unit 221 to be a low level, so that, when the first logic operation module 20 outputs a high level first, the first interlock unit 220 outputs a low level signal, and the second interlock unit 221 outputs a high level signal; similarly, for example, when the second logic operation module 21 outputs a high level earlier than the first logic operation module 20, the second logic operation module 21 outputs a high level earlier, before the first logic operation module 21 outputs a high level, the input end IN of the second interlock unit 221 is at a high level, the enable end EN is the same as the output end OUT of the first interlock unit 220 and is at a high level by default, and the output end OUT of the second interlock unit 221 is at a low level; the enable terminal EN of the first interlock unit 220 is at a low level, and at this time, even if the input terminal IN of the output terminal OUT of the first logic operation module 220 is at a high level, the output terminal OUT of the first interlock unit 220 is still at a high level, that is, the second logic operation module 21 outputs a high level to the second interlock unit 221 first, and the enable terminal of the first interlock unit 220 is controlled to be at a low level, so that the second interlock unit 221 outputs a low level signal and the first interlock unit 220 outputs a high level signal under the condition that the second logic operation module 21 outputs a high level first. The first logic operation module 20 determines that it is higher than the second logic operation module 21 and outputs a high level according to a first voltage signal output by the first interlock unit 220, for example, the first voltage signal is a high level signal, the first identity is a standby logic operation module, and for example, the identity of the standby logic operation module is a; if the first voltage signal is a low level signal, it is determined that the first voltage signal is higher than the second logic operation module 21, and the first identity is a main logic operation module, for example, the identity of the main logic operation module is B. Similarly, the second logic operation module 21 determines that it is higher than the first logic operation module 20 and outputs a higher level according to a second voltage signal output by the second interlock unit 221, for example, the second voltage signal is a high level signal, the second identity is a standby logic operation module, and if the second voltage signal is a low level signal, it determines that it is higher than the first logic operation module 20 and outputs a higher level, and the second identity is a main logic operation module.

In the embodiment, the identity of the logic operation module is confirmed through the voltage signal, the interlocking switching can be performed quickly, the size of the interlocking switching circuit can be effectively reduced, and the light weight of the interlocking switching circuit is realized.

In the embodiment described above with reference to fig. 2, in order to improve the accuracy of the logic operation module in confirming the active/standby logic operation module, the embodiment of the present application further provides another interlock switching circuit, and referring to fig. 3, fig. 3 is a block diagram of a structure of another interlock switching circuit provided in the embodiment of the present application. As shown in fig. 3: the interlock switching circuit 32 is disposed between the first logic operation module 30 and the second logic operation module 31, the interlock switching circuit 32 includes a first interlock unit 320 and a second interlock unit 321, each of the first interlock unit 320 and the second interlock unit 321 includes an input end IN, an output end OUT, and an enable end EN, the interlock switching circuit 32 further includes a first read-back unit 322 and a second read-back unit 323, wherein:

an input end IN of the first interlock unit 320 is connected to an output end of the first logic operation module 30, an output end OUT of the first interlock unit 320 is connected to an input end of the first read-back unit 322, a first output end 1 of the first read-back unit 322 is connected to an enable end EN of the second interlock unit 321 and an input end of the first logic operation module 30, a first output end 1 of the first read-back unit 322 outputs a first read-back signal according to the first voltage signal, and the first logic operation module 30 is further configured to determine the first identity according to the first read-back signal;

the input end IN of the second interlock unit 321 is connected to the output end of the second logic operation module 31, the output end of the second interlock unit 321 is connected to the input end of the second read-back unit 323, the first output end 1 of the second read-back unit 321 is connected to the enable end EN of the first interlock unit 320 and the input end of the second logic operation module 31, the first output end 1 of the second read-back unit 323 outputs a second read-back signal according to the second voltage signal, and the second logic operation module 31 is further configured to determine the second identity according to the second read-back signal. In the embodiment, the interlock unit is isolated from the logic operation module by the read-back unit, and the logic operation module confirms the main and standby logic operation modules according to the read-back signal, so that the accuracy of interlock switching can be improved.

Optionally, the first read-back unit includes a first phototransistor; the second read-back unit includes a second phototransistor. Optionally, the model of the first phototransistor and/or the second phototransistor may be MOCD213R 2M.

The operation principle of the interlock switching circuit 32 is as follows:

taking the first logic operation module 30 outputting a high level earlier than the second logic operation module 31, the first logic operation module 30 outputting a high level earlier, before the second logic operation module 31 outputting a high level, the input terminal IN of the first interlock unit 320 being a high level, the enable terminal EN being the same as the output terminal OUT of the second interlock unit 321, and defaulting to a high level, taking the enable terminal EN and the output terminal OUT of the first interlock unit 320 and the second interlock unit 321 being connected by an inverter as an example, the output terminal OUT of the first interlock unit 320 being a low level, that is, the input terminal of the first read-back unit 322 being a low level, taking the first read-back unit 322 being driven at a high level and outputting a low level by default when not being driven as an example, the first output terminal 1 of the first read-back unit 322 being a low level, that is the first read-back signal being a low level, the enable terminal EN of the second interlock unit 321 is at a low level, and at this time, even if the output of the second logic operation module 31 is at a high level, so that the input terminal IN of the second interlock unit 321 is at a high level, the output terminal OUT of the second interlock unit 321 is still at a high level; it can be understood that the first logic operation module 30 outputs a high level to the first interlock unit 320 first, so that the first output terminal of the first read-back unit outputs a low level, and the enable terminal EN of the second interlock unit 321 is controlled to be a low level, so that in the case that the first logic operation module 30 outputs a high level first, the first read-back unit 322 outputs a low level signal, and the second read-back unit 323 outputs a high level signal; similarly, for example, when the second logic operation module 31 outputs a high level earlier than the first logic operation module 30, the second logic operation module 31 outputs a high level earlier, before the first logic operation module 31 outputs a high level, the input terminal IN of the second interlock unit 321 is a high level, and the enable terminal EN is defaulted to be a high level as the same as the output terminal of the first interlock unit 320, the output terminal OUT of the second interlock unit 321 is a low level, the input terminal of the second read-back unit 323 is a low level, for example, when the second read-back unit 323 is driven at a high level and is not driven at a low level, the first output terminal 1 of the second read-back unit 323 is a low level, that is, when the second read-back signal is a low level, the enable terminal EN of the first interlock unit 320 is a low level, even if the first logic operation module 31 outputs a high level, the input end IN of the first interlock unit 321 is at a high level, and the output end OUT of the first interlock unit 321 is still at a high level, so that the first read-back signal is at a high level. The first logic operation module 30 determines that it is higher than the second logic operation module 31 and then outputs a high level according to a first read-back signal output by the first read-back unit 322, for example, the first read-back signal is a high level signal, the first identity is a standby logic operation module, and for example, the identity of the standby logic operation module is a; if the first read-back signal is a low level signal, it is determined that the first read-back signal is higher in level than the second logic operation module 31, where the first identity is a primary logic operation module, and for example, the identity of the primary logic operation module is B. Similarly, the second logic operation module 31 determines that it is higher than the first logic operation module 30 and then outputs a higher level according to the second read-back signal output by the second read-back unit 323, for example, the second read-back signal is a high level signal, the second identity is a standby logic operation module, and if the second read-back signal is a low level signal, it determines that it is higher than the first logic operation module 30 and outputs a higher level signal, and the second identity is a main logic operation module.

By implementing the embodiment, the first read-back unit and the second read-back unit are added, so that the interference of the interlocking unit on the logic operation module unit is isolated, and the logic operation module can more accurately confirm the identity of the logic operation module.

Further, the first read-back unit 322 and the second read-back unit 323 further include a second output terminal;

the second output end 2 of the first read-back unit 322 is connected to the input end of the first logic operation module 30, the second output end 2 of the first read-back unit 322 outputs a third read-back signal according to the first voltage signal, the first read-back signal and the third read-back signal are opposite, and the first logic operation module 30 is further configured to determine the first identity according to the first read-back signal and the second read-back signal. For example, when the first logic operation module 30 is a master logic operation module, the first read-back signal output by the first read-back unit 322 is at a low level, and the third read-back signal is at a high level, and when the first logic operation module 30 is a slave logic operation module, the first read-back signal output by the first read-back unit 322 is at a high level, and the third read-back signal is at a low level.

The second output end 2 of the second read-back unit 323 is connected to the input end of the second logic operation module, the second output end 2 of the second read-back unit 323 outputs a fourth read-back signal according to the second voltage signal, the second read-back signal and the fourth read-back signal are opposite, and the second logic operation module is further configured to determine the second identity according to the second read-back signal and the fourth read-back signal. For example, when the second logic operation module 31 is a main logic operation module, the second read-back signal output by the second read-back unit 323 is at a low level, and the fourth read-back signal is at a high level, and when the second logic operation module 31 is a standby logic operation module, the second read-back signal output by the second read-back unit 323 is at a high level, the fourth read-back signal is at a low level. By implementing the embodiment, one more read-back signal is output in the first read-back unit and the second read-back unit, so that the first logic operation module and the second logic operation module can respectively judge the identities thereof according to the two read-back signals, and the obtained result is confirmed to be more accurate.

In a possible embodiment, the output signal of the logic operation module is determined by the logic operation results of the multiple processors, and the application takes the example that the output signal of the logic operation module is determined by the logic operation results of the two processors as an example for description, and refer to fig. 4, where fig. 4 is a structural block diagram of another interlock switching circuit provided in the embodiment of the application. As shown in fig. 4, the interlock switching circuit 42 is disposed between the first logic operation module 40 and the second logic operation module 41, the interlock switching circuit 42 includes a first interlock unit 420, a second interlock unit 421, a first read-back unit 422, and a second read-back unit 423, the first logic operation module 40 includes a first processor 400 and a second processor 401, the interlock switching circuit 42 further includes a first switching driving unit 424, the first switching driving unit 424 includes a first input terminal and a second input terminal, wherein:

the input end IN of the first interlock unit 420 is connected to the output end of the first switch driving unit 424, the first input end of the first switch driving unit 424 is connected to the output end of the first processor 400, the second input end of the first switch driving unit 424 is connected to the output end of the second processor 401, and the first processor 400 and the second processor 401 are configured to perform a logic operation on a target event and send a result of the logic operation to the first switch driving unit 424 at a first time; the first switching driving unit 424 is configured to control the first interlock unit 420 to output the first voltage signal when the logic operation results of the first processor 400 and the second processor 401 are consistent. For example, the programs executed in the first processor 400 and the second processor 401 may be consistent, for example, the target event is a result of calculating 1+1, and if the result of the calculation is 2, a high level is output; if the calculation result is not 2, outputting a low level. The first processor 400 and the second processor 401 respectively output a high level or a low level to the first switch driving unit 424, and when the output results of the first processor 400 and the second processor 401 are consistent, the first switch driving unit 424 outputs a high level to the first interlock unit 420, and controls the first interlock unit 420 to output the first voltage signal, i.e., a low level signal.

Optionally, the first switching driving unit 424 includes a first optocoupler relay and a second optocoupler relay, an input of the first optocoupler relay is the first input, and an input of the second optocoupler relay is the second input. In a possible implementation manner, the first processor 400 and the second processor 401 are not disposed on the same circuit board, so that the first processor 400 and the second processor 401 are not grounded, and the first switching driving unit 424 uses a first optical coupling relay and a second optical coupling relay, so that the grounds of the first processor 400 and the second processor 401 can be placed in the same ground, and it is ensured that the first switching driving unit 420 is accurately controlled.

By implementing the embodiment, the application range of the interlock switching circuit provided by the embodiment of the present application can be expanded, so that the interlock switching circuit provided by the embodiment of the present application can be applied to a logic operation module composed of a plurality of processors, for example, can be applied to a 2-by-2-to-2 architecture in a rail transit signal system.

Further, the second logical operation module 41 includes a third processor 410 and a fourth processor 411;

the interlock switching circuit 42 further comprises a second switching driving unit 425, the second switching driving unit 425 comprising a third input terminal and a fourth input terminal;

an input end IN of the second interlock unit 421 is connected to an output end of the second switch driving unit 425, a third input end of the second switch driving unit 425 is connected to the third processor 410, a fourth input end of the second switch driving unit 425 is connected to the fourth processor 411, the third processor 410 and the fourth processor 411 are configured to perform a logical operation on the target event, and send a result of the logical operation to the second switch driving unit 425 at a second time, where the second time is greater than the first time; the second switching driving unit 425 is configured to control the second interlock unit 421 to output the second voltage signal when the first interlock unit 420 does not output the first voltage signal and the logic operation results of the third processor 410 and the fourth processor 411 on the target event are consistent. Specifically, the first logic operation module 40 does not output the first voltage signal, which represents that the first logic operation module 40 fails to rob the main logic operation module, and the second interlock unit 421 switches the second logic operation module 41 to the main logic operation module by outputting a low level, similarly, the programs executed in the third processor 410 and the fourth processor 411 may be consistent, for example, the target event is a result of calculating 1+2, and if the calculation result is 3, a high level is output; if the calculation result is not 3, a low level is output. The third processor 410 and the second processor 411 respectively output a high level or a low level to the second switching driving unit 425, and when the output results of the third processor 410 and the fourth processor 411 are consistent, the second switching driving unit 425 outputs a high level to the second interlock unit 421, and controls the second interlock unit 421 to output the second voltage signal, that is, a low level signal.

Optionally, the second switching driving unit 425 includes a third optical coupling relay and a fourth optical coupling relay, an input end of the third optical coupling relay is the third input end, and an input end of the fourth optical coupling relay is the fourth input end. In a possible implementation manner, the third processor 410 and the fourth processor 411 are not disposed on the same circuit board, so that the third processor 410 and the fourth processor 411 are not grounded, and the second switching driving unit 425 uses a third optical coupling relay and a fourth optical coupling relay, so that the grounds of the third processor 410 and the fourth processor 411 can be placed in the same ground, thereby ensuring that the second switching driving unit 425 is accurately controlled.

By implementing the implementation, under the condition that one logic operation module is not matched with the main logic operation module, the interlocking switching circuit can switch the other logic operation module into the main logic operation module through the transmission of voltage signals and does not involve the switching of a mechanical structure, so that the response time of interlocking switching is greatly shortened.

A detailed description is given below of an interlock switching circuit provided in the present application with reference to specific components, and referring to fig. 5, fig. 5 is a schematic circuit diagram of an interlock switching circuit provided in an embodiment of the present application. First, it is noted that the interlock switching circuit is disposed between the first logic operation module and the second logic operation module, and the present application exemplarily illustrates that the first logic operation module includes the first processor CPU1 and the second processor CPU2, the second logic operation module includes the third processor CPU3 and the fourth processor CPU4, as shown in fig. 5, the interlock switching circuit includes the first interlock unit 500 and the second interlock unit 501, the first interlock unit 500 includes the first logic gate optical coupler U1, the second interlock unit 501 includes the second logic gate optical coupler U2, and the specific model is 6N137, for example, it should be noted that the present application may use other logic gate optical couplers having an enable pin instead of the specific components listed in the present application, and is not limited to the specific components listed in the present application. Specifically, the method comprises the following steps:

the input terminals of the first interlock unit 500 are the 2 nd PIN and the 3 rd PIN of the first logic gate optical coupler U1, and the nth PIN is referred to as PIN n hereinafter, for example, the 2 nd PIN is referred to as PIN 2. The output terminal of the first interlock unit 500 is PIN6 of the first logic gate optical coupler U1, and the enable terminal of the first interlock unit 500 is PIN7 of the first logic gate optical coupler U1; similarly, the input terminals of the second interlock unit 501 are PIN2 and PIN3 of the second logic gate optical coupler U2, the output terminal of the second interlock unit 501 is PIN6 of the second logic gate optical coupler U2, and the enable terminal of the second interlock unit 501 is PIN7 of the second logic gate optical coupler U2. The PIN2 of the first logic gate optical coupler U1 is connected to the output terminal of the CPU1 included in the first logic operation module, optionally, the output terminal of the CPU1 may be connected to the PIN2 of the first logic gate optical coupler U1 through a first resistor R1, and the first resistor R1 is used to prevent the first logic gate optical coupler U1 from being damaged by overcurrent. The PIN3 of the first logic gate optocoupler U1 is connected to the output of the CPU 2. The PIN6 of the first logic gate optical coupler U1 is connected to the PIN7 of the second logic gate optical coupler U2 and the input end of the first logic operation module, for example, the PIN6 of the first logic gate optical coupler U1 is connected to the input end of the CPU1, the PIN2 and the PIN3 of the second logic gate optical coupler U2 are connected to the output ends of the CPU3 and the CPU4 included in the second logic operation module, optionally, the output end of the CPU3 is connected to the PIN2 of the second logic gate optical coupler U2 through a third resistor R3, and the second resistor R2 is used to prevent the second logic gate optical coupler U2 from being damaged by overcurrent. The PIN6 of the second logic gate optical coupler U2 is connected to the PIN7 of the first logic gate optical coupler U1 and to an input of the second logic operation module, and the PIN6 of the second logic gate optical coupler U2 is illustratively connected to an input of the CPU 3. Optionally, PIN 8 of the first logic gate optical coupler U1 is connected to PIN6 of the first logic gate optical coupler U1 through a second resistor R2, PIN 8 of the first logic gate optical coupler U1 is also connected to the ground of CH3_ GND through a first capacitor C1, so as to filter the ripple of the power supply CH3_5V, and further, the first capacitor C1 is disposed near PIN 8 of the first logic gate optical coupler U1. The PIN6 of the first logic gate optical coupler U1 is connected to CH3_ GND through a second capacitor C2, and the second capacitor C2 is used to stabilize the output of the first logic gate optical coupler U1. Similarly, PIN 8 of the second logic gate optical coupler U2 is connected to PIN6 of the second logic gate optical coupler U2 through a fourth resistor R4, PIN 8 of the second logic gate optical coupler U2 is also connected to the ground of CH1_ GND through a third capacitor C3, so as to filter the ripple of the power supply CH1_5V, and further, the third capacitor C3 is disposed near PIN 8 of the second logic gate optical coupler U2. The PIN6 of the second logic gate optical coupler U2 is connected to CH1_ GND through a fourth capacitor C4, and the fourth capacitor C4 is used for stabilizing the output of the second logic gate optical coupler U2.

The working principle of the interlocking switching circuit is as follows:

taking the example that the CPU1 and the CPU2 included in the first logic operation module output the levels that turn on the diodes at the PIN2 and the PIN3 of the first logic gate optical coupler U1, it can be understood that the leds are disposed in the PIN2 and the PIN3 of the first logic gate optical coupler U1, and whether the leds are turned on affects the output of the PIN6 of the first logic gate optical coupler U1, as shown in table 1 with reference to the following truth table of 6N 127:

table 1

LED	ENABLE(PIN 7)	OUT(PIN 6)
			ON	H	L
OFF	H	H
			ON	L	H
OFF	L	H
			ON	NC	L
OFF	NC	H

Note that the PINs 7 of the first logic gate optical coupler U1 and the second logic gate optical coupler U2 default to high. Since the second logic gate optical coupler U2 has no output, PIN7 of the first logic gate optical coupler U1 remains high, and according to table 1, LED is ON (ON) and PIN7 is H (high), VOUT _ I of PIN6 output of the first logic gate optical coupler U1 is L (low), that is, PIN7 of the second logic gate optical coupler U2 is L (low), so that the output of the second logic gate optical coupler U2 is turned off, and PIN6 output of the second logic gate optical coupler U2 is constantly high. That is, the first voltage signal is at a low level, the second voltage signal is at a high level, and the first logic operation module, such as the CPU1 and/or the CPU2, reads the first voltage signal and/or the second voltage signal to determine that the first logic operation module is the main logic operation module. Similarly, for example, when the CPU3 and the CPU4 included in the second logic operation module output first a level to turn ON the PIN2 of the second logic gate optical coupler U2 and the diode at the PIN3, since the first logic gate optical coupler U1 does not output, the PIN7 of the second logic gate optical coupler U2 remains high, and as shown in table 1, if the LED is ON (ON) and the PIN7 is H (high), VOUT _ II of the PIN6 output of the second logic gate optical coupler U2 is L (low), that is, the PIN7 of the first logic gate optical coupler U1 is L (low), so that the output of the first logic gate optical coupler U1 is turned off, and the PIN6 output of the first logic gate optical coupler U1 is constantly high. That is, the second voltage signal is at a low level, the first voltage signal is at a high level, and the second logic operation module, such as the CPU3 and/or the CPU4, reads the first voltage signal and/or the second voltage signal to determine that the second logic operation module is the main logic operation module. It is understood that the

CPUs

1, 2, 3 and 4 in the first and second logic operation modules can read the first voltage signal and/or the second voltage signal, and the application is not limited to which CPU reads the voltage signal.

In one possible embodiment, the interlock switching circuit further includes a first read-back unit 502 and a second read-back unit 503, such that the first read-back unit 502 includes a first phototransistor U3; the second read-back unit 503 includes a second phototransistor U4, and the specific model is MOCD213R2M for illustration.

The first output terminal of the first read-back unit 502 is the PIN7 of the first phototransistor U3, and the input terminal of the first read-back unit 502 is the PIN1 of the first phototransistor U3; the first output terminal of the second read-back unit 503 is the PIN7 of the second phototransistor U4, and the input terminal of the second read-back unit 503 is the PIN1 of the second phototransistor U4. The PIN6 of the first logic gate optical coupler U1 is connected to the PIN1 of the first phototransistor U3, and optionally, the PIN6 of the first logic gate optical coupler U1 may be connected to the PIN1 of the first phototransistor U3 via a fifth resistor R5. The PIN6 of the second logic gate optical coupler U2 is connected to the PIN1 of the second phototransistor U4, and optionally, the PIN6 of the second logic gate optical coupler U2 may be connected to the PIN1 of the second phototransistor U4 via a ninth resistor R9. The PIN7 of the first phototransistor U3 is coupled to the PIN7 of the second logic gate optocoupler U2 and to an input of the first logic operation block, and the PIN7 of the first phototransistor U3 is illustratively coupled to an input of the CPU 1. The PIN7 of the second phototransistor U4 is connected to the PIN7 of the second logic gate optocoupler U2 and to an input of the second logic operation module, and the PIN7 of the second phototransistor U4 is illustratively connected to an input of the CPU 3. PIN7 of the first phototransistor U3 is connected to CH1_ GND through a seventh resistor R7, PIN2 of the first phototransistor U3 is connected to CH3_ GND, PIN 8 of the first phototransistor U3 is connected to CH1_ 3.3V; the PIN7 of the second phototransistor U4 is connected to the CH3_ GND through a twelfth resistor R12, and the PIN 8 of the second phototransistor U4 is connected to the CH3_ 3.3V.

The working principle of the interlocking switching circuit is as follows:

taking the example that the CPU1 and the CPU2 included in the first logic operation block output the level of turning on the diodes at the PIN2 and PIN3 of the first logic gate optical coupler U1 first, VOUT _ I of PIN6 output of the first logic gate optocoupler U1 is L (low), i.e., PIN1 of the first phototransistor U3 is outputting a low level, PIN1 of the first phototransistor U3 and the light emitting diode in PIN2 are not turned on, the transistor between PIN7 and PIN 8 of the first phototransistor U3 is turned off, i.e., PIN7 outputs low level, the enable terminal PIN7 of the second logic gate optical coupler U2 connected to PIN7 of the first phototransistor U3 is low level, thereby turning off the output of the second logic gate optocoupler U2, the PIN6 output of the second logic gate optocoupler U2 is constantly high. Namely, the first read-back signal is at a low level; the second read-back signal is at a high level, and the first logic operation module, such as the CPU1 and/or the CPU2, reads the first read-back signal and/or the second read-back signal, and determines that the first logic operation module is the main logic operation module. Similarly, for example, the CPU3 and the CPU4 included in the second logic operation module output the level for turning on the PIN2 of the second logic gate optical coupler U2 and the diode at the PIN3, VOUT _ II of PIN6 output of the second logic gate optocoupler U2 is L (low), i.e., PIN1 of the second phototransistor U4 is outputting a low level, PIN1 of the second phototransistor U4 and the light emitting diode in PIN2 are not turned on, the transistor between PIN7 and PIN 8 of the second phototransistor U4 is turned off, i.e., PIN7 outputs low level, the enable terminal PIN7 of the first logic gate optical coupler U1 connected to PIN7 of the second phototransistor U4 is low level, thereby turning off the output of the first logic gate optocoupler U1, the PIN6 output of the first logic gate optocoupler U1 is constantly high. That is, the first read-back signal is at a high level, the second read-back signal is at a low level, and the second logic operation module, such as the CPU3 and/or the CPU4, reads the first read-back signal and/or the second read-back signal, and determines that the second logic operation module is the primary logic operation module.

In a possible implementation manner, the second output terminal of the first read-back unit 502 is the PIN6 of the first phototransistor U3, the PIN6 of the first phototransistor U3 is connected to the input terminal of the first logic operation module, for example, the PIN6 of the first phototransistor U3 is connected to the input terminal of the CPU1, optionally, the PIN6 of the first phototransistor U3 is connected to the CH2_3.3V through an eighth resistor R8, the input terminal of the first read-back unit 502 may further include the PIN3 of the first phototransistor U3, and the PIN 4 of the first read-back unit 502 is connected to the CH3_ GND; the second output terminal of the read-back unit 503 of the second read-back unit is PIN6 of the second phototransistor U4, PIN6 of the second phototransistor U4 is connected to the input terminal of the second logic operation module, for example, PIN6 of the second phototransistor U4 is connected to the input terminal of the CPU3, optionally, PIN6 of the first phototransistor U3 is connected to CH4_3.3V through an eighth resistor R8, the input terminal of the second read-back unit 503 may further include PIN3 of the second phototransistor U4, and PIN 4 of the second read-back unit 503 is connected to CH1_ GND.

The working principle of the read-back circuit is as follows: the PIN7 of the first phototransistor U3 is opposite the read back signal output by PIN 5, so the third read back signal is low when the first read back signal is high; similarly, the PIN7 of the second phototransistor U4 is opposite to the read-back signal output by PIN 5, and the fourth read-back signal is high when the second read-back signal is low. Any one CPU in the second logic operation module and/or the first logic operation module reads a plurality of read-back signals, and determines the main logic operation module, for example, if the first read-back signal is low level, the third read-back signal is high level, and determines the first logic operation module as the main logic operation module; the second read-back signal is at a low level, the fourth read-back signal is at a high level, and the second logic operation module is determined to be the main logic operation module.

Further, the interlock switching circuit further includes a first switching driving unit 504, and the first switching driving unit 504 includes a first optical coupling relay U5 and a second optical coupling relay U6, and the specific model is AQV212S for example.

PIN1 of first opto-coupler relay U5 is first input, PIN1 of second opto-coupler relay U6 is the second input, PIN 4 of first opto-coupler relay U5 and PIN6 of second opto-coupler relay U6 are the output of first switching drive unit 504, PIN6 and CH1_5V of first opto-coupler relay U5 are connected, PIN 4 and CH1_ GND of second opto-coupler relay U6 are connected, wherein:

PIN2 of the first logic gate optical coupler U1 is connected with PIN 4 of the first optical coupling relay U5, PIN3 of the first logic gate optical coupler U1 is connected with PIN6 of the second optical coupling relay U6, PIN1 of the first optical coupling relay U5 is connected with an output end of the CPU1, optionally, an output end of the CPU1 can be connected with PIN1 of the first optical coupling relay U5 through a thirteenth resistor R13, an output end of the CPU1 is further connected with PIN2 of the first optical coupling relay U5 and CH1_ GND through a fourteenth resistor R14, and the thirteenth resistor R13 and the fourteenth resistor R14 are used for preventing overcurrent from damaging the first optical coupling relay U5. The PIN1 of the second optical coupler relay U6 is connected to the output end of the CPU2, optionally, the output end of the CPU2 is connected to the PIN1 of the second optical coupler relay U6 through a fifteenth resistor R15, the output end of the CPU2 is further connected to the PIN2 of the second optical coupler relay U6 and CH2_ GND through a sixteenth resistor R16, and the fifteenth resistor R15 and the sixteenth resistor R16 are used for preventing overcurrent from damaging the second optical coupler relay U6.

The working principle of the interlocking switching circuit is as follows:

taking the first logic operation module as an example to output a high level first, that is, the first processor CPU1 outputs a high level, the second processor CPU2 also outputs a high level, the diode between the

PINs

1 and 2 of the first optical coupler relay U5 is turned on, the diode between the PINs 1 and PIN2 of the second optical coupler relay U6 is turned on, the diode between the PINs 2 and PIN3 of the first logic gate optical coupler U1 is turned on, and since the second logic operation module does not output, the enable terminal PIN7 of the first logic gate optical coupler U1 is a high level, so the PIN6 of the first logic gate optical coupler U1 outputs a low level, that is, the input terminals PIN1 and PIN3 of the first read-back unit U3 are low levels, the PIN7 of the first read-back unit U3 is a low level, the PIN6 is a high level, and at this time, the PIN7 of the first read-back unit U3 of the CPU1 is a low level, and PIN6 is high level, and the first logic operation module is confirmed to be a main logic operation module.

Furthermore, the interlock switching circuit further includes a second switching driving unit 505, and the second switching driving unit 505 includes a third optical coupling relay U7 and a fourth optical coupling relay U8, specifically model is AQV212S for example.

PIN1 of third opto-coupler relay U7 is the third input, PIN1 of fourth opto-coupler relay U8 is the fourth input, PIN 4 of third opto-coupler relay U7 and PIN6 of fourth opto-coupler relay U8 are the output of second switching drive unit 505, PIN6 and CH3_5V of third opto-coupler relay U7 are connected, PIN 4 and CH3_ GND of fourth opto-coupler relay U6 are connected, wherein:

PIN2 of the second logic gate optical coupler U2 is connected with PIN 4 of the third optical coupling relay U7, PIN3 of the second logic gate optical coupler U2 is connected with PIN6 of the fourth optical coupling relay U8, PIN1 of the third optical coupling relay U7 is connected with the output end of the CPU3, optionally, the output end of the CPU3 can be connected with PIN1 of the third optical coupling relay U7 through a seventeenth resistor R17, the output end of the CPU3 is further connected with PIN2 and CH3_ GND of the third optical coupling relay U7 through an eighteenth resistor R18, and the seventeenth resistor R17 and the eighteenth resistor R18 are used for preventing overcurrent from damaging the third optical coupling relay U7. The PIN1 of the fourth optical coupler relay U8 is connected with the output end of the CPU4, optionally, the output end of the CPU4 is connected to the PIN1 of the fourth optical coupler relay U8 through a nineteenth resistor R19, the output end of the CPU4 is further connected with the PIN2 of the fourth optical coupler relay U8 and the CH4_ GND through a twentieth resistor R20, and the nineteenth resistor R19 and the twentieth resistor R20 are used for preventing overcurrent from damaging the fourth optical coupler relay U8.

The working principle of the interlocking switching circuit is as follows:

when the first logical operation block abandons the main logical operation block, the third processor CPU3 outputs a high level, the fourth processor CPU4 also outputs a high level, the diode between the PIN1 and the PIN2 of the third optocoupler relay U7 is turned on, the diode between PIN1 and PIN2 of the second logic gate optocoupler U2 is turned on, since the first logic operation block is not the main logic operation block, the enable PIN7 of the second logic gate optocoupler U2 is high, so the PIN6 of the second logic gate optocoupler U2 outputs low, i.e. inputs PIN1 and PIN3 of said second read-back unit U4 are low, the PIN7 of the second read-back unit U4 is at a low level and the PIN6 is at a high level, and at this time, the CPU3 reads that the PIN7 of the second read-back unit U4 is at a low level and the PIN6 is at a high level, and confirms that the second logic operation module is the main logic operation module.

Referring to fig. 6, fig. 6 is a system architecture diagram of a signaling system according to an embodiment of the present disclosure. As shown in fig. 6, the signaling system 60 includes a first logic operation module 600, a second logic operation module 601, and an interlock switching circuit 602, and it is understood that the interlock switching circuit 602 includes any one of the interlock switching circuits described above, and the signaling system 60 is used for rail transit or automobiles. The first logic operation module 600 and/or the second logic operation module 601 may be a Central Processing Unit (CPU), and the processor may also be other general purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. Optionally, the first logic operation module 600 and the second logic operation module 601 may be configured to implement a 2-by-2-out-of-2 architecture, the first logic operation module 600 and the second logic operation module 601 respectively have independent channels, and when the signal system 60 is powered on, the interlock switching circuit 602 implements active/standby switching between the two modules.

It should be noted that the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the embodiments provided in the present application, it should be understood that the disclosed method, apparatus, and system may be implemented in other ways. The above-described embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or other forms.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, all the functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately regarded as one unit, or two or more units may be integrated into one unit; the integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.

Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program performs the steps including the method embodiments; and the aforementioned storage medium includes: a mobile storage device, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

Alternatively, the integrated unit of the present invention may be stored in a computer-readable storage medium if it is implemented in the form of a software functional module and sold or used as a separate product. Based on such understanding, the technical solutions of the embodiments of the present invention may be essentially implemented or a part contributing to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the methods described in the embodiments of the present invention. And the aforementioned storage medium includes: a removable storage device, a ROM, a RAM, a magnetic or optical disk, or various other media that can store program code.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. The interlocking switching circuit is characterized by being arranged between a first logic operation module and a second logic operation module and comprising a first interlocking unit and a second interlocking unit, wherein the first interlocking unit and the second interlocking unit respectively comprise an input end, an output end and an enabling end, and the interlocking switching circuit comprises:

2. The interlock switching circuit of claim 1, further comprising a first read-back cell and a second read-back cell, the first read-back cell and the second read-back cell each comprising a first output;

3. The interlock switching circuit of claim 1 wherein the first logic operation module comprises a first processor and a second processor;

4. The interlock switching circuit of claim 3 wherein said second logic operation module comprises a third processor and a fourth processor;

5. The interlock switching circuit of claim 2, wherein the first read-back unit and the second read-back unit further comprise a second output;

6. The interlock switching circuit of claim 1 wherein the first interlock unit comprises a first logic gate optical coupler and the second interlock unit comprises a second logic gate optical coupler.

7. The interlock switching circuit of any one of claims 2 or 5 wherein the first read-back cell comprises a first phototransistor; the second read-back unit includes a second phototransistor.

8. The interlock switching circuit of claim 3, wherein the first switching drive unit comprises a first optocoupler relay having an input as the first input and a second optocoupler relay having an input as the second input.

9. The interlock switching circuit according to claim 4, wherein the second switching drive unit includes a third optical coupling relay whose input is the third input and a fourth optical coupling relay whose input is the fourth input.

10. A signalling system comprising a first logic operation module, a second logic operation module and the interlock switching circuit of any one of claims 1 to 9, the signalling system being for use in rail transit or in automobiles.