CN113743569B - Pulse signal transmitting method, device and storage medium - Google Patents
Pulse signal transmitting method, device and storage medium Download PDFInfo
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- CN113743569B CN113743569B CN202010477960.2A CN202010477960A CN113743569B CN 113743569 B CN113743569 B CN 113743569B CN 202010477960 A CN202010477960 A CN 202010477960A CN 113743569 B CN113743569 B CN 113743569B
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 210000003050 axon Anatomy 0.000 claims abstract description 106
- 210000002569 neuron Anatomy 0.000 claims abstract description 102
- 230000005540 biological transmission Effects 0.000 claims description 8
- 230000002776 aggregation Effects 0.000 claims description 7
- 238000004220 aggregation Methods 0.000 claims description 7
- 230000004931 aggregating effect Effects 0.000 claims description 4
- 230000008054 signal transmission Effects 0.000 claims description 4
- 238000013528 artificial neural network Methods 0.000 abstract description 14
- 210000001787 dendrite Anatomy 0.000 description 5
- 210000000225 synapse Anatomy 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000013135 deep learning Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
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Abstract
The invention relates to a pulse signal transmitting method, a pulse signal transmitting device and a pulse signal storage medium, in particular to a pulse signal transmitting method, a pulse signal transmitting device and a pulse signal storage medium, when pulse signals are required to be transmitted to a plurality of target axons, a plurality of pulse signals with the same transmitting neuron, the same target chip address and the same target neuron core address but different target neuron core inner axon addresses are aggregated into one or more data packets to be transmitted, so that the number of the data packets is reduced, and the problem of excessively high bandwidth occupied by virtual connection in a large-scale pulse neural network is solved.
Description
Technical Field
The present invention relates to the field of signal processing of a pulse neural network, and in particular, to a method and apparatus for transmitting a pulse signal, and a storage medium.
Background
Implementation of deep neural networks typically requires a significant amount of computational effort. As with classical deep convolutional network model AlexNet, at least 7.2 hundred million multiplication operations are required. The large amount of operation generates large power consumption, which is generally about 10 watts to 100 watts.
Solving the above problems, impulse neural networks (SNNs) have attracted attention in academia and industry in recent years due to their low power consumption and more human brain-approaching characteristics. In a impulse neural network, an axon is a unit that receives impulses, a neuron is a unit that transmits impulses, and one neuron is connected to a plurality of axons through dendrites, and the connection point of dendrites and axons is called a synapse. After the axon receives the pulse, all dendrites connected with the axon have the synapse connection receive the pulse, and the dendrite downstream neurons are affected. The neuron sums pulses from multiple axons and sends one pulse downstream if the value exceeds a threshold. The pulse neural network propagates 1-bit pulse, the activation frequency of the pulse is low, and only addition and subtraction operations are needed, and no multiplication operation is needed. Compared to deep learning based neural networks, impulse neural networks consume less power.
One neuron is connected with more than 1000 axons through dendrites, and virtual connection is commonly adopted for connection among the neurons in actual hardware implementation in a pulse neural network due to space limitation: the transmitting neuron transmits a data packet Bao Zhongzhi to clarify the chip address, the neuron core address and the neuron inner axon address of the target axon. After receiving the data packet, the target neuron core stores the data packet into a memory according to the axon address to wait for operation. It can be seen that a 1-bit direct connection requires a multi-bit wide packet to represent in a virtual connection. One packet needs to be sent every time a pulse is sent. The bandwidth occupied by the virtual connection is much higher than the bandwidth of the direct connection.
Disclosure of Invention
The invention aims to provide a pulse signal transmitting method, a pulse signal transmitting device and a pulse signal storage medium, when pulse signals need to be transmitted to a plurality of target axons, the pulse signals with the same transmitting neuron, the same target chip address and the same target neuron core address are aggregated into one or more data packets for transmission by a plurality of pulse signals with different target neuron core inner axon addresses, so that the number of the data packets is reduced, and the problem of excessively high bandwidth occupied by virtual connection in a large-scale pulse neural network is solved.
The aim of the invention can be achieved by the following technical scheme:
A pulse signal transmission method, comprising:
Receiving a request for sending a pulse signal;
judging whether at least two target axons in all target axons of the pulse signals to be sent are positioned in the same target chip and the same neuron core, if so, then
And determining the number N of the required data packets according to the number of pulse signals to be transmitted, of which the target axons are positioned in the same target chip and the same neuron core, and the upper limit of the target number of the preconfigured data packets, and aggregating the pulse signals to be transmitted, of which the target axons are positioned in the same target chip and the same neuron core, into N data packets for transmission.
A pulse signal transmitting apparatus comprising:
A request receiving unit configured to receive a request to transmit a pulse signal;
a judging unit configured to judge whether at least two target axons are located in the same target chip and the same neuron nucleus among all target axons of the pulse signals to be transmitted,
The aggregation transmitting unit is configured to determine the number N of required data packets according to the number of the pulse signals to be transmitted in the same target chip and the same neuron core, which are the target axons, and the upper limit of the target number of the preconfigured data packets when at least two target axons in all the target axons of the pulse signals to be transmitted are in the same target chip and the same neuron core, and aggregate the pulse signals to be transmitted, which are the target axons in the same target chip and the same neuron core, into N data packets for transmission.
A readable storage medium having stored thereon a program which when executed by a processor performs a method as described above.
Another aspect of the present invention is to provide an inexpensive data packet structure that can be implemented by the following means.
The data packet is composed of a basic data segment and a plurality of address data segments, each address data segment is composed of an axon address and a valid bit, wherein the valid bit is used for representing whether the corresponding axon address is the address of a target axon needing to send a pulse signal. The valid bit of at least one address data segment in one data packet may not be transmitted, and is used for representing that the corresponding axon address is the address of the target axon needing to transmit the pulse signal.
In another embodiment, the data packet is composed of a basic data segment and a plurality of address data segments, and each of the remaining address data segments is composed of an axon address and a valid bit, except that the first address data segment is composed of an axon address, where the valid bit is used to characterize whether the corresponding axon address is an address of a target axon that needs to send a pulse signal.
If the address of the axon in the address data segment is the address of the target axon needing to send the pulse signal, the valid bit is 1, otherwise, the valid bit is 0.
If the valid bit value in the address data segment is an address representing that the axon address is a target axon which does not need to send a pulse signal, the axon address can be randomly generated data or any other data.
In the same data packet, the valid address data segment is located before the invalid address data segment, wherein the valid bit of the valid address data segment is used for representing that the corresponding axon address is the address of the target axon needing to send the pulse signal, and the valid bit of the invalid address data segment is used for representing that the corresponding axon address is the address of the target axon not needing to send the pulse signal.
Compared with the prior art, the invention has the following beneficial effects:
1) The method comprises the steps of aggregating a plurality of pulse signals with the same transmitting neuron, the same target chip address and the same target neuron core address but different axon addresses in the target neuron core into one or more data packets for transmission, so that the number of the data packets is reduced, and the problem of overhigh bandwidth occupied by virtual connection in a large-scale pulse neural network is solved.
2) By designing the composition structure of the data packet, the overall size of the data packet can be reduced when the pulse signal aggregation transmission is performed.
3) By setting the address data segment that is invalid at the end, the response rate can be improved, and the data processing amount of the receiving side can be reduced.
Detailed Description
The present invention will be described in detail with reference to specific examples. The present embodiment is implemented on the premise of the technical scheme of the present invention, and a detailed implementation manner and a specific operation process are given, but the protection scope of the present invention is not limited to the following examples.
In order to solve the problem of too high bandwidth occupied by virtual connection in a large-scale pulse neural network, the application provides a pulse signal sending method, which comprises the following steps:
Receiving a request for sending a pulse signal;
Judging whether at least two target axons in all target axons of pulse signals to be sent are located in the same target chip and the same neuron core, if so, determining the number N of required data packets according to the number of the pulse signals to be sent of which the target axons are located in the same target chip and the same neuron core and the upper limit of the target number of the preconfigured data packets, and aggregating the pulse signals to be sent of which the target axons are located in the same target chip and the same neuron core into N data packets to be sent.
The corresponding can be realized by a pulse signal transmitting device, which comprises:
A request receiving unit configured to receive a request to transmit a pulse signal;
a judging unit configured to judge whether at least two target axons are located in the same target chip and the same neuron nucleus among all target axons of the pulse signals to be transmitted,
The aggregation transmitting unit is configured to determine the number N of required data packets according to the number of the pulse signals to be transmitted in the same target chip and the same neuron core, which are the target axons, and the upper limit of the target number of the preconfigured data packets when at least two target axons in all the target axons of the pulse signals to be transmitted are in the same target chip and the same neuron core, and aggregate the pulse signals to be transmitted, which are the target axons in the same target chip and the same neuron core, into N data packets for transmission.
The program may be stored in a readable storage medium in the form of a program, which when executed by a processor, implements a method as described above.
In one embodiment of the present application, a structure of a data packet is designed, the data packet is composed of a basic data segment and a plurality of address data segments, each address data segment is composed of an axon address and a valid bit, wherein the valid bit is used for characterizing whether the corresponding axon address is an address of a target axon needing to send a pulse signal.
Specifically, for example, consider 2 pulse signal aggregation, if a single pulse signal needs to be represented by a 40-bit packet, and assuming that the axon address bit width is 9 bits, this packet is expanded, adding 9 bits to the second axon address, and 1 bit to characterize whether the second axon address exists. Thus, a 40+9+1=50-bit packet mechanism is obtained, and this 50-bit packet can replace the original 2 40-bit packets. In this example, the bandwidth requirement is (50)/(40×2) =62.5%, and the number of data packets is reduced by half.
In other embodiments, the original pulse signal may not be 40 bits, nor is the axon address 9 bits, but the general principle of the way is similar.
In one embodiment of the present application, if the address of the axon in the address data segment is the address of the target axon that needs to send the pulse signal, the valid bit is 1, otherwise, the valid bit is 0, and this way is matched with the knowledge of the public, so that the understanding is convenient.
In another embodiment of the present application, if the valid bit value in the address data segment is an address indicating that the axon address is a target axon that does not need to send a pulse signal, the axon address may be randomly generated data or any other data.
In order to save resources, the valid bit of the first address data segment in a data packet may not be sent, which is used to characterize the corresponding axon address as the address of the target axon that needs to send the pulse signal, so that the width of the data packet may be reduced by 1 bit.
In one embodiment of the present application, the upper limit of the number of targets of the pre-configured packet is based on the maximum number of targets that can be supported in the hardware implementation, specifically, it is assumed that all the axons are directed to the neuron core a, and the neuron core a has 6 axons in total, 4 of which are required to burst pulse data this time, and the 4 axons are assumed to be a, b, c, d, and the other two axons are e and f, respectively
When the hardware aggregates 2 pulse signals at most, it can be realized as follows:
Packet 1 contains the chip address of neuron core a, the address of on-chip neuron core a, the address of neuron b, 1 (indicating that neuron b is also a valid receive address),
Packet 2 contains the chip address of neuron core a, the address of on-chip neuron core a, the address of neuron c, the address of neuron d, 1 (indicating that neuron d is also a valid receive address).
When the hardware aggregates at most 3 pulse signals, the implementation method 1 is as follows:
packet 1 contains the chip address of neuron core a, the address of on-chip neuron core a, the address of neuron b, 1 (indicating that neuron b is also a valid receive address), the address of neuron c, 1 (indicating that neuron c is also a valid receive address),
The data packet 2 contains the chip address of the neuron core a, the address of the on-chip neuron core a, the neuron d address, the neuron e address, 0 (indicating that the neuron e is not a valid receiving address), the neuron f address, 0 (indicating that the neuron f is not a valid receiving address);
The inventors have noted that: the manner in which packet 1 contains acd/abd/bcd and packet 2 contains b/c/a is consistent with the concepts of implementing method 1 described above, as follows.
When the hardware aggregates at most 3 pulse signals, the implementation method 2 is as follows:
Packet 1 contains the chip address of neuron core a, the address of on-chip neuron core a, the address of neuron b, 1 (indicating that neuron b is also a valid receive address), the address of neuron e, 0 (indicating that neuron e is not a valid receive address),
The data packet 2 contains the chip address of the neuron core a, the address of the on-chip neuron core a, the neuron c address, the neuron d address, 1 (indicating that the neuron d is a valid receiving address), the neuron f address, and 0 (indicating that the neuron f is not a valid receiving address).
When hardware aggregates 5 pulse signals at most, the method 1 is implemented:
the data packet 1 comprises a chip address of the neuron core A, an address of the neuron core A in the chip and a neuron a address; neuron b address, 1 (indicating that neuron b is also a valid receive address); neuron c address, 1 (indicating that neuron c is a valid receive address); neuron d address, 1 (indicating that neuron d is a valid receive address); neuron e address, 0 (indicating that neuron e is a valid receive address)
When hardware aggregates 5 pulse signals at most, method 2 is implemented:
the data packet 1 comprises a chip address of the neuron core A, an address of the neuron core A in the chip and a neuron a address; neuron b address, 1 (indicating that neuron b is also a valid receive address); neuron c address, 1 (indicating that neuron c is a valid receive address); neuron e address, 0 (indicating that neuron e is not a valid receive address); neuron d address, 1 (indicating that neuron d is a valid receive address)
When one packet contains one or more invalid addresses, the invalid address may be placed at the rearmost position, and the corresponding address valid bit is set to 0; invalid addresses may be distributed in a plurality of locations, and the corresponding address valid bit may be set to 0. However, in this example, since the first address has no corresponding address valid bit, the first address is always valid by default, so the invalid address cannot be placed at the first address. Of course, one could also arrange for the first address to be a valid bit, in which case the invalid address could be placed anywhere.
The pulse aggregation method can be popularized to applications other than the general pulse neural network. For example, in a convolutional-based impulse neural network, a transmitting neuron may transmit impulses to multiple neurons in the same core of the same chip, and the multiple target neurons may be aggregated as well, which may occur in the same channel and at different spatial locations, with the above-mentioned axon addresses replaced by spatial coordinates; aggregation may also occur on different channels at the same spatial location, with the above described axon address being replaced by the channel address.
Claims (5)
1. A pulse signal transmission method, comprising:
Receiving a request for sending a pulse signal;
judging whether at least two target axons in all target axons of the pulse signals to be sent are positioned in the same target chip and the same neuron core, if so, then
Determining the number N of required data packets according to the number of pulse signals to be transmitted, of which the target axons are positioned in the same target chip and the same neuron core, and the upper limit of the target number of the pre-configured data packets, and aggregating the pulse signals to be transmitted, of which the target axons are positioned in the same target chip and the same neuron core, into N data packets for transmission;
the data packet consists of a basic data segment and a plurality of address data segments, wherein each address data segment consists of an axon address and a valid bit, and the valid bit is used for representing whether the corresponding axon address is the address of a target axon needing to send a pulse signal;
the valid bit of at least the first address data segment exists in one data packet and is used for representing that the corresponding axon address is the address of the target axon needing to send the pulse signal;
The valid bit of the valid address data segment is used for representing that the corresponding axon address is the address of the target axon needing to send the pulse signal, wherein the valid bit of the invalid address data segment is used for representing that the corresponding axon address is the address of the target axon not needing to send the pulse signal.
2. The method of claim 1, wherein if the address of the axon in the address data segment is the address of the target axon to be sent, the valid bit is 1, and vice versa, the valid bit is 0.
3. The pulse signal transmission method according to claim 1, wherein if the valid bit value in the address data segment is an address indicating that the axon address is a target axon for which the pulse signal is not required, the axon address is an arbitrary value.
4. A pulse signal transmission apparatus, comprising:
A request receiving unit configured to receive a request to transmit a pulse signal;
a judging unit configured to judge whether at least two target axons are located in the same target chip and the same neuron nucleus among all target axons of the pulse signals to be transmitted,
The aggregation transmitting unit is configured to determine the number N of required data packets according to the number of the pulse signals to be transmitted in the same target chip and the same neuron core, which are the target axons, and the upper limit of the target number of the preconfigured data packets when at least two target axons in the target axons of all the pulse signals to be transmitted are in the same target chip and the same neuron core, and aggregate the pulse signals to be transmitted, which are the target axons in the same target chip and the same neuron core, into N data packets for transmission;
The data packet consists of a basic data segment and a plurality of address data segments, wherein each address data segment consists of an axon address and a valid bit, and the valid bit is used for representing whether the corresponding axon address is the address of a target axon needing to send a pulse signal;
the valid bit of at least the first address data segment exists in one data packet and is used for representing that the corresponding axon address is the address of the target axon needing to send the pulse signal;
The valid bit of the valid address data segment is used for representing that the corresponding axon address is the address of the target axon needing to send the pulse signal, wherein the valid bit of the invalid address data segment is used for representing that the corresponding axon address is the address of the target axon not needing to send the pulse signal.
5. A readable storage medium having stored thereon a program which when executed by a processor implements the method of any of claims 1-3.
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| CN202010477960.2A CN113743569B (en) | 2020-05-29 | Pulse signal transmitting method, device and storage medium |
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| CN202010477960.2A CN113743569B (en) | 2020-05-29 | Pulse signal transmitting method, device and storage medium |
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| CN113743569B true CN113743569B (en) | 2024-07-05 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106161254A (en) * | 2016-07-18 | 2016-11-23 | 中国科学院计算技术研究所 | A kind of many purposes data transmission network road route device, method, chip, router |
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106161254A (en) * | 2016-07-18 | 2016-11-23 | 中国科学院计算技术研究所 | A kind of many purposes data transmission network road route device, method, chip, router |
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