CN113741109A

CN113741109A - Array substrate and display panel

Info

Publication number: CN113741109A
Application number: CN202111051100.3A
Authority: CN
Inventors: 鲁康
Original assignee: TCL Huaxing Photoelectric Technology Co Ltd
Current assignee: TCL China Star Optoelectronics Technology Co Ltd; TCL Huaxing Photoelectric Technology Co Ltd
Priority date: 2021-09-08
Filing date: 2021-09-08
Publication date: 2021-12-03

Abstract

An array substrate comprises a plurality of sub-pixels which are arranged in an array mode, and each sub-pixel is divided into a main pixel area and a sub-pixel area. Every line the sub-pixel still includes main area thin film transistor and subregion thin film transistor, main area thin film transistor is including being connected main area pixel electrode and first common electrode through first via hole, subregion thin film transistor is including being connected the second common electrode of subregion pixel electrode through the second via hole, wherein in each row B colour in the sub-pixel, still including with two adjacent main area pixel electrode first common electrode with the grid metal routing that the second common electrode of subregion pixel electrode is connected together, prevent thereby that vertical crosstalk from realizing the optimization to picture taste and display performance simultaneously. The invention also provides a display panel.

Description

Array substrate and display panel

Technical Field

The invention relates to the technical field of liquid crystal display, in particular to an array substrate and a display panel comprising the same.

Background

As shown in fig. 1, in the conventional 3T (three TFT) structure, Data signals are supplied from the same Data line Data to the main pixel unit 11 and the sub-pixel unit 12 of the same pixel unit 1, and the same image display Data is written to the main pixel unit 11 and the sub-pixel unit 12. Specifically, the Data line Data respectively provides voltages to the first switch T1 of the main pixel unit 11 and the second switch T2 of the sub-pixel unit 12, wherein one end of the second switch T2 further leaks electricity to the voltage stabilization line Acom through the third switch T3, so that the potential of the sub-pixel unit 12 is lower than the potential of the main pixel unit 11, thereby causing the positive and negative frame charging difference of the pixel unit 1 and causing the Data line coupling (Data coupling) on both sides of the pixel to be different, and further causing the problems of Low Color Shift (LCS), horizontal series winding (H-cross, H-CT), moire (Mura) and display performance degradation.

Since the signal of the common electrode Acom of the sub-pixel unit 12 is provided by the transparent metal oxide layer, the transparent metal oxide layer needs to communicate with the drain of the second switching element T2 of the sub-pixel unit 12 through a via hole in order to transmit the signal of the common electrode Acom to the sub-pixel unit 12. However, the via hole reduces the aperture ratio (AR%) of the pixel unit 1 in the display area, thereby affecting the light transmittance of the display panel. In addition, the display panel also needs to turn on white balance (white tracking) in the debugging stage, and most of the display panels need to chop the blue sub-pixels, so that when a gray-bottom white frame is displayed, the coupling asymmetry of the left and right Data lines Data can be caused, and vertical crosstalk (V-cross; V-CT) is caused, wherein the larger the capacitance between the Data lines Data and the pixel electrodes is, the more serious the influence is.

Disclosure of Invention

The invention aims to provide an array substrate and a display panel, which prevent vertical crosstalk and simultaneously realize optimization of picture quality and display performance by adopting a grid metal routing design.

In order to achieve the above object, the present invention provides an array substrate including a plurality of sub-pixels arranged in an array, each sub-pixel is formed by cyclically arranging sub-pixels of three colors of red, green and blue, each sub-pixel is divided into a main pixel area and a sub-pixel area, a scan line is respectively disposed corresponding to each row of sub-pixels, the scan line is disposed between the main pixel area and the sub-pixel area, and a data line is respectively disposed corresponding to each column of sub-pixels. Every line the sub-pixel still includes main district's thin film transistor and subregion thin film transistor, main district's thin film transistor is including being connected main district pixel electrode and first common electrode through first via hole, subregion thin film transistor is including being connected the second common electrode of subregion pixel electrode through the second via hole, wherein, blue in each line in the sub-pixel, still include with two adjacent main district pixel electrode first common electrode with the grid metal routing that the second common electrode of subregion pixel electrode is connected.

Preferably, the grid metal routing crosses over the scan lines of the blue sub-pixels in each row and connects the first common electrode of the main area pixel electrode and the second common electrode of the sub-area pixel electrode through a third via hole and a fourth via hole.

Preferably, the first via hole and the second via hole have depths greater than the third via hole and the fourth via hole, and the first common electrode, the second common electrode, and the scan line are disposed on the same layer.

Preferably, the display device further comprises a substrate, a gate insulating layer and a passivation layer, wherein the substrate is arranged in a stacked manner, the gate insulating layer is arranged on the first common electrode, the second common electrode and the scanning line, and the passivation layer is arranged on the grid metal routing.

Preferably, the aperture ratio of the sub-pixels of each row of blue is smaller than the aperture ratio of the sub-pixels of each row of red and green, and the pixel area of the sub-pixels of each row of blue is smaller than or equal to the pixel area of the sub-pixels of each row of red and green.

Preferably, the aperture ratio of the sub-pixels of each row of blue colors is smaller than the aperture ratio of the sub-pixels of each row of red and green colors and ranges from 1% to 10%.

Preferably, each row of the sub-pixels further includes a shared thin film transistor located between the main pixel region and the sub-pixel region, and a shared metal trace disposed on a vertical trunk of the sub-pixel electrode.

Preferably, a third gate of the shared thin film transistor is connected to the scan line, a third source is connected to the data line, and a third drain is connected to the shared metal trace.

Preferably, the sub-pixel further includes a first capacitor and a second capacitor, the first capacitor is a storage capacitor of the main pixel region and is formed by a storage electrode of the main pixel region and an opposite common electrode; the second capacitor is a storage capacitor of the sub-pixel area and is formed by a storage electrode of the sub-pixel area and an opposite common electrode.

Furthermore, the present invention also provides a display panel including the array substrate according to the above embodiment.

The invention also has the following effects that through separately designing each blue sub-pixel with the grid metal routing (Mesh _ com) of the first common electrode (Acom) and the second common electrode (Acom) connecting the main pixel area and the sub-pixel area and each red sub-pixel, the grid metal routing can improve the capability of the common electrodes of the two main/sub-pixel areas of being capable of restoring voltage after being coupled by the data lines, and the horizontal series winding is optimized. In addition, the common electrodes of the two main/sub-pixel areas are connected through grid metal wiring, so that the sub-pixels of red, green and blue can keep the same data voltage under the same gray scale without cutting down, the charge rate difference of positive and negative frames of each sub-pixel is reduced, the data coupling of the two main/sub-pixel areas is the same, the problems of vertical crosstalk (V-CT) and shaking marks (Mura) are optimized, and the taste and the display performance of the display panel are optimized.

Drawings

In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a sub-pixel in a conventional pixel unit;

FIG. 2A is a schematic diagram of a red and green sub-pixel structure in an array substrate according to the present invention;

FIG. 2B is a schematic view of a blue sub-pixel structure in the array substrate according to the present invention;

FIG. 3 is a schematic diagram of an equivalent circuit in which each row of sub-pixels in the array substrate employs three TFTs (3T +);

fig. 4 is a schematic cross-sectional view of a blue sub-pixel structure in an array substrate according to the present invention, which employs a mesh metal trace (mesh _ com); and

fig. 5 is a schematic structural diagram of the distribution of each sub-pixel array in the array substrate of the invention.

Detailed Description

Reference in the detailed description to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the same phrases in various places in the specification are not necessarily limited to the same embodiment, but are to be construed as independent or alternative embodiments to other embodiments. In light of the disclosure of the embodiments provided by the present invention, it should be understood by those skilled in the art that the embodiments described in the present invention can have other combinations or variations consistent with the concept of the present invention.

As shown in fig. 2A to 5, the present invention provides an array substrate 100 including a plurality of sub-pixels 110 arranged in an array, each sub-pixel 110 is formed by cyclically arranging sub-pixels 110 of three colors of red, green and blue (RGB), and the cyclic arrangement sequence of the sub-pixels 110 in each row is the same. Each sub-pixel 110 is divided into a main pixel area 112 and a sub-pixel area 114, and a scan line Gate is respectively disposed corresponding to each row of the sub-pixels 110, and the scan line Gate is disposed between the main pixel area 112 and the sub-pixel area 114. One Data line Data is respectively arranged corresponding to each column of the sub-pixels 110. Each row of the sub-pixels 110 further includes a main region thin film transistor T1 and a sub-region thin film transistor T2, the main region thin film transistor T1 includes connecting the main region pixel electrode 120 with the first common electrode 116(Acom) through the first via hole 122, and the sub-region thin film transistor T2 includes connecting the second common electrode 118(Acom) of the sub-region pixel electrode 130 through the second via hole 124.

Specifically, as shown in fig. 2A and 5, the main pixel region 112 receives a scan signal from the scan line Gate, a Data signal from the Data line Data, and an atom signal from the first common electrode 116 to have a voltage of the main pixel electrode 120. The sub-pixel region 114 is a non-display region receiving the scan signal from the scan line Gate, the Data signal from the Data line Data, and the atom signal from the second common electrode 118, so as to have a voltage of the sub-pixel electrode 120 different from a voltage of the main pixel electrode 120, wherein the first common electrode 116 and the second common electrode 118 are disposed outside each sub-pixel 110.

Each of the sub-pixels 110 further includes a first capacitor Cst _ main, a liquid crystal capacitor Clc _ main of the main pixel region 112, a liquid crystal capacitor Clc _ sub of the sub-pixel region, and a second capacitor Cst _ sub, wherein the first capacitor Cst _ main is a storage capacitor of the main pixel region 112 and is formed by a storage electrode of the main pixel region 112 and an opposite first common electrode 116 (atom). The second capacitor Cst _ sub is a storage capacitor of the sub-pixel region, and is formed by the storage electrode of the sub-pixel region 114 and the opposite second common electrode 118 (Acom). Each row of the sub-pixels 110 further includes a shared thin film transistor T3 between the main pixel region 112 and the sub-pixel region 114, and a shared metal trace 150(share _ bar) disposed on the vertical trunk of the sub-pixel electrode 130. The third Gate of the shared thin film transistor T3 is connected to the scan line Gate, the third source is connected to the Data line Data, and the third drain is connected to the shared metal trace 150. The liquid crystal capacitor Clc _ main of the main pixel region 112 and the liquid crystal capacitor Clc _ sub of the sub pixel region are conventional thin film transistor structures, and are not described herein again.

Since the array substrate 100 of the embodiment adopts the three thin film transistors (3T +) and the 8-domain sub-pixel structure, compared to the existing three thin film transistors (3T), the potential of the sub-pixel electrode 130 is leaked through the shared metal trace 150(share _ bar), also called M2, disposed on the vertical trunk of the sub-pixel electrode 130, so that the potential of the sub-pixel electrode 130 is lower than the potential of the main pixel electrode 120 to form a voltage difference, thereby reducing the risk of vertical crosstalk (V-crosstalk), and therefore, the sub-pixel 110 of the embodiment adopts the three thin film transistors (3T +) to optimize the RGB color itself with a Low Color Shift (LCS) and improve the Transmittance (Tr%). Compared with the existing 3T pixel structure, the shared metal trace 150(M2) of the present embodiment also has the advantages of reducing space occupation ratio and reducing parasitic capacitance (parasitic capacitance).

As shown in fig. 2B and fig. 5, different from the sub-pixels 110 of each row RG color, the sub-pixels 110 of each row B color further include grid metal wires 140(Mesh _ com) connecting the first common electrode 116 of the main pixel electrode 120 and the second common electrode 118 of the sub-pixel electrode 130 which are adjacent to each other, so as to optimize the display performance of each sub-pixel 110 of each B color. The grid metal routing 140 crosses the scan line Gate of the sub-pixel 110 of each row B color and connects the first common electrode 116 of the main pixel electrode 120 and the second common electrode 118 of the sub-pixel electrode 130 through a third via 126 and a fourth via 128.

In the embodiment shown in fig. 5, the liquid crystal display further includes a substrate 102, a Gate insulating layer 104 disposed on the first common electrode 116, the second common electrode 118 and the scan line Gate (i.e., M1), and a passivation layer 106 disposed on the grid metal trace 140. The first and

second via holes

122 and 124 are deeper than the third and

fourth via holes

126 and 128, and the first and second

common electrodes

116 and 118 are disposed at the same layer as the scan line Gate (M1). The first common electrode 116, the second common electrode 118 and the scan line Gate (M1) may be formed by the same process, and the material thereof may include any one of titanium (Ti), molybdenum (Mo), tantalum (Ta) and niobium (Nb), for example. The material of the shared metal trace 150(M2) and the grid metal trace 140 may be made of any one of Cu, Al, and Ag, for example. The main pixel electrode 120 of the main pixel region 112 and the sub pixel electrode 130 of the sub pixel region 114 may be made of Indium Tin Oxide (ITO).

It should be noted that, when the sub-pixels 110 of the array substrate 100 adopt a stripe (Strip) pixel arrangement manner, the grid metal routing (Mesh com) of the embodiment connects the first common electrode 116 (atom) and the second common electrode 118 (atom) of the main pixel region 112 and the sub-pixel region 114, so as to improve the capability of the first common electrode 116 (atom) and the second common electrode 118 (atom) of being capable of recovering voltage after being coupled by the Data line Data, thereby achieving the purpose of optimizing horizontal serial winding (H-CT), display performance and improving moving patterns (Mura).

Furthermore, due to the color gamut of the RGB color sub-pixels 110, a cut-down is required during white balance, so that the voltage-transmission (V-T) curves (i.e. the curves of light transmittance varying with voltage) of the RGB color sub-pixels 110 are different. Generally, in 256 gray levels (8bit), for example, 255/255/240 (original 256/256/256) is applied to the RGB sub-pixels 110 after being cut down, in this case, different Data voltages of RG and B under the same gray level are applied, charging rate differences are caused by cutting down the levels in positive and negative frames, Data coupling to the Data lines of the sub-pixels 110 is also different, and the sub-pixel 110 of the B color is separately implemented by using a three-thin-film transistor (3T +) and a Mesh metal trace 140(Mesh com) structure according to the present embodiment, and through a functional relationship from color to black and white, the functional relationship is: and Lv-f (gray), wherein the function is f, L is a function value, RGB L255-f (255) and L240-f (240) are set, so that the voltages of the final RGB sub-pixels 110 at the same gray scale are the same, and thus the problems of optimizing the vertical crosstalk (V-CT) and the wobbling (Mura) are realized without cutting down the scale. Therefore, the taste and the display performance of the picture display can be optimized.

Referring to fig. 2A and 2B together, since the sub-pixels 110 of each row B color further employ Mesh metal routing 140(Mesh _ com) connecting the first common electrode 116 and the second common electrode 118, an Aperture Ratio (AR%) of the sub-pixels 110 of each row B color is smaller than an Aperture Ratio of the sub-pixels 110 of each row RG color, for example, between 1% and 10%. The pixel area of the sub-pixel 110 of each row B color is smaller than the pixel area of the sub-pixel 110 of each row RG color. However, in other alternative embodiments, the pixel area of the sub-pixel 110 of the color of row B can be designed to be equal to the pixel area of the sub-pixel 110 of the color of row RG, and can be changed as needed.

The invention further provides a display panel, which includes the array substrate 100 and a color filter substrate (not shown) as described in the foregoing embodiments, and a liquid crystal layer (not shown) located between the array substrate 100 and the color filter substrate. For the detailed structure and function of the array substrate 100, please refer to the above embodiments, and in addition, since the color film substrate and the liquid crystal layer are both in the prior art, further description is omitted here.

In the present embodiment, each sub-pixel 110 of the B color is separately designed from each sub-pixel 110 of the RG color by using the Mesh _ com of the Mesh metal routing 140(Mesh _ com) connecting the first common electrode 116(Acom) and the second common electrode 118(Acom) of the main pixel region 112 and the sub-pixel region 114, so that the Mesh metal routing can improve the capability of the

common electrodes

116 and 118 of the two main/sub-pixel regions that can recover voltage after being coupled by the data line, and optimize horizontal series winding. In addition, the

common electrodes

116 and 118 of the two main/sub-pixel regions are connected through the grid metal wiring 140, so that the sub-pixels 110 of RGB colors can be kept the same data voltage under the same gray scale without cutting down, the difference of positive and negative frame charging rates of the sub-pixels 110 is reduced, and the data coupling of the two main/sub-pixel regions is the same, thereby optimizing the problems of vertical crosstalk (V-CT) and wobbling (Mura), and realizing the optimization of the taste and the display performance of the display panel.

In view of the foregoing, while the present invention has been described in conjunction with specific embodiments thereof, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the scope of the included claims.

Claims

1. An array substrate, comprising:

the array-arranged red, green and blue sub-pixels are arranged in a circular mode, each sub-pixel is divided into a main pixel area and a sub-pixel area, a scanning line is arranged corresponding to each row of sub-pixels and is arranged between the main pixel area and the sub-pixel areas, and a data line is arranged corresponding to each column of sub-pixels; and

every line the sub-pixel still includes main district's thin film transistor and subregion thin film transistor, main district's thin film transistor is including being connected main district pixel electrode and first common electrode through first via hole, subregion thin film transistor is including being connected the second common electrode of subregion pixel electrode through the second via hole, wherein, blue in each line in the sub-pixel, still include with two adjacent main district pixel electrode first common electrode with the grid metal routing that the second common electrode of subregion pixel electrode is connected.

2. The array substrate of claim 1, wherein the grid metal trace crosses over the scan lines of the rows of blue sub-pixels and connects the first common electrode of the primary pixel electrode and the second common electrode of the secondary pixel electrode through a third via and a fourth via.

3. The array substrate of claim 2, wherein the first via hole and the second via hole are deeper than the third via hole and the fourth via hole, and the first common electrode, the second common electrode and the scan line are disposed at the same layer.

4. The array substrate of claim 2, further comprising a substrate, a gate insulating layer disposed on the first common electrode, the second common electrode and the scan line, and a passivation layer disposed on the grid metal trace.

5. The array substrate of claim 1, wherein the aperture ratio of the sub-pixels of each row of blue is smaller than the aperture ratio of the sub-pixels of each row of red and green, and the pixel area of the sub-pixels of each row of blue is smaller than or equal to the pixel area of the sub-pixels of each row of red and green.

6. The array substrate of claim 5, wherein the aperture ratio of the blue sub-pixels in each row is less than the aperture ratio of the red sub-pixels in each row by 1% to 10%.

7. The array substrate of claim 1, wherein each row of the sub-pixels further comprises a shared thin film transistor between the main pixel region and the sub-pixel region and a shared metal trace disposed on a vertical trunk of the sub-pixel electrode.

8. The array substrate of claim 1, wherein a third gate of the shared thin film transistor is connected to the scan line, a third source is connected to the data line, and a third drain is connected to the shared metal trace.

9. The array substrate of claim 1, wherein the sub-pixel further comprises a first capacitor and a second capacitor, the first capacitor is a storage capacitor of the main pixel region and is formed by a storage electrode of the main pixel region and an opposite common electrode; the second capacitor is a storage capacitor of the sub-pixel area and is formed by a storage electrode of the sub-pixel area and an opposite common electrode.

10. A display panel comprising the array substrate and the color filter substrate according to any one of claims 1 to 9, and a liquid crystal layer located between the array substrate and the color filter substrate.