CN113726313A - Multi-chip system, chip and clock synchronization method - Google Patents

Multi-chip system, chip and clock synchronization method Download PDF

Info

Publication number
CN113726313A
CN113726313A CN202010449155.9A CN202010449155A CN113726313A CN 113726313 A CN113726313 A CN 113726313A CN 202010449155 A CN202010449155 A CN 202010449155A CN 113726313 A CN113726313 A CN 113726313A
Authority
CN
China
Prior art keywords
clock signal
symbol clock
symbol
chip
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010449155.9A
Other languages
Chinese (zh)
Inventor
张秉彝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Realtek Semiconductor Corp
Original Assignee
Realtek Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Realtek Semiconductor Corp filed Critical Realtek Semiconductor Corp
Priority to CN202010449155.9A priority Critical patent/CN113726313A/en
Publication of CN113726313A publication Critical patent/CN113726313A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs

Abstract

The multichip system comprises a first chip and a second chip. The first chip is used for generating a first symbol clock signal according to a first clock signal from a first oscillator. The second chip is used for generating a second symbol clock signal according to a second clock signal from the second oscillator, detecting a difference between the second symbol clock signal and the first symbol clock signal to generate an error signal, and synchronizing the first symbol clock signal and the second symbol clock signal according to the error signal.

Description

Multi-chip system, chip and clock synchronization method
Technical Field
The present invention relates to a multichip system, and more particularly, to a slave chip and clock synchronization method in a multichip system.
Background
In multichip systems, the clocks between multiple chips need to be synchronized with each other to ensure that data and/or instructions can be received correctly. In the current technology, multiple chips share the clock signal generated by the same oscillator. However, as the number of chips in a multichip system increases, the difficulty of circuit wiring design increases, which makes it difficult to implement the circuit wiring design.
Disclosure of Invention
In some embodiments, the multichip system includes a first chip and a second chip. The first chip is used for generating a first symbol (symbol) clock signal according to a first clock signal from a first oscillator. The second chip is used for generating a second symbol clock signal according to a second clock signal from the second oscillator, detecting a difference between the second symbol clock signal and the first symbol clock signal to generate an error signal, and synchronizing the first symbol clock signal and the second symbol clock signal according to the error signal.
In some embodiments, a chip includes synchronization circuitry, a sample clock generation circuit, and a symbol clock generation circuit. The synchronization circuitry is configured to detect a difference between a first symbol clock signal and a second symbol clock signal to generate an error signal, wherein the first symbol clock signal is generated from a first clock signal of a first oscillator via a master chip. The sampling clock generating circuit is used for generating a sampling clock signal according to a second clock signal from the second oscillator and the error signal. The symbol clock generating circuit is used for generating a second symbol clock signal which is synchronous with the first symbol clock signal according to the sampling clock signal.
In some embodiments, the clock synchronization method includes the following operations: receiving a first symbol clock signal from a master chip, wherein the master chip is configured to generate the first symbol clock signal according to a first clock signal from a first oscillator; generating a second symbol clock signal according to a second clock signal from a second oscillator; and detecting a difference between the second symbol clock signal and the first symbol clock signal to generate an error signal, and adjusting the second symbol clock signal according to the error signal to synchronize the second symbol clock signal with the first symbol clock signal.
The features, operation and effects of the present invention will be described in detail with reference to the accompanying drawings and preferred embodiments.
Drawings
FIG. 1 is a schematic diagram of a multichip system according to some embodiments of the invention;
FIG. 2 is a schematic diagram depicting the synchronization circuitry of FIG. 1, in accordance with some embodiments of the invention;
FIG. 3A is a waveform diagram depicting the correlation signal of FIG. 2 according to some embodiments of the present invention;
FIG. 3B is a waveform diagram depicting the correlation signal of FIG. 2 according to some embodiments of the present invention; and
fig. 4 is a flow chart depicting a method of clock synchronization according to some embodiments of the present invention. .
Description of the symbols:
100: multichip system
101. 103: oscillator
110. 120: chip and method for manufacturing the same
112. 122: phase-locked loop circuit
114. 124: sampling clock generating circuit
116. 126: symbol clock generating circuit
128: synchronous circuit system
CLK1, CLK 2: clock signal
f1, f 2: frequency of
Serr: error signal
Ssy1、Ssy2: system clock signal
Ssa1、Ssa2: sampling clock signal
Ssb1、Ssb2: symbol clock signal
202: phase detector circuit
204: loop filter circuit
Scnt: count value
P1-P2: front edge
1-5, -1 to-5: count value
400: clock synchronization method
S410, S420 and S430: operation of
Detailed Description
All words used herein have their ordinary meaning. The definitions of the above-mentioned words in commonly used dictionaries, any use of the examples in the context of this invention that include any word discussed herein, is intended to be exemplary only and should not be construed as limiting the scope and meaning of the invention. As such, the present invention is not limited to the various embodiments shown in the description herein.
As used herein, "about" or "approximately" generally means within about twenty percent, preferably within about ten percent, and more preferably within about five percent of the error or range of the numerical value. Unless otherwise indicated, all numbers expressing quantities of ingredients, and so forth used herein are to be understood as being approximate, i.e., error or range, as indicated by the word "about".
As used herein, the term "couple" or "connect" refers to two or more elements being in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or to the operation or action of two or more elements being operated with each other. As used herein, the term "circuitry" may be a single system formed by at least one circuit (circuit), and the term "circuitry" may be a device connected by at least one transistor and/or at least one active and passive component in a manner to process a signal.
As used herein, the term "and/or" includes any combination of one or more of the associated listed items. The terms first, second, third and the like are used herein to describe and distinguish between various components. Thus, a first component may also be referred to herein as a second component without departing from the spirit of the invention. For ease of understanding, similar components in the various figures will be designated with identical reference numerals.
Fig. 1 is a schematic diagram of a multichip system 100 according to some embodiments of the invention. In some embodiments, the multichip system 100 may be applied to, but not limited to, a Digital Storage Oscilloscope (DSO) or a communication device installed in different rooms.
Multichip system 100 includes oscillator 101, oscillator 103, chip 110, and chip 120. The oscillators 101 and 103 are two different oscillators, which respectively generate the clock signal CLK1 and the clock signal CLK 2. In some embodiments, oscillator 101 and oscillator 103 may be, but are not limited to, quartz oscillators. In this example, chip 110 operates as a master chip and chip 120 operates as a slave chip. To ensure that data and/or commands can be exchanged correctly, a clock signal (e.g., symbol clock signal S) of the chip 120sb2) Is set to be synchronous with the clock signal of the chip 110 (e.g. the symbol clock signal S)sb1). The chip 110 is coupled to the oscillator 101 for receiving the clock signal CLK1 and generating the symbol clock signal S according to the clock signal CLK1sb1. The chip 120 is coupled to the chip 110 and the oscillator 103 to receive the symbol clock signal S respectivelysb1And a clock signal CLK 2. Chip 120 according to timeThe clock signal CLK2 generates a symbol clock signal Ssb2And detecting the symbol clock signal Ssb2And a symbol clock signal Ssb1To generate an error signal SerrAccording to the error signal SerrAdjusting a symbol clock signal Ssb2. In this way, the symbol clock signal Ssb2Can be associated with the symbol clock signal Ssb1Synchronization is maintained.
The following paragraphs will describe various embodiments of the chip 110 and/or the chip 120, but the invention is not limited to the following embodiments.
As shown in fig. 1, the chip 110 includes a phase-locked loop circuit 112, a sampling clock generation circuit 114, and a symbol clock generation circuit 116. The PLL circuit 112 generates a system clock signal S according to a clock signal CLK1sy1. In some embodiments, the PLL circuit 112 is controlled based on a negative feedback mechanism (not shown) to provide the system clock signal Ssy1In synchronization with the clock signal CLK 1. In some embodiments, the pll circuitry 112 may include, but is not limited to, a phase detector circuit (not shown), a low pass filter circuit (not shown), a vco circuit (not shown), and/or a divider circuit (not shown), wherein the aforementioned circuits may be configured as the aforementioned negative feedback mechanism.
The sampling clock generating circuit 114 is coupled to the PLL circuit 112 for receiving the system clock signal Ssy1. The sampling clock generation circuit 114 generates a system clock signal S according to the sampling clock signalsy1Generating a sampling clock signal Ssa1. In some embodiments, the sampling clock generation circuit 114 may include, but is not limited to, a delay circuit (not shown), a multiplexer circuit (not shown), and/or a phase interpolator circuit (not shown). The delay circuit can delay the system clock signal Ssy1To generate a plurality of clock signals having different phases. The multiplexer circuit may select at least two of the plurality of clock signals to generate a plurality of output signals and provide the output signals to the phase interpolator circuit. The phase interpolator circuit can generate a sampling clock signal S based on a plurality of output signalssa1. The above arrangement of the sampling clock generating circuit 114 is used for illustration, but the invention is not limited thereto. In other embodiments, the sampling clock generation circuit 114 may be an all-digital phase-locked loop.
The symbol clock generating circuit 116 is coupled to the sampling clock generating circuit 114 for receiving the sampling clock signal Ssa1. The symbol clock generating circuit 116 generates a symbol clock signal S according to the sampling clock signal Ssa1Generating a symbol clock signal Ssb1. In some embodiments, the sampling clock signal Ssa1For setting the time interval between a plurality of data samples (i.e. setting the data sampling rate), and a symbol clock signal Ssb1For setting the period of time for the chip 110 to process a data. In some embodiments, the sampling clock signal Ssa1Has a frequency higher than the symbol clock signal Ssb1Of (c) is detected. In some embodiments, the symbol clock generation circuit 116 may be implemented by, but is not limited to, a frequency divider circuit.
The chip 120 includes a phase-locked loop circuit 122, a sampling clock generation circuit 124, a symbol clock generation circuit 126, and synchronization circuitry 128. The PLL circuit 122 generates a system clock signal S according to a clock signal CLK2sy2. In some embodiments, the PLL circuit 122 is configured in a manner similar to that of the PLL circuit 112. In some embodiments, the phase-locked loop circuit 122 does not receive the clock signal CLK1 from the oscillator 101.
The sampling clock generating circuit 124 is coupled to the PLL circuit 122 for receiving the system clock signal Ssy2. The sampling clock generation circuit 124 generates a system clock signal S according to the system clock signalsy2Generating a sampling clock signal Ssa2. In some embodiments, the sample clock generation circuit 124 is arranged in a manner similar to the sample clock generation circuit 122.
The symbol clock generating circuit 126 is coupled to the sampling clock generating circuit 124 for receiving the sampling clock signal Ssa2. The symbol clock generating circuit 126 generates a symbol clock signal S according to the sampling clock signal Ssa2Generating a symbol clock signal Ssb2. In some embodiments, the sampling clock signal Ssa2For setting the time interval between a plurality of data samples, and a symbol clock signal Ssb2For setting the period of time for the chip 120 to process a data. In some embodiments, the sampling clock signalNumber Ssa2For sampling data, and the duration of one symbol in the sampled and recovered data is equivalent to the symbol clock signal Ssb2The duty cycle of (a). In some embodiments, as shown in FIG. 1, the clock signal S is sampledsa2Frequency f of1Higher than the symbol clock signal Ssb2Frequency f of2. In some embodiments, the sampling clock signal Ssa2Frequency f of1May be approximately a symbol clock signal Ssb2Frequency f of264-8192 times of the total weight of the total. In some embodiments, the symbol clock generation circuit 126 may be implemented by, but is not limited to, a frequency divider circuit.
The synchronization circuitry 128 is coupled to the chip 110 to receive the symbol clock signal Ssb1And coupled to the symbol clock generating circuit 126 for receiving the symbol clock signal Ssb2And is coupled to the PLL circuit 122 for receiving the system clock signal Ssy2. The synchronization circuitry 128 detects the symbol clock signal Ssb1And a symbol clock signal Ssb2To generate an error signal Serr. For example, the synchronization circuitry 128 clocks the signal S according to the symbolsb1And a symbol clock signal Ssb2For system clock signal Ssy2Is counted to generate an error signal Serr. For example, the synchronization circuitry 128 clocks the signal S according to the symbolsb1And a symbol clock signal Ssb2Starts counting the at least one pulse wave, e.g. a signal with a leading phase, and is based on the symbol clock signal Ssb1And a symbol clock signal Ssb2The other stops counting the at least one pulse wave. Some embodiments and operations of the synchronization circuitry 128 will be described with reference to fig. 2, 3A, and 3B.
In some embodiments, the sampling clock generation circuit 124 is further configured to generate the error signal S according to the error signal SerrAdjusting the sampling clock signal Ssa2. Accordingly, the symbol clock generating circuit 126 can generate the adjusted sampling clock signal S according to the adjusted sampling clock signal Ssa2Updating the symbol clock signal Ssb2. In this way, the symbol clock signal Ssb2Holdable and symbolic clock signal Ssb1And (6) synchronizing. For example, the sampling clock generation circuit 124 may include, but is not limited to, a delay circuit (not shown), a multiplexer circuit (not shown), and/or a phase interpolator circuit (not shown). The delay circuit can delay the system clock signal Ssy2To generate a plurality of clock signals having different phases. The multiplexer circuit can be based on the error signal SerrAt least two of the plurality of clock signals are selected to generate a plurality of output signals, and the output signals are provided to a phase interpolator circuit. The phase interpolator circuit can generate a sampling clock signal S based on a plurality of output signalssa2. The above arrangement of the sampling clock generating circuit 124 is used for example, but the invention is not limited thereto.
It should be understood that the number of chips shown in fig. 1 is for illustration and the invention is not limited thereto. In one or more embodiments, the number of chips in the multichip system 100 may be two or more.
In some related art, the chips in a multichip system share the same oscillator to achieve clock synchronization. In these techniques, when the number of chips increases, an additional buffer circuit is required to be added between the oscillator and the chip to improve the driving capability of the oscillator. However, the extra buffer will cause difficulty in the layout of the multichip system on the circuit board and will cause a significant increase in the overall cost.
In contrast to the related art, in some embodiments of the present invention, different oscillators (e.g., oscillator 101 and oscillator 103) are used for the chips (e.g., chip 110 and chip 120), and one of the chips (e.g., chip 120 operating as a slave chip) can be clocked according to a signal generated by another of the chips (e.g., chip 110 operating as a master chip). Therefore, the number of buffer circuits can be reduced and the difficulty of wiring design can be reduced.
Fig. 2 is a schematic diagram depicting the synchronization circuitry 128 of fig. 1, in accordance with some embodiments of the invention. Synchronization circuitry 128 includes phase detector circuitry 202 and loop filter circuitry 204. The phase detector circuit 202 is responsive to the symbol clock signal Ssb1And a symbol clock signal Ssb2For system clock signal Ssy2Is counted to generate a count value Scnt. The loop filter circuit 204 is coupled to the phase detector circuit 202 for receiving the counting value Scnt. Loop filter circuit 204 counts value ScntFiltering to generate an error signal Serr. In some embodiments, the phase detector circuit 202 may include, but is not limited to, a flip-flop circuit (not shown) and/or a counter circuit (not shown), the operation of which will be described later with reference to fig. 3A and 3B. In some embodiments, the loop filter circuit 204 may be a low pass filter circuit.
Fig. 3A is a waveform diagram plotting the correlation signals of fig. 2 according to some embodiments of the present invention. In this example, the symbol clock signal Ssb1Is ahead of the symbol clock signal Ssb2The phase of (c). As shown in fig. 3A, the symbol clock signal Ssb1Has a positive edge P1 earlier than the symbol clock signal Ssb2Positive edge P2. The phase detector circuit 202 is responsive to the symbol clock signal Ssb1Is triggered to start the system clock signal Ssy2Is counted to generate a count value ScntAnd according to a symbol clock signal Ssb2Positive edge P2 of the clock signal to stop the system clock signal Ssy2Is counted. Thus, the phase detector circuit 202 can detect the symbol clock signal Ssb1And a symbol clock signal Ssb2The difference between them is equivalent to 5 pulses and outputs the count value ScntIs 5.
Fig. 3B is a waveform diagram plotting the correlation signals of fig. 2 according to some embodiments of the present invention. In this example, the symbol clock signal Ssb1Is behind the symbol clock signal Ssb2The phase of (c). As shown in fig. 3B, the symbol clock signal Ssb2Has a positive edge P2 earlier than the symbol clock signal Ssb1Positive edge P1. The phase detector circuit 202 is responsive to the symbol clock signal Ssb2Is triggered to start the system clock signal Ssy2Is counted to generate a count value ScntAnd according to the symbol clock signalSsb1Positive edge P1 of the clock signal to stop the system clock signal Ssy2Is counted. Thus, the phase detector circuit 202 can detect the symbol clock signal Ssb1And a symbol clock signal Ssb2The difference between them is equivalent to 5 pulses and outputs the count value ScntIs-5 (negative values are used to indicate the symbol clock signal Ssb1Is behind the symbol clock signal Ssb2Phase (d) of the phase.
Fig. 4 is a flow chart depicting a method 400 of clock synchronization according to some embodiments of the present invention. In some embodiments, the clock synchronization method 400 may be performed by, but is not limited to, the chip 120 of fig. 1 (operating as a slave chip).
In operation S410, a first symbol clock signal is received from a master chip, wherein the master chip generates the first symbol clock signal according to the first clock signal from a first oscillator. In operation S420, a second symbol clock signal is generated according to a second clock signal from a second oscillator. In operation S430, a difference between the second symbol clock signal and the first symbol clock signal is detected to generate an error signal, so as to adjust the second symbol clock signal according to the error signal to synchronize the second symbol clock signal with the first symbol clock signal.
The above description of the operations of the clock synchronization method 400 can refer to the above embodiments, and therefore, the description thereof is omitted here. The above operations are merely examples, and need not be performed in the order in this example. The various operations under the clock synchronization method 400 may be added, substituted, omitted, or performed in a different order, as appropriate, without departing from the manner and scope of operation of various embodiments of the invention. Alternatively, one or more operations under the clock synchronization method 400 may be performed simultaneously or partially simultaneously.
In summary, according to the multi-chip system, the chip and the clock synchronization method in some embodiments of the invention, a plurality of chips can perform clock synchronization using different oscillators. Therefore, the number of the buffer circuits can be reduced, and the difficulty of wiring design can be reduced.
Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art can make changes and modifications to the technical features of the present invention according to the contents explicitly or implicitly included in the present invention, but all changes and modifications can be made within the scope of the present invention.

Claims (10)

1. A multichip system, the multichip system comprising:
a first chip for generating a first symbol clock signal according to a first clock signal from a first oscillator; and
and the second chip is used for generating a second symbol clock signal according to a second clock signal from a second oscillator, detecting the difference between the second symbol clock signal and the first symbol clock signal to generate an error signal, and synchronizing the first symbol clock signal and the second symbol clock signal according to the error signal.
2. The multichip system of claim 1, wherein the second chip comprises:
the phase-locked loop circuit is used for generating a system clock signal according to the second clock signal;
synchronization circuitry to count at least one pulse in the system clock signal according to the first symbol clock signal and the second symbol clock signal to generate the error signal;
a sampling clock generating circuit for generating a sampling clock signal according to the system clock signal and the error signal; and
a symbol clock generating circuit for generating the second symbol clock signal synchronized with the first symbol clock signal according to the sampling clock signal.
3. The multichip system of claim 2, wherein the synchronization circuitry is further to start counting the at least one pulse wave based on one of the first symbol clock signal and the second symbol clock signal and stop counting the at least one pulse wave based on the other of the first symbol clock signal and the second symbol clock signal.
4. The multichip system of claim 2, wherein the synchronization circuitry comprises:
a phase detection circuit for counting the at least one pulse wave according to the first symbol clock signal and the second symbol clock signal to generate a count value; and
a loop filter circuit for filtering the count value to generate the error signal.
5. The multichip system of claim 2, wherein a frequency of the sampling clock signal is higher than a frequency of the second symbol clock signal.
6. The multichip system of claim 1, wherein the first oscillator is different from the second oscillator.
7. A chip, comprising:
synchronization circuitry to detect a difference between a first symbol clock signal and a second symbol clock signal to generate an error signal, wherein the first symbol clock signal is generated from a first clock signal of a first oscillator via a master chip;
a sampling clock generating circuit for generating a sampling clock signal according to a second clock signal from a second oscillator and the error signal; and
a symbol clock generating circuit for generating the second symbol clock signal synchronized with the first symbol clock signal according to the sampling clock signal.
8. The chip of claim 7, wherein the chip further comprises:
a phase-locked loop circuit for generating a system clock signal based on the second clock signal,
wherein the synchronization circuitry is configured to count at least one pulse in the system clock signal according to the first symbol clock signal and the second symbol clock signal to generate the error signal.
9. The chip of claim 8, wherein the synchronization circuitry comprises:
a phase detection circuit for counting the at least one pulse wave according to the first symbol clock signal and the second symbol clock signal to generate a count value; and
a loop filter circuit for filtering the count value to generate the error signal.
10. A clock synchronization method, comprising:
receiving a first symbol clock signal from a master chip, wherein the master chip is configured to generate the first symbol clock signal according to a first clock signal from a first oscillator;
generating a second symbol clock signal according to a second clock signal from a second oscillator; and
detecting a difference between the second symbol clock signal and the first symbol clock signal to generate an error signal, to adjust the second symbol clock signal according to the error signal to synchronize the second symbol clock signal to the first symbol clock signal.
CN202010449155.9A 2020-05-25 2020-05-25 Multi-chip system, chip and clock synchronization method Pending CN113726313A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010449155.9A CN113726313A (en) 2020-05-25 2020-05-25 Multi-chip system, chip and clock synchronization method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010449155.9A CN113726313A (en) 2020-05-25 2020-05-25 Multi-chip system, chip and clock synchronization method

Publications (1)

Publication Number Publication Date
CN113726313A true CN113726313A (en) 2021-11-30

Family

ID=78671581

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010449155.9A Pending CN113726313A (en) 2020-05-25 2020-05-25 Multi-chip system, chip and clock synchronization method

Country Status (1)

Country Link
CN (1) CN113726313A (en)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020049936A1 (en) * 2000-07-31 2002-04-25 Vadim Gutnik Clock distribution circuits and methods of operating same that use multiple clock circuits connected by phase detector circuits to generate and synchronize local clock signals
US20040104753A1 (en) * 2002-11-28 2004-06-03 Renesas Technology Corp. Semiconductor device capable of accurately producing internal multi-phase clock signal
CN103888136A (en) * 2012-12-20 2014-06-25 澜起科技（上海）有限公司 No-crystal clock generation system of broadcast system-on-chip
US8917806B1 (en) * 2013-10-18 2014-12-23 Richtek Technology Corp Digital phase-locked loop and phase/frequency detector module thereof
US20150180650A1 (en) * 2012-07-25 2015-06-25 Hytera Communications Corp., Ltd. Synchronisation method and device for transmit and receive symbols of all-digital receiver
KR101807850B1 (en) * 2016-12-13 2017-12-11 한림대학교 산학협력단 Multi-Chip System Clock Signal Distribution Synchronization Technology with In-Phase Clock Lines
CN108540108A (en) * 2018-06-27 2018-09-14 宗仁科技(平潭)有限公司 Pierce circuit and IC chip built in a kind of IC
US20190383737A1 (en) * 2018-06-15 2019-12-19 Quantum-Si Incorporated Data acquisition control for advanced analytic instruments having pulsed optical sources

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020049936A1 (en) * 2000-07-31 2002-04-25 Vadim Gutnik Clock distribution circuits and methods of operating same that use multiple clock circuits connected by phase detector circuits to generate and synchronize local clock signals
US20040104753A1 (en) * 2002-11-28 2004-06-03 Renesas Technology Corp. Semiconductor device capable of accurately producing internal multi-phase clock signal
US20150180650A1 (en) * 2012-07-25 2015-06-25 Hytera Communications Corp., Ltd. Synchronisation method and device for transmit and receive symbols of all-digital receiver
CN103888136A (en) * 2012-12-20 2014-06-25 澜起科技（上海）有限公司 No-crystal clock generation system of broadcast system-on-chip
US8917806B1 (en) * 2013-10-18 2014-12-23 Richtek Technology Corp Digital phase-locked loop and phase/frequency detector module thereof
KR101807850B1 (en) * 2016-12-13 2017-12-11 한림대학교 산학협력단 Multi-Chip System Clock Signal Distribution Synchronization Technology with In-Phase Clock Lines
US20190383737A1 (en) * 2018-06-15 2019-12-19 Quantum-Si Incorporated Data acquisition control for advanced analytic instruments having pulsed optical sources
CN108540108A (en) * 2018-06-27 2018-09-14 宗仁科技(平潭)有限公司 Pierce circuit and IC chip built in a kind of IC

Similar Documents

Publication Publication Date Title
US5212716A (en) Data edge phase sorting circuits
US6188286B1 (en) Method and system for synchronizing multiple subsystems using one voltage-controlled oscillator
JPH08125647A (en) Integrated circuit device for precise timing recovery and its method
US9748961B2 (en) Single cycle asynchronous domain crossing circuit for bus data
US7482841B1 (en) Differential bang-bang phase detector (BBPD) with latency reduction
WO2007019339A2 (en) Clock-and-data-recovery system
KR100195855B1 (en) Clock synchronization scheme for fractional multiplication systems
US20160142066A1 (en) Frequency division clock alignment
US6622256B1 (en) System for protecting strobe glitches by separating a strobe signal into pointer path and timing path, filtering glitches from signals on pointer path thereof
JP5286845B2 (en) Data recovery circuit
JP2003224471A (en) Pll circuit and optical communication receiver
US20030112913A1 (en) Generating a lock signal indicating whether an output clock signal generated by a PLL is in lock with an input reference signal
JP3327249B2 (en) PLL circuit
US6982575B2 (en) Clock ratio data synchronizer
EP0897229B1 (en) Clock recovery circuit
JP4293840B2 (en) Test equipment
CN113726313A (en) Multi-chip system, chip and clock synchronization method
TWI226774B (en) Clock and data recovery circuit
US7664166B2 (en) Pleisiochronous repeater system and components thereof
TWI743791B (en) Multi-chip system, chip, and clock synchronization method
US7023944B2 (en) Method and circuit for glitch-free changing of clocks having different phases
US6606361B1 (en) Circuits, systems, and methods for providing a single output clock and output data stream from an interface having multiple clocks and an input data stream
US20040223574A1 (en) Phase frequency detector used in digital PLL system
US6617904B1 (en) Electronic circuit with clock generating circuit
EP0572135B1 (en) State machine phase lock loop

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination