CN113726311B - Pulse signal filter circuit and electronic equipment - Google Patents
Pulse signal filter circuit and electronic equipment Download PDFInfo
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Abstract
The application discloses pulse signal filter circuit and electronic equipment. The pulse signal filtering circuit comprises an input buffer control logic circuit and at least one filtering unit circuit; the filtering unit circuit comprises an input cache circuit, a time domain filtering circuit and a space domain filtering circuit which are connected in sequence; the input cache circuit is connected with the input cache control logic circuit; the input buffer control logic circuit is used for controlling the input buffer circuit to buffer the input pulse signal; the time domain filtering circuit is used for performing time domain filtering on the data from the input cache circuit; the spatial filtering circuit is used for carrying out spatial filtering on the data from the time domain filtering circuit. The pulse signal filtering circuit comprises the multi-path filtering unit circuit, multi-path parallel filtering of pulse signals can be achieved, power consumption of pulse filtering is reduced, information processing speed and throughput are improved, the size and power consumption of the circuit are reduced, and the requirements of practical application can be well met.
Description
Technical Field
The application relates to the technical field of signal processing, in particular to a pulse signal filter circuit and electronic equipment.
Background
The nerve pulse signal is a basic carrier for sensing, transmitting and processing information by biological neurons, and has the advantages of small information storage capacity, high calculation energy efficiency and the like. The bionic pulse signal simulates a calculation mode of a biological neuron to process information by the bionic pulse signal. Technicians have been working on optimizing the biomimetic pulse signal processing process in order to improve information processing speed and throughput.
Disclosure of Invention
The application aims to provide a pulse signal filter circuit and electronic equipment. The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.
According to an aspect of an embodiment of the present application, there is provided a pulse signal filtering circuit, including an input buffer control logic circuit and at least one filtering unit circuit; the filtering unit circuit comprises an input cache circuit, a time domain filtering circuit and a space domain filtering circuit which are connected in sequence; the input cache circuit is connected with the input cache control logic circuit;
the input buffer control logic circuit is used for controlling the input buffer circuit to buffer the input pulse signal;
the time domain filtering circuit is used for performing time domain filtering on the data from the input cache circuit;
the spatial filtering circuit is used for carrying out spatial filtering on the data from the time domain filtering circuit.
In some embodiments of the present application, the input buffer circuit includes a data selector, a buffer and a buffer block, a first input end of the data selector receives the pulse signal, an output end of the data selector is connected to an input end of the buffer, and an output end of the buffer is respectively connected to a second input end of the data selector and the buffer block.
In some embodiments of the present application, the time-domain filtering circuit includes a time-domain filtering control logic circuit, and a time memory calculation module, an axon neurotransmitter data processing module, an axon pulse issue probability processing module, a data selector, and a timing filtering output buffer, which are respectively controlled by the time-domain filtering control logic circuit;
the time memory calculation module is used for acquiring time memory data according to the data of the cache block;
the axon pulse issuing probability processing module is used for acquiring axon pulse issuing probability according to the time memory data;
the axon neurotransmitter data processing module is used for acquiring axon neurotransmitter data according to the time memory data and the axon pulse emission probability;
the data selector is used for selecting data meeting a preset time sequence filtering condition according to the data of the cache block and the axon neurotransmitter data;
and the time sequence filtering output buffer is used for storing the data meeting the preset time sequence filtering condition.
In some embodiments of the present application, the time memory calculation module includes a time memory register, a filter selection circuit, and a synaptic decay lookup table, wherein the synaptic decay lookup table is configured to receive data from the time memory register, and the filter selection circuit is configured to adjust and select data from the time memory register, and write the selected data into the time memory register;
the axon impulse sending probability processing module comprises an axon impulse sending probability buffer and a first data adjustment updating circuit, wherein the first data adjustment updating circuit is used for adjusting and updating data in the axon impulse sending probability buffer according to data from the synapse attenuation lookup table;
the axon neurotransmitter data processing module comprises an axon neurotransmitter buffer and a second data adjustment update circuit for adjusting and updating data in the axon neurotransmitter buffer based on data from the synaptic attenuation look-up table and data from the axon impulse firing probability processing module; the data of the second data adjustment updating circuit is input into the data selector.
In some embodiments of the present application, the spatial filtering circuit includes a spatial filtering control logic circuit, and a data reading circuit, a filtering selection circuit, a data buffering accumulation circuit, and a history memory cache circuit, which are respectively controlled by the spatial filtering control logic circuit, and the data reading circuit, the filtering selection circuit, the data buffering accumulation circuit, and the history memory cache circuit are sequentially connected; the history memory cache circuit is connected with the data reading circuit; the data reading circuit is connected with the time sequence filtering output buffer;
the data reading circuit is used for reading the data of the time sequence filtering output buffer;
the filtering selection circuit is used for selecting the data from the data reading circuit and selecting the data meeting the preset condition;
the data buffer accumulation circuit is used for carrying out accumulation calculation on the data meeting the preset airspace filtering condition to obtain a calculation result;
the history memory cache circuit is used for adjusting the calculation result, storing the adjusted calculation result and storing the data of the data reading circuit.
In some embodiments of the present application, the data reading circuit includes an equality discriminator, a row counter, a first comparator and a first data selector connected in sequence, and a column counter, a first comparator and a second data selector connected in sequence, the row counter, the equality discriminator and the first data selector being connected in sequence; the output end of the first data selector is connected with the input end of the second data selector; the input end of the first data selector is connected with the time sequence filtering output buffer.
In some embodiments of the present application, the filter selection circuit includes a weight buffer, a first line pulse buffer, a second line pulse buffer, a third data selector, a fourth data selector, a fifth data selector, and an addition circuit; the addition circuit is configured to sum output data of the third data selector, the fourth data selector, and the fifth data selector; the weight buffer is respectively connected with the input ends of the third data selector, the fourth data selector and the fifth data selector; the second data selector is respectively connected with the first line pulse buffer and the third data selector; the first line pulse buffer is respectively connected with the fourth data selector and the second line pulse buffer; the second line pulse buffer is connected with the fifth data selector.
In some embodiments of the present application, the data buffer accumulation circuit includes a first buffer, a second buffer, a third buffer, and an accumulation circuit configured to calculate a sum of an output value of the first buffer, an output value of the second buffer, and an output value of the third buffer with a history time memory of the history memory buffer circuit, and output a comparison result of the sum with a threshold.
In some embodiments of the present application, the history memory buffer circuit includes a second comparator, a third comparator, a multiplier, a subtractor, a sixth data selector, a seventh data selector, a filtered output buffer block, and a history memory; the history memory is respectively connected with the row counter, the line counter and the sixth data selector; the second comparator is respectively connected with the filtering output cache block and the sixth data selector; the multiplier is connected with the sixth data selector; the seventh data selector is connected with the sixth data selector; the subtracter is respectively connected with the third comparator and the seventh data selector.
In some embodiments of the present application, the pulse signal filtering circuit further comprises a filtering output buffer for storing the data output by the spatial filtering circuit.
According to another aspect of the embodiments of the present application, there is provided an electronic device for performing pulse signal filtering, including the pulse signal filtering circuit described in any one of the above.
The technical scheme provided by one aspect of the embodiment of the application can have the following beneficial effects:
the pulse signal filter circuit provided by the embodiment of the application comprises a multi-path filter unit circuit, multi-path parallel filtering of pulse signals can be achieved, the power consumption of pulse filtering is reduced, the information processing speed and the throughput are improved, the size and the power consumption of the circuit are reduced, and the requirements of practical application can be well met.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the application, or may be learned by the practice of the embodiments. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 shows an architectural block diagram of a pulse signal filtering circuit of one embodiment of the present application;
FIG. 2 shows a block diagram of an input buffer circuit in one embodiment of the present application;
FIG. 3 shows a block diagram of a time domain filtering circuit in one embodiment of the present application;
fig. 4 shows a block diagram of a spatial filtering circuit in an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is further described with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The bionic pulse signal processing process is optimized, and improvement can be performed from two aspects of model optimization and architecture design so as to solve the problems of low energy efficiency and low speed of pulse signal processing in the prior art.
As shown in fig. 1, an embodiment of the present application provides a pulse signal filtering circuit, which includes an input buffer control logic circuit and at least one (25 in this embodiment as an example) filtering unit circuit; the filtering unit circuit comprises an input cache circuit, a time domain filtering circuit, a space domain filtering circuit and a filtering output cache which are connected in sequence; the input cache circuit is connected with the input cache control logic circuit; the input buffer control logic circuit is used for controlling the input buffer circuit to buffer the input pulse signal; the time domain filtering circuit is used for performing time domain filtering on the data from the input cache circuit; the spatial filtering circuit is used for carrying out spatial filtering on the data from the time domain filtering circuit. The filtering output buffer is used for storing the data output by the spatial filtering circuit.
As shown in fig. 2, the external pulse array feeds into 25 input buffer circuits. Each input buffer circuit is connected with a time domain filter circuit and a space domain filter circuit in sequence. And the calculation result of the spatial filtering circuit is sent to a corresponding filtering output buffer. The whole circuit comprises 25 filter unit circuits which operate in parallel. Each two paths of filter unit circuits are independent, and an input cache circuit, a time domain filter circuit and a space domain filter circuit in each path of filter unit circuit operate in a pipeline mode. The number of the filter unit circuits can also adopt other numbers according to actual needs. The circuit structure of parallel processing of the multi-path filter unit circuit can reduce the power consumption of pulse filtering and improve the processing speed and the data throughput.
The input buffer circuit comprises a data selector, a buffer and a buffer block, wherein a first input end of the data selector receives the pulse signal, an output end of the data selector is connected with an input end of the buffer, and an output end of the buffer is respectively connected with a second input end of the data selector and the buffer block.
As shown in fig. 2, the input buffer circuit includes a data selector (MUX), a buffer and a buffer block (ram), an output end of the data selector is connected to an input end of the buffer, and an output end of the buffer is connected to an input end of the data selector and the buffer block, respectively. Wherein the MUX represents a data selector.
External data is input in 64-bit width and is fed into 25 buffer buffers (buffers) in a pipelined mode under control of control logic. Each buffer is 64 bits wide. And after receiving the input data, the buffer starts to shift, each clock cycle moves by one bit, and the shifted data is stored into the buffer through the data selector. Meanwhile, the data at the forefront (lowest bit) of the buffer is written into the buffer block ram under the clock driving. The input of one buffer to the buffer block ram is done every 64 clock cycles. When the last bit of the buffer is written into the buffer block, the control logic writes the new 64-bit data into the buffer. This process is repeated until 100000 bits of burst data are input to the cache block.
The time domain filter circuit comprises a time domain filter control logic circuit, and a time memory calculation module, an axon neurotransmitter data processing module, an axon pulse distribution probability processing module, a data selector and a time sequence filter output buffer which are respectively connected with the time domain filter control logic circuit.
The axon neurotransmitter data processing module and the time memory calculating module are respectively connected with the data selector; the data selector is connected with the time sequence filtering output buffer; the time memory calculation module is connected with the cache block; the time memory calculation module is used for acquiring time memory data according to the data of the cache block; the axon pulse issuing probability processing module is used for acquiring axon pulse issuing probability according to the time memory data; the axon neurotransmitter data processing module is used for acquiring axon neurotransmitter data according to the time memory data and the axon pulse emission probability; the data selector is used for selecting data which accords with a preset time sequence filtering condition according to the data of the cache block and the axon neurotransmitter data; the time sequence filtering output buffer is used for storing data meeting preset time sequence filtering conditions.
The circuit architecture of the time domain filter circuit is shown in fig. 3, and includes a time domain filter control logic circuit, and a time memory calculation module a, an axon neurotransmitter data processing module B, an axon pulse transmission probability processing module C, a data selector 3, and a time sequence filter output buffer, which are respectively connected to the time domain filter control logic circuit. The time domain filtering control logic circuit controls the reading and writing of data, calculation and other links. For clarity, fig. 3 shows the control logic as a single block, while the connections to other circuit parts are omitted. The entire module can run efficiently in pipeline mode.
The time memory calculation module A comprises a MUX1, a MUX2, a comparator 4, a time memory buffer, a synapse attenuation look-up table LUT1-2, a buffer-f, a buffer-d and the like. The MUX1, the MUX2, and the comparator 4 constitute a filter selection circuit. The filtering selection circuit is used for adjusting and selecting data from the time memory buffer, and then writing the selected data into the time memory buffer, and specifically comprises: when the pulse signal from the input buffer circuit is at low level, the data is read from the time memory buffer, and whether the data exceeds the preset maximum value C0 is judged, if not, the read data is added by one and then written into the time memory buffer.
The axon neurotransmitter data processing block B includes an axon neurotransmitter buffer, a buffer 12, a multiplier 6, a multiplier 8, an adder 7, an adder 9, a subtractor 10, an absolute value operator 11, a comparator 5, a threshold memory, and the like. The data output by the axon neurotransmitter buffer is stored in buffer 12. The multiplier 6, the multiplier 8, the adder 7, the adder 9, the subtractor 10, the absolute value arithmetic unit 11, the comparator 5, and the threshold memory constitute a first data adjustment and update circuit for adjusting data from the buffer 12 and updating data in the axon neurotransmitter buffer by using the adjusted data, and specifically includes: the data in the axon neurotransmitter buffer is multiplied by the pulse non-emission probability through a multiplier 6, subtracted by an adder 7, multiplied by the result buffered in buffer-d, and then added by one through an adder 9 to obtain the neurotransmitter variable at the current moment, and the data in the axon neurotransmitter buffer is updated by using the neurotransmitter variable at the current moment.
The axon pulse issuance probability processing module C includes an axon pulse issuance probability buffer, a buffer 13, a buffer 14, an adder 15, a multiplier 16, an adder 17, an adder 18, a multiplier 19, an adder 20, and the like. The buffer 13, the buffer 14, the adder 15, the multiplier 16, the adder 17, the adder 18, the multiplier 19, and the adder 20 constitute a second data adjustment update circuit. The second data adjusting and updating circuit is configured to adjust data in the axon pulse emission probability buffer according to data from the synapse decay lookup table, and update the data in the axon pulse emission probability buffer by using the adjusted data, and specifically includes: reading the pulse transmission probability data of the axon pulse transmission probability buffer at the previous moment, storing the pulse transmission probability data in the buffer 13 at the previous moment in the buffer 14 after taking the inverse number, adding one to the inverse number stored in the buffer 14 through an adder 15, multiplied by a constant C1 through a multiplier 16, added to a constant C2 through an adder 17, added to the pulse delivery probability data at the previous time through an adder 18 to obtain a sum, the sum is multiplied by a synapse timing decay signal by a multiplier 19, the product is added to a constant C3 by an adder 20 to obtain a pulse emission probability at the current time, and the pulse emission probability at the current time is sent to an axon pulse emission probability buffer to update the pulse emission probability data at the previous time in the axon pulse emission probability buffer.
The buffer blocks of the input buffer circuit are respectively connected with one input end of the MUX2 and one input end of the MUX 3; the output end of the MUX2 is connected to the time memory register for writing data into the time memory register to update the data in the time memory register; the outputs of the time memory buffer are respectively connected to the input terminal of the MUX1, one input terminal of the comparator 4 and the synaptic attenuation look-up table LUT1-2, the preset constant C0 is respectively input to one input terminal of the MUX1 and the other input terminal of the comparator 4, the output terminal of the comparator 4 is connected to one input terminal of the MUX1, the output of the MUX1 is added with 1 and then input to one input terminal of the MUX2, and the other input terminal of the MUX2 is input with 1. The output terminal of MUX3 is connected to the time-domain filtering output buffer. The synaptic attenuation look-up table LUT1-2 is connected to two buffers buffer-f and buffer-d, respectively. The lookup result of LUT1-2 is stored in two buffers buffer-f and buffer-d. The axon neurotransmitter buffer is connected with the buffer 12, and one input ends of the buffer 12, the multiplier 6, the adder 7, the multiplier 8, the adder 9, the subtractor 10, the absolute value arithmetic unit 11, the comparator 5 and the MUX3 are sequentially connected; the buffer 12 is connected with the subtracter 10; the threshold value memory is connected with one input end of the comparator 5; the buffer 14, the adder 15, the multiplier 16, the adder 17, the adder 18, the multiplier 19, the adder 20, the axon pulse transmission probability buffer and the buffer 13 are sequentially connected, and the output data of the buffer 13 is input into the buffer 14 after being subtracted by one; the buffer _ f is connected to the multiplier 19; the buffer _ d is connected with the multiplier 8; the buffer 13 is connected to an adder 18. In order to meet the circuit timing requirements, one or more buffers can be added among the functional units of the time memory calculation module A, the axon neurotransmitter data processing module B and the axon pulse transmission probability processing module C.
The time memory calculation module A is used for writing '1' into a time memory cache by the control logic when the input pulse signal is at a high level; when the input pulse signal is at low level, the control logic reads out the result of the time memory buffer, adds one to the result, and then writes the result into the time memory module. The data selector MUX1 may ensure that the time memory does not exceed a preset maximum value (i.e., C0). The read time memory data serves as the lookup index terminal of a single input dual output lookup table circuit (i.e., LUT 1-2). Specific implementations of the circuit include but are not limited to lookup table logic, ram, etc. The search result is stored in two buffers (i.e. buffer-f and buffer-d).
After the data of the axon neurotransmitter buffer is read out, the data is multiplied by the result cached by buffer-d after two operations of multiplication and subtraction of the impulse non-release probability, and then the result is multiplied by one to obtain the neurotransmitter variable at the current moment. This variable is used on the one hand to update the neurotransmitter buffer and on the other hand to compare the amount of neurotransmission in the neurotransmitter buffer at the previous moment, and when the difference exceeds a threshold value, the comparator is triggered to output a pulse. The pulse is stored in a filtered output buffer.
The control logic module controls to read the data of the axon pulse emission probability buffer and input the data into the buffer-u1, and then the inverse number is taken and stored in the buffer-u 2. After "plus one" of the results of buffer-u2, one branch is multiplied by the axon residual transmitter to calculate a new axon transmission mass; the other branch is multiplied by a constant C1, added with a constant C2, added with the pulse emission probability of the previous moment, multiplied by a synaptic time sequence attenuation signal, and added with a constant C3 to obtain the pulse emission probability of the current moment, and the pulse emission probability is sent to an axon pulse emission probability buffer.
The spatial filtering circuit comprises a spatial filtering control logic circuit, and a data reading circuit, a filtering selection circuit and a data buffering accumulation circuit which are respectively controlled by the spatial filtering control logic circuit, wherein the data reading circuit, the filtering selection circuit and the data buffering accumulation circuit are sequentially connected; the data reading circuit is connected with the time sequence filtering output buffer;
the data reading circuit is used for reading the data of the time sequence filtering output buffer;
the filter selection circuit is used for selecting the data from the data reading circuit and selecting the data meeting the preset conditions;
the data buffer accumulation circuit is used for carrying out accumulation calculation on the data meeting the preset conditions and outputting a calculation result.
The calculation compression method adopted by the time domain filter circuit comprises the technical scheme of replacing the exponential operation of a filter model with a lookup table and replacing the floating-point number operation with the fixed-point number operation. The time domain filter circuit is used for realizing a calculation compression method of pulse filtering, and the index operation is replaced by the lookup table operation. The following calculation formula:
from the equations (1) and (2), the time-domain filter circuit needs to calculate the exponential term
And
this results in a large amount of computing resources being consumed and high computing delay. Wherein, Deltat n Is shown asnThe time between the issuance of a pulse at a time step,u n+1，u n ，r n+1andr n representing the probability of neurotransmitter release before and after the current pulse is fired and the remaining amount of neurotransmitter available on the axon.UIndicating an increased amount of neurotransmitter release probability caused by a single action potential.FA time constant representing the decay of the neurotransmitter release to 0 after a single action potential,Dis the time constant for the neurotransmitter residual to return to 1 after a single action potential.u f Is a probability parameter for not delivering a pulse. The embodiments of the present application propose to compute these two terms using a look-up table model. Specifically, the values in equations (1) and (2) are calculated in advance
And
at at n =0,1,2,…,K,K+1,…,NIs stored in a look-up table and then Δ is retrieved as requiredtThe attenuation factor at the time of day.
According to the embodiment of the application, floating point number operation is replaced by fixed point number operation, and the lookup table results in the formulas (1) and (2) are converted into fixed point numbers, so that the storage resource consumption required by the calculation model of the lookup table is reduced. Alternative fixed-point numbers include, but are not limited to, fixed-point numbers of 8-bit integers, 24-bit fractions (total data width of 32 bits), fixed-point numbers of 4-bit integers, 12-bit fractions (total data width of 16 bits), and the like. In addition, the multipliers in the formulas (1) and (2) use corresponding fixed-point multipliers, and the filter parameters, the pulse delivery probability and the neurotransmitter margin are also expressed by fixed-point numbers. Replacing floating-point numbers and floating-point multipliers with fixed-point numbers and fixed-point multipliers may reduce computational resource requirements and computational latency. The technical scheme of replacing the index operation of the filtering model with the lookup table and replacing the floating-point number operation with the fixed-point number operation greatly reduces the calculation complexity of the index operation, thereby improving the filtering speed, and reducing the calculation power and power consumption requirements on computing equipment by replacing the floating-point number with the fixed-point number.
The circuit architecture of the spatial filtering circuit is shown in fig. 4. The spatial filtering circuit comprises a spatial filtering control logic circuit, and a data reading circuit, a filtering selection circuit, a data buffering accumulation circuit and a history memory cache circuit which are sequentially connected, wherein the history memory cache circuit is also connected with the data reading circuit. The data read circuit, filter select circuit, data buffer accumulation circuit, and history buffer circuit are labeled with letters D, E, F and G, respectively. The data reading circuit, the filtering selection circuit, the data buffering accumulation circuit and the history memory cache circuit are respectively connected with the airspace filtering control logic circuit. The spatial filtering control logic circuit is used for controlling the data reading circuit, the filtering selection circuit, the data buffering accumulation circuit and the history memory cache circuit to respectively realize respective functions.
The data reading circuit includes a column counter 21, a comparator 22, a row counter 23, a comparator 24, an equality discriminator 25, a MUX26, and a MUX 27. The data output from the time-domain filter output buffer of the time-domain filter circuit is input to the input of MUX 26. The equality discriminator 25 discriminates whether or not the data output from the line counter 23 is equal to 0. The column counter 21 is connected to an input terminal of the comparator 22, and the predetermined constant C _ W is input to another input terminal of the comparator 22, an output terminal of the comparator 22 is connected to a first input terminal (i.e., a data selection control terminal) of the MUX27, an output terminal of the MUX26 is connected to a second input terminal of the MUX27, and 0 is input to a third input terminal of the MUX 27; the line counter 23 is connected to the input of the comparator 24 and the input of the equality discriminator 25, respectively; the other input terminal of the equality discriminator 25 inputs 0; the other input terminal of the comparator 24 inputs a preset constant C _ BH.
The filter selection circuit includes a weight buffer rom, a line pulse buffer 36, a line pulse buffer 37, a MUX28, a MUX29, a MUX30, an adder 31, and an adder 32. The weight buffer rom is respectively connected with one input end of the MUX28, the MUX29 and the MUX 30; the output end of the MUX27 is respectively connected with the control signal input end of the MUX28 and the line pulse buffer 36; the line pulse buffer 36 is connected to one input terminal of the MUX29 and the line pulse buffer 37, respectively; the line pulse buffer 37 is connected to one input of the MUX 30; MUX28, MUX29, and MUX30 each have an input terminal input 0; the output end of the MUX28 and the output end of the MUX29 are respectively connected with the adder 31; the output of MUX30 and adder 31 are connected to adder 32.
The data buffer accumulation circuit comprises a first buffer, a second buffer, a third buffer and an accumulation circuit, wherein the accumulation circuit is used for calculating the sum of the output value of the first buffer, the output value of the second buffer, the output value of the third buffer and the historical memory data of the historical memory buffer circuit and outputting the comparison result of the sum and the threshold. As shown in fig. 4, the data Buffer accumulation circuit includes three buffers, and an adder 33 and an adder 34 connected in sequence, which are Buffer _ S1, Buffer _ S2, and Buffer _ S3, respectively. An output of adder 32 is coupled to an input of Buffer _ S3. The output end of the Buffer _ S3 is respectively connected with the input end of the Buffer _ S2 and the input end of the adder 33; the output end of the Buffer _ S2 is respectively connected with the input end of the Buffer _ S1 and the input end of the adder 33; the output end of the Buffer _ S1 is connected with the input end of the adder; the output terminal of Buffer _ S0 is connected to the input terminal of adder 35, and S1, S2 and S3 are the output values of Buffer _ S1, Buffer _ S2 and Buffer _ S3, respectively.
The history memory buffer circuit comprises a comparator 40, a comparator 45, a multiplier 41, a subtracter 42, a MUX43, a MUX44, a filtered output buffer block and a history memory. The history memory is connected to the column counter 21, the row counter 23, the adder 35, and the MUX43, respectively. The comparator 40 is connected to the adder 35, and the comparator 40 is configured to compare the output of the adder 35 with a preset Threshold, and input the comparison result to the filtered output buffer block and the MUX43, respectively. The adder 35 is connected to the multiplier 41 and the subtractor 42, respectively. The multiplier 41 is connected to the MUX 43. MUX44 is connected to MUX 43. The subtractor 42 is connected to the comparator 45 and the MUX44, respectively. The history memory buffer circuit is used for adjusting the calculation result output by the data buffer accumulation circuit, storing the adjusted calculation result, and storing the data from the column counter 21 and the row counter 23. Data from the column counter 21 and the row counter 23 are stored in a history memory.
Since the input buffer is divided into 25 paths to operate in parallel in this embodiment, a line of data overlaps between two adjacent paths. Therefore, the present embodiment caches the last line of data of the previous way and the first line of data of the next way of each way in advance. The corresponding data is selected and sent to the filter selection circuit through the comparison of the line counter and two fixed values. When the column counter exceeds one row, zero is replenished to the row pulse buffer. After the current two lines of pulse data are cached in the line pulse buffer, the pulse of the third line is used as a selection end of the data selector on one hand to select the filtering weight or zero of the cache on the other hand to be sent to the first line pulse buffer; meanwhile, the last bit data of the first line pulse buffer is used as the selection end of the weight or 0 data selector on one hand, and is sent into the second line pulse buffer on the other hand. This computing architecture reuses the pulse data, greatly reducing the bandwidth requirements. The control logic circuit controls the output results of the three data selectors of the filtering selection circuit to be accumulated to the Buffer _ S3, meanwhile, the result of the Buffer _ S3 is gradually sent to the Buffer _ S2 in a pipeline mode, and the Buffer _ S2 is sent to the Buffer _ S1. Then the cumulative sum of Buffer _ S3 and Buffer _ S2 and Buffer _ S1 is the partial filter result. And adding the filtering result at the current moment to the memory of the historical moment to obtain a total accumulated value. The total accumulated value is compared with a threshold value to obtain a filtering output. The filtered output value is written into a filtered output cache block. The total accumulated value is attenuated after being multiplied by C _ tr, and then is sent to one input end (marked as branch 1) of MUX; meanwhile, the total accumulated value minus the value of C _ mn is compared with C _ ml, and the smaller value of the two is connected to the second input end (marked as branch 2) of the second MUX through the selection of the other MUX; the MUX is gated by the final filter output, with branch 1 being used to update the history buffer when the filter output is "1", and branch 2 being used to update the history buffer otherwise. The pipeline computing mode not only increases the data reuse rate, but also reduces the power consumption and improves the throughput.
An electronic device for performing pulse signal filtering includes the pulse signal filtering circuit of any of the above embodiments.
The circuit and the electronic equipment are suitable for scenes such as satellites, unmanned vehicles and mobile phones which have requirements on high speed and low power consumption.
The pulse signal filtering circuit provided by the embodiment of the application improves the pulse filtering speed through parallelization, and reuses data and intermediate results through a production line, so that the bandwidth requirement for accessing cache is reduced, redundant calculation is avoided, the volume and power consumption of a device, equipment or a model for pulse signal filtering can be reduced, and the information processing speed and throughput are increased.
It should be noted that:
the terms "first," "second," "third," and the like as used herein may be used herein to describe various objects, but these objects are not limited by these terms. These terms are only used to distinguish one object from other objects.
The algorithms and displays presented herein are not inherently related to any particular computer, virtual machine, or other apparatus. Various general purpose devices may also be used with the examples based on this disclosure. The required structure for constructing such a device will be apparent from the description above. In addition, this application is not directed to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the present application as described herein, and any descriptions of specific languages are provided above to disclose the best modes of the present application.
The above-mentioned embodiments only express the embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.
Claims (9)
1. A pulse signal filter circuit is characterized by comprising an input buffer control logic circuit and at least one filter unit circuit; the filtering unit circuit comprises an input cache circuit, a time domain filtering circuit and a space domain filtering circuit which are connected in sequence; the input cache circuit is connected with the input cache control logic circuit;
the input buffer control logic circuit is used for controlling the input buffer circuit to buffer the input pulse signal;
the time domain filtering circuit is used for performing time domain filtering on the data from the input cache circuit;
the spatial filtering circuit is used for carrying out spatial filtering on the data from the time domain filtering circuit;
the input buffer circuit comprises a data selector, a buffer and a buffer block, wherein a first input end of the data selector receives the pulse signal, an output end of the data selector is connected with an input end of the buffer, and an output end of the buffer is respectively connected with a second input end of the data selector and the buffer block;
the time domain filter circuit comprises a time domain filter control logic circuit, and a time memory calculation module, an axon neurotransmitter data processing module, an axon pulse issuing probability processing module, a data selector and a time sequence filter output buffer which are respectively controlled by the time domain filter control logic circuit;
the time memory calculation module is used for acquiring time memory data according to the data of the cache block;
the axon pulse issuing probability processing module is used for acquiring axon pulse issuing probability according to the time memory data;
the axon neurotransmitter data processing module is used for acquiring axon neurotransmitter data according to the time memory data and the axon pulse emission probability;
the data selector is used for selecting data meeting a preset time sequence filtering condition according to the data of the cache block and the axon neurotransmitter data;
and the time sequence filtering output buffer is used for storing the data meeting the preset time sequence filtering condition.
2. The pulsed signal filtering circuit according to claim 1, wherein the time memory calculation module comprises a time memory register, a filter selection circuit and a synaptic attenuation look-up table, the synaptic attenuation look-up table is configured to receive data from the time memory register, the filter selection circuit is configured to adjust and select data from the time memory register, and write the selected data into the time memory register;
the axonal impulse sending probability processing module comprises an axonal impulse sending probability buffer and a first data adjusting and updating circuit, wherein the first data adjusting and updating circuit is used for adjusting and updating data in the axonal impulse sending probability buffer according to data from the synapse attenuation lookup table;
the axon neurotransmitter data processing module comprises an axon neurotransmitter buffer and a second data adjustment update circuit for adjusting and updating data in the axon neurotransmitter buffer based on data from the synaptic attenuation look-up table and data from the axon impulse firing probability processing module; the data of the second data adjustment updating circuit is input into the data selector.
3. The pulse signal filter circuit according to claim 1, wherein the spatial filter circuit comprises a spatial filter control logic circuit, and a data reading circuit, a filter selection circuit, a data buffer accumulation circuit and a history memory buffer circuit which are respectively controlled by the spatial filter control logic circuit, and the data reading circuit, the filter selection circuit, the data buffer accumulation circuit and the history memory buffer circuit are sequentially connected; the history memory cache circuit is connected with the data reading circuit; the data reading circuit is connected with the time sequence filtering output buffer;
the data reading circuit is used for reading the data of the time sequence filtering output buffer;
the filtering selection circuit is used for selecting the data from the data reading circuit and selecting the data meeting the preset condition;
the data buffer accumulation circuit is used for carrying out accumulation calculation on the data meeting the preset conditions to obtain a calculation result;
the history memory cache circuit is used for adjusting the calculation result, storing the adjusted calculation result and storing the data of the data reading circuit.
4. The pulse signal filter circuit according to claim 3, wherein the data reading circuit comprises an equality discriminator, a row counter, a first comparator and a first data selector which are connected in sequence, and a column counter, a first comparator and a second data selector which are connected in sequence, the row counter, the equality discriminator and the first data selector being connected in sequence; the output end of the first data selector is connected with the input end of the second data selector; the input end of the first data selector is connected with the time sequence filtering output buffer.
5. The pulse signal filter circuit according to claim 4, wherein the filter selection circuit comprises a weight buffer, a first line pulse buffer, a second line pulse buffer, a third data selector, a fourth data selector, a fifth data selector, and an addition circuit; the addition circuit is configured to sum output data of the third data selector, the fourth data selector, and the fifth data selector; the weight buffer is respectively connected with the input ends of the third data selector, the fourth data selector and the fifth data selector; the second data selector is respectively connected with the first line pulse buffer and the third data selector; the first line pulse buffer is respectively connected with the fourth data selector and the second line pulse buffer; the second line pulse buffer is connected with the fifth data selector.
6. The pulse signal filter circuit according to claim 5, wherein the data buffer accumulation circuit includes a first buffer, a second buffer, a third buffer, and an accumulation circuit for calculating a sum of an output value of the first buffer, an output value of the second buffer, and an output value of the third buffer with a history time memory of the history memory buffer circuit, and outputting a comparison result of the sum with a threshold.
7. The pulse signal filter circuit according to claim 6, wherein the history memory buffer circuit includes a second comparator, a third comparator, a multiplier, a subtractor, a sixth data selector, a seventh data selector, a filter output buffer block, and a history memory; the history memory is respectively connected with the row counter, the line counter and the sixth data selector; the second comparator is respectively connected with the filtering output cache block and the sixth data selector; the multiplier is connected with the sixth data selector; the seventh data selector is connected with the sixth data selector; the subtracter is respectively connected with the third comparator and the seventh data selector.
8. The pulse signal filtering circuit according to claim 1, further comprising a filter output buffer for storing data output by the spatial domain filtering circuit.
9. An electronic device for pulse signal filtering, comprising a pulse signal filtering circuit according to any one of claims 1 to 8.
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