CN113725167A - 集成电路元件及其制作方法 - Google Patents

集成电路元件及其制作方法 Download PDF

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CN113725167A
CN113725167A CN202010447437.5A CN202010447437A CN113725167A CN 113725167 A CN113725167 A CN 113725167A CN 202010447437 A CN202010447437 A CN 202010447437A CN 113725167 A CN113725167 A CN 113725167A
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integrated circuit
layer
uppermost
dielectric
seal ring
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CN113725167B (zh
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马瑞吉
杨国裕
林家辉
张竹君
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN202310897900.XA priority patent/CN117080169A/zh
Priority to US16/914,482 priority patent/US11133270B1/en
Priority to US17/401,335 priority patent/US11462489B2/en
Priority to US17/408,505 priority patent/US20210384146A1/en
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Abstract

本发明公开一种集成电路元件及其制作方法，其中该集成电路元件包含：一基底；一集成电路区域，位于所述基底上，所述集成电路区域包含一介电堆叠；一密封环，设于所述介电堆叠中，并环绕于所述集成电路区域周围；一沟槽，环绕所述密封环，并显露出所述介电堆叠的一侧壁；一湿气阻隔层，连续的覆盖所述集成电路区域，并延伸至所述介电堆叠的所述侧壁，从而密封所述介电堆叠中的两个相邻介电膜之间的交界；以及一钝化层，位于所述湿气阻隔层上。

Description

集成电路元件及其制作方法
技术领域
本发明涉及半导体技术领域，特别是涉及一种改良的集成电路元件及其制作方法。
背景技术
密封环的形成是半导体后段制作工艺的重要步骤。密封环是集成电路周围的应力保护结构，可保护半导体芯片内的内部电路免受因晶片切割而造成的损坏。
密封环的另一功能是保护密封环内侧的集成电路免受湿气引起的退化。由于集成电路的介电层通常由多孔的低介电常数(低k)介电材料形成，因此水分很容易穿透低k介电层到达集成电路。
通常，密封环在芯片的外围是连续的结构，但是由连续密封环所构成的芯片外围直接电气路径会将噪声传递到敏感的模拟和RF电路模块。防止噪声传递的一种常规解决方案是采用电性上不连续的密封环，从而抑制了很大一部分噪声传递。然而，密封环的不连续性却会导致水分和污染物渗透进入半导体芯片。
发明内容
本发明的主要目的在于提供一种改良的集成电路元件及其制作方法，以解决上述现有技术的不足与缺点。
本发明一方面提供一种集成电路元件，包含：一基底；一集成电路区域，位于所述基底上，所述集成电路区域包含一介电堆叠；一密封环，设于所述介电堆叠中，并环绕于所述集成电路区域周围；一沟槽，环绕所述密封环，并显露出所述介电堆叠的一侧壁；一湿气阻隔层，连续的覆盖所述集成电路区域，并延伸至所述介电堆叠的所述侧壁，从而密封所述介电堆叠中的两个相邻介电膜之间的交界；以及一钝化层，位于所述湿气阻隔层上。
依据本发明一实施例，其中所述集成电路区域包含一射频电路。
依据本发明一实施例，其中所述基底是一硅覆绝缘基底，包含一下基底、一埋入氧化层和位于所述埋入氧化层上的一元件层。
依据本发明一实施例，其中所述元件层包含一硅层。
依据本发明一实施例，其中所述密封环经由一穿透所述元件层和所述埋入氧化层的贯通接触件电耦合至所述下基板。
依据本发明一实施例，其中所述两个相邻的介电膜是两个相邻的低介电常数介电膜。
依据本发明一实施例，其中所述密封环为一不连续的密封环。
依据本发明一实施例，其中所述密封环由内连的金属线和介层通孔所构成的。
依据本发明一实施例，其中所述金属线包含一最上层铜金属线，且所述湿气阻隔层直接接触所述最上层铜金属线。
依据本发明一实施例，其中所述最上层铜金属线为一最上层镶嵌铜金属线，并且所述湿气阻隔层同时作为覆盖所述最上层镶嵌铜金属线的顶面的一上盖层。
依据本发明一实施例，所述的集成电路元件另包含：一最上层介电膜，覆盖所述介电堆叠；一最上层介层通孔，贯穿所述最上层介电膜和所述湿气阻隔层，以与所述最上层铜金属线电连接；以及一铝垫，设于所述最上层介层通孔上并与所述最上层介层通孔电连接。
依据本发明一实施例，其中所述钝化层覆盖所述铝垫的周缘和所述最上层介电膜的顶面。
依据本发明一实施例，其中所述最上层介电膜包含氧化硅。
依据本发明一实施例，其中所述钝化层包含聚酰亚胺、氮化硅或氧化硅。
依据本发明一实施例，其中所述湿气阻隔层包含氮化硅、氮氧化硅或碳氮化硅。
本发明另一方面提供一种形成集成电路元件的方法，包括提供一基底；在所述基底上形成一集成电路区域，所述集成电路区域包含一介电堆叠；在所述介电堆叠中形成一密封环，所述密封环环绕于所述集成电路区域周围；形成一沟槽，环绕所述密封环，所述沟槽显露出所述介电堆叠的一侧壁；形成一湿气阻隔层，连续的覆盖所述集成电路区域，并延伸至所述介电堆叠的所述侧壁，从而密封所述介电堆叠中的两个相邻介电膜之间的交界；以及于所述湿气阻隔层上形成一钝化层。
依据本发明一实施例，其中所述集成电路区域包含一射频电路。
依据本发明一实施例，其中所述基底是一硅覆绝缘基底，包含一下基底、一埋入氧化层和位于埋入氧化层上的一元件层。
依据本发明一实施例，其中所述元件层包含一硅层。
依据本发明一实施例，其中所述密封环经由一穿透所述元件层和所述埋入氧化层的贯通接触件电耦合至所述下基板。
依据本发明一实施例，其中所述两个相邻的介电膜是两个相邻的低介电常数介电膜。
依据本发明一实施例，其中所述密封环为一不连续的密封环。
依据本发明一实施例，其中所述密封环由内连的金属线和介层通孔所构成的。
依据本发明一实施例，其中所述金属线包含一最上层铜金属线。
依据本发明一实施例，其中所述最上层铜金属线为一最上层镶嵌铜金属线。
依据本发明一实施例，其中另包含：形成一最上层介电膜，覆盖所述介电堆叠；形成一最上层介层通孔，贯穿所述最上层介电膜和所述湿气阻隔层，以与所述最上层铜金属线电连接；以及形成一铝垫，设于所述最上层介层通孔上并与所述最上层介层通孔电连接。
依据本发明一实施例，其中所述钝化层覆盖所述铝垫的周缘和所述最上层介电膜的顶面。
依据本发明一实施例，其中所述最上层介电膜包含氧化硅。
依据本发明一实施例，其中所述钝化层包含聚酰亚胺、氮化硅或氧化硅。
依据本发明一实施例，其中所述湿气阻隔层包含氮化硅、氮氧化硅或碳氮化硅。
附图说明
图1至图5为本发明一实施例所绘示的形成集成电路元件的方法的示意图，其中，图1为集成电路元件的上视示意图，图2至图5为沿着图1中切线I-I’的剖视图。
主要元件符号说明
1 集成电路元件
10 集成电路区域
11 射频电路
20 切割道区域
30 密封环
40 介电堆叠
40a 侧壁
100 基底
101 下基底
102 埋入氧化层
103 元件层
401 介电膜
402 交界
403 介电膜
404 湿气阻隔层
405 最上层介电膜
410 图案化的光致抗蚀剂层
AP 铝垫
M1 第1层金属导线层
M2 第2层金属导线层(最上层铜金属线)
OB 开孔
PL 钝化层
R 沟槽
ST 沟槽绝缘区域
TV 贯通接触件
V1 介层通孔
Vn 最上层介层通孔
具体实施方式
在下文中，将参照附图说明细节，该些附图中的内容也构成说明书细节描述的一部分，并且以可实行该实施例的特例描述方式来绘示。下文实施例已描述足够的细节使该领域的一般技术人士得以具以实施。
当然，也可采行其他的实施例，或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此，下文的细节描述不应被视为是限制，反之，其中所包含的实施例将由随附的权利要求来加以界定。
请参阅图1至图5，其为依据本发明一实施例所绘示的形成集成电路元件1的方法的示意图，其中，图1为集成电路元件1的上视示意图，图2至图5为沿着图1中切线I-I’的剖视图。
如图1和图2所示，首先提供一基底100，例如，所述基底100是一硅覆绝缘(silicon-on-insulator，SOI)基底，包含一下基底(lower substrate)101、一埋入氧化层(buried oxide layer)102和位于埋入氧化层102上的一元件层(device layer)103。其中，所述下基底101可以是一硅基底，所述埋入氧化层102可以是一硅氧层，所述元件层103包含一硅层，例如，单晶硅层。
依据本发明一实施例，在所述基底100上形成有一集成电路区域10。依据本发明一实施例，所述集成电路区域10包含一射频(radio-frequency，RF)电路11。为简化说明，图2中并未显示出集成电路区域10的电路元件和金属内连线结构。紧邻于所述集成电路区域10的是一切割道(scribe lane)区域20。
依据本发明一实施例，所述集成电路区域10包含一介电堆叠40。依据本发明一实施例，在所述介电堆叠40中已形成有一结构上和电性上不连续的密封环30，所述密封环30环绕于所述集成电路区域10周围。所述密封环30可以保护射频电路11免受因晶片切割而造成的损坏。电性上不连续的密封环30可以抑制噪声传递。然而，由于所述密封环30在结构上不连续，导致其阻隔湿气或污染物侵入射频电路11的能力降低。本发明可以具体解决这个问题。
依据本发明一实施例，如图2所示，所述介电堆叠40具有至少两个相邻的介电膜401和介电膜403，在介电膜401和介电膜403之间具有一交界402。湿气或应力有可能沿着介电膜401和介电膜403之间的交界402侵入射频电路11，造成电路结构腐蚀或损坏。依据本发明一实施例，所述两个相邻的介电膜401和403可以是两个相邻的低介电常数(low-k)介电膜。所谓的「低介电常数介电膜」指的是介电常数小于2.5的介电膜。
依据本发明一实施例，所述密封环30由内连的金属线M和介层通孔V所构成的。为简化说明，图2中仅例示出第1层金属导线层M1、第2层金属导线层M2和介于第1层金属导线层M1与第2层金属导线层M2之间的介层通孔V1。依据本发明一实施例，第2层金属导线层M2为最上层铜金属线，例如，最上层镶嵌铜金属线。换言之，在此例中，第2层金属导线层M2和介层通孔V1以双镶嵌铜制作工艺形成的内连线结构，而在第2层金属导线层M2上方不会有铜内连线。依据本发明一实施例，所述密封环30经由一穿透所述元件层103和所述埋入氧化层102的贯通接触件TV电耦合至所述下基板101。依据本发明一实施例，贯通接触件TV贯穿设于所述元件层103中的沟槽绝缘区域ST。
如图3所示，在完成第2层金属导线层M2的化学机械研磨制作工艺后，接着在第2层金属导线层M2和介电膜403上形成一图案化的光致抗蚀剂层410。依据本发明一实施例，图案化的光致抗蚀剂层410覆盖住所述集成电路区域10，显露出切割道区域20。接着，进行一非等向性干蚀刻制作工艺，蚀刻掉未被图案化的光致抗蚀剂层410覆盖的所述介电堆叠40，显露出切割道区域20内的所述元件层103，如此在切割道区域20内形成一沟槽R。
依据本发明一实施例，所述沟槽R环绕所述密封环30，且所述沟槽R显露出所述介电堆叠40的一侧壁40a以及在所述侧壁40a上的所述介电膜401和所述介电膜403之间的所述交界402。在完成所述沟槽R之后，接着将剩余的图案化的光致抗蚀剂层410去除。
如图4所示，接着形成一湿气阻隔层404，连续的覆盖所述集成电路区域10，并延伸至所述介电堆叠40的所述侧壁40a上，从而密封所述介电堆叠40中的两个相邻介电膜401和403之间的交界402，因此，所述湿气阻隔层404可以有效的阻绝湿气或污染物侵入射频电路11。依据本发明一实施例，其中所述湿气阻隔层404可以包含氮化硅、氮氧化硅或碳氮化硅。此外，所述湿气阻隔层404还直接接触第2层金属导线层M2和介电膜403的上表面，可以同时作为第2层金属导线层M2的上盖层。依据本发明一实施例，所述湿气阻隔层404除了覆盖所述介电堆叠40的所述侧壁40a，还延伸至切割道区域20内，并且覆盖所述元件层103。
如图5所示，接着，形成一最上层介电膜405，覆盖所述湿气阻隔层404和所述介电堆叠40。依据本发明一实施例，其中所述最上层介电膜405包含氧化硅。接着，在所述最上层介电膜405中形成一最上层介层通孔Vn，贯穿所述最上层介电膜405和所述湿气阻隔层404，以与所述第2层金属导线层M2电连接。接着，在最上层介电膜405上形成一铝垫AP，设于所述最上层介层通孔Vn上，并与所述最上层介层通孔Vn电连接。接着，沉积一钝化层PL，顺形的覆盖住最上层介电膜405。依据本发明一实施例，其中所述钝化层PL包含聚酰亚胺、氮化硅或氧化硅。
依据本发明一实施例，其中所述钝化层PL覆盖所述铝垫AP的周缘和所述最上层介电膜405的顶面。依据本发明一实施例，利用光学光刻制作工艺和蚀刻制作工艺，可以在所述钝化层PL中形成开孔OB，显露出部分的铝垫AP的上表面，用于后续进行与外部电路连接。
结构上，如图5所示，本发明集成电路元件1，包含：一基底100；一集成电路区域10，位于所述基底100上，所述集成电路区域10包含一介电堆叠40；一密封环30，设于所述介电堆叠40中，并环绕于所述集成电路区域10周围；一沟槽R，环绕所述密封环30，并显露出所述介电堆叠40的一侧壁40a；一湿气阻隔层404，连续的覆盖所述集成电路区域10，并延伸至所述介电堆叠40的所述侧壁40a，从而密封所述介电堆叠40中的两个相邻介电膜401、403之间的交界402；以及一钝化层PL，位于所述湿气阻隔层404上。
依据本发明一实施例，其中所述集成电路区域10包含一射频电路11。依据本发明一实施例，其中所述基底100是一硅覆绝缘基底，包含一下基底101、一埋入氧化层102和位于所述埋入氧化层102上的一元件层103。依据本发明一实施例，其中所述元件层103包含一硅层。
依据本发明一实施例，其中所述密封环30为一不连续的密封环依据本发明一实施例，其中所述密封环30由内连的金属线M和介层通孔V所构成的。依据本发明一实施例，其中所述金属线M包含一最上层铜金属线M2，且所述湿气阻隔层404直接接触所述最上层铜金属线M2。依据本发明一实施例，其中所述最上层铜金属线M2为一最上层镶嵌铜金属线，并且所述湿气阻隔层404同时作为覆盖所述最上层镶嵌铜金属线的顶面的一上盖层。依据本发明一实施例，其中所述密封环30经由一穿透所述元件层103和所述埋入氧化层102的贯通接触件TV电耦合至所述下基板101。
依据本发明一实施例，其中所述两个相邻的介电膜401、403是两个相邻的低介电常数介电膜。依据本发明一实施例，所述的集成电路元件1另包含：一最上层介电膜405，覆盖所述介电堆叠40；一最上层介层通孔Vn，贯穿所述最上层介电膜405和所述湿气阻隔层404，以与所述最上层铜金属线M2电连接；以及一铝垫AP，设于所述最上层介层通孔Vn上并与所述最上层介层通孔Vn电连接。
依据本发明一实施例，其中所述钝化层PL覆盖所述铝垫AP的周缘和所述最上层介电膜405的顶面。依据本发明一实施例，其中所述最上层介电膜405包含氧化硅。依据本发明一实施例，其中所述钝化层PL包含聚酰亚胺、氮化硅或氧化硅。依据本发明一实施例，其中所述湿气阻隔层404包含氮化硅、氮氧化硅或碳氮化硅。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (30)

1.一种集成电路元件，其特征在于，包含：
基底；
集成电路区域，位于所述基底上，所述集成电路区域包含介电堆叠；
密封环，设于所述介电堆叠中，并环绕于所述集成电路区域周围；
沟槽，环绕所述密封环，并显露出所述介电堆叠的一侧壁；
湿气阻隔层，连续的覆盖所述集成电路区域，并延伸至所述介电堆叠的所述侧壁，从而密封所述介电堆叠中的两个相邻介电膜之间的交界；以及
钝化层，位于所述湿气阻隔层上。
2.如权利要求1所述的集成电路元件，其中所述集成电路区域包含射频电路。
3.如权利要求1所述的集成电路元件，其中所述基底是硅覆绝缘基底，包含下基底、埋入氧化层和位于所述埋入氧化层上的元件层。
4.如权利要求3所述的集成电路元件，其中所述元件层包含硅层。
5.如权利要求3所述的集成电路元件，其中所述密封环经由一穿透所述元件层和所述埋入氧化层的贯通接触件电耦合至所述下基板。
6.如权利要求1所述的集成电路元件，其中所述两个相邻的介电膜是两个相邻的低介电常数介电膜。
7.如权利要求1所述的集成电路元件，其中所述密封环为不连续的密封环。
8.如权利要求7所述的集成电路元件，其中所述密封环由内连的金属线和介层通孔所构成的。
9.如权利要求8所述的集成电路元件，其中所述金属线包含最上层铜金属线，且所述湿气阻隔层直接接触所述最上层铜金属线。
10.如权利要求9所述的集成电路元件，其中所述最上层铜金属线为最上层镶嵌铜金属线，并且所述湿气阻隔层同时作为覆盖所述最上层镶嵌铜金属线的顶面的上盖层。
11.如权利要求10所述的集成电路元件，其中另包含：
最上层介电膜，覆盖所述介电堆叠；
最上层介层通孔，贯穿所述最上层介电膜和所述湿气阻隔层，以与所述最上层铜金属线电连接；以及
铝垫，设于所述最上层介层通孔上并与所述最上层介层通孔电连接。
12.如权利要求11所述的集成电路元件，其中所述钝化层覆盖所述铝垫的周缘和所述最上层介电膜的顶面。
13.如权利要求12所述的集成电路元件，其中所述最上层介电膜包含氧化硅。
14.如权利要求12所述的集成电路元件，其中所述钝化层包含聚酰亚胺、氮化硅或氧化硅。
15.如权利要求1所述的集成电路元件，其中所述湿气阻隔层包含氮化硅、氮氧化硅或碳氮化硅。
16.一种形成集成电路元件的方法，包含：
提供基底；
在所述基底上形成集成电路区域，所述集成电路区域包含介电堆叠；
在所述介电堆叠中形成密封环，所述密封环环绕于所述集成电路区域周围；
形成沟槽，环绕所述密封环，所述沟槽显露出所述介电堆叠的一侧壁；
形成湿气阻隔层，连续的覆盖所述集成电路区域，并延伸至所述介电堆叠的所述侧壁，从而密封所述介电堆叠中的两个相邻介电膜之间的交界；以及
在所述湿气阻隔层上形成钝化层。
17.如权利要求16所述的方法，其中所述集成电路区域包含射频电路。
18.如权利要求16所述的方法，其中所述基底是硅覆绝缘基底，包含下基底、埋入氧化层和位于埋入氧化层上的元件层。
19.如权利要求18所述的方法，其中所述元件层包含硅层。
20.如权利要求18所述的方法，其中所述密封环经由穿透所述元件层和所述埋入氧化层的贯通接触件电耦合至所述下基板。
21.如权利要求16所述的方法，其中所述两个相邻的介电膜是两个相邻的低介电常数介电膜。
22.如权利要求16所述的方法，其中所述密封环为不连续的密封环。
23.如权利要求22所述的方法，其中所述密封环由内连的金属线和介层通孔所构成的。
24.如权利要求23所述的方法，其中所述金属线包含最上层铜金属线。
25.如权利要求24所述的方法，其中所述最上层铜金属线为最上层镶嵌铜金属线。
26.如权利要求25所述的方法，其中另包含：
形成最上层介电膜，覆盖所述介电堆叠；
形成最上层介层通孔，贯穿所述最上层介电膜和所述湿气阻隔层，以与所述最上层铜金属线电连接；以及
形成铝垫，设于所述最上层介层通孔上并与所述最上层介层通孔电连接。
27.如权利要求26所述的方法，其中所述钝化层覆盖所述铝垫的周缘和所述最上层介电膜的顶面。
28.如权利要求27所述的方法，其中所述最上层介电膜包含氧化硅。
29.如权利要求27所述的方法，其中所述钝化层包含聚酰亚胺、氮化硅或氧化硅。
30.如权利要求16所述的方法，其中所述湿气阻隔层包含氮化硅、氮氧化硅或碳氮化硅。
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