CN113724775B

CN113724775B - Meta information management method, solid state disk controller and solid state disk

Info

Publication number: CN113724775B
Application number: CN202110970247.6A
Authority: CN
Inventors: 方浩俊; 黄运新; 杨亚飞
Original assignee: Nanjing Dapu Information Technology Co ltd
Current assignee: Nanjing Dapu Information Technology Co ltd
Priority date: 2021-08-23
Filing date: 2021-08-23
Publication date: 2023-07-04
Anticipated expiration: 2041-08-23
Also published as: CN113724775A

Abstract

The embodiment of the application relates to the field of solid state disk application and discloses a meta-information management method, a solid state disk controller and a solid state disk. Logic blocks and meta information, the method comprising: assigning the same base address to the logical addresses of data in the same data page or the same word line; the logical address of each meta-information within the same data page or same word line is stored in the form of a combination of base address and offset. The logical address is stored in the form of combination of the base address and the offset, the space occupied by the logical address for occupying meta information can be reduced, and the error correction check data length can be increased, so that the integral error correction capability of the solid state disk can be improved, and the service life of the solid state disk can be prolonged.

Description

Meta information management method, solid state disk controller and solid state disk

Technical Field

The present disclosure relates to the field of solid state disk applications, and in particular, to a meta information management method, a solid state disk controller, and a solid state disk.

Background

The solid state disk (Solid State Drives, SSD) is a hard disk made of a solid state electronic memory chip array, and the solid state disk comprises a control unit and a memory unit (FLASH memory chip or DRAM memory chip), wherein in solid state memory, the size of meta information influences error correction capability.

At present, as the capacity of the solid state disk is larger and larger, the meta information demand is also more and more, because the data in the same page or word line is not specially optimized, the distribution range of the logical address corresponding to the data is 0 to the maximum, and the space occupied by the storage of the logical address in the form of full address is overlarge, for example, a large-capacity disk needs to occupy more than four bytes, so that the whole error correction capability of the solid state disk is insufficient, and the whole service life of the solid state disk is further insufficient.

Based on the above problems, improvements are needed in the prior art.

Disclosure of Invention

The embodiment of the application provides a meta information management method, a solid state disk controller and a solid state disk, so as to solve the technical problem of short overall service life of the existing solid state disk.

In order to solve the technical problems, the embodiment of the application provides the following technical scheme:

in a first aspect, an embodiment of the present application provides a meta information management method, which is applied to a solid state disk, where the solid state disk includes at least one word line, each word line includes at least two data pages, and each data page includes at least one error correction unit, where the error correction unit includes: logic blocks and meta information, the method comprising:

Assigning the same base address to the logical addresses of data in the same data page or the same word line;

the logical address of each meta-information within the same data page or same word line is stored in the form of a combination of base address and offset.

In a second aspect, an embodiment of the present application provides a solid state disk controller, including:

at least one processor; the method comprises the steps of,

a memory communicatively coupled to the at least one processor; wherein, the liquid crystal display device comprises a liquid crystal display device,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the meta information management method as described in the first aspect.

In a third aspect, an embodiment of the present application provides a solid state hard disk, including:

a flash memory array comprising a plurality of wafers, each of the wafers comprising a plurality of groupings, each of the groupings comprising a plurality of physical blocks, each of the physical blocks comprising a plurality of physical pages;

the solid state disk controller as described in the second aspect.

In a fourth aspect, embodiments of the present application further provide a non-volatile computer-readable storage medium storing computer-executable instructions for enabling a solid state disk to perform the meta information management method as described above.

The beneficial effects of the embodiment of the application are that: in a case different from the prior art, the meta information management method provided in the embodiment of the present application is applied to a solid state disk, where the solid state disk includes at least one word line, each word line includes at least two data pages, and each data page includes at least one error correction unit, where the error correction unit includes: logic blocks and meta information, the method comprising: assigning the same base address to the logical addresses of data in the same data page or the same word line; the logical address of each meta-information within the same data page or same word line is stored in the form of a combination of base address and offset. The logical address is stored in the form of combination of the base address and the offset, the space occupied by the logical address for occupying meta information can be reduced, and the error correction check data length can be increased, so that the integral error correction capability of the solid state disk can be improved, and the service life of the solid state disk can be prolonged.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.

Fig. 1 is a schematic structural diagram of a solid state disk provided in an embodiment of the present application;

FIG. 2 is a schematic structural diagram of a solid state disk controller according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of RBER distribution of a data page of TLC Flash provided in an embodiment of the present application;

FIG. 4 is a schematic diagram of a data page provided by an embodiment of the present application;

FIG. 5 is a schematic diagram of a data page of TLC Flash provided in an embodiment of the present application;

fig. 6 is a flowchart of a meta information management method according to an embodiment of the present application;

FIG. 7 is a schematic diagram of meta information movement of a data page of TLC Flash according to an embodiment of the present application;

FIG. 8 is a schematic diagram of error correction threshold of a data page of TLC Flash according to an embodiment of the present application;

fig. 9 is a schematic flow chart of determining a first adjustment interval and a second adjustment interval according to an embodiment of the present application;

FIG. 10 is a flowchart of issuing an operation command according to an embodiment of the present application;

FIG. 11 is a schematic diagram of another solid state disk according to an embodiment of the present disclosure;

FIG. 12 is a schematic diagram of an error correction engine generating error correction check data according to an embodiment of the present application;

FIG. 13 is a flowchart illustrating another meta-information management method according to an embodiment of the present disclosure;

FIG. 14 is a schematic illustration of a polymerization process provided in an embodiment of the present application;

FIG. 15 is a schematic diagram of a storage manner of a logical address according to an embodiment of the present disclosure;

FIG. 16 is a schematic diagram of a relationship between a logical address and a page or word line according to an embodiment of the present application;

fig. 17 is a detailed flowchart of step S131 in fig. 13;

FIG. 18 is a flowchart illustrating the storage of meta information according to an embodiment of the present application;

fig. 19 is a schematic diagram of a process of meta information provided in an embodiment of the present application;

FIG. 20 is a schematic diagram of another meta-information process provided by an embodiment of the present application;

FIG. 21 is a schematic diagram of a firmware system of a solid state disk controller according to an embodiment of the present disclosure;

FIG. 22 is a schematic diagram of a firmware system of another solid state disk controller according to an embodiment of the present disclosure;

FIG. 23 is a detailed schematic of the first aggregate processing module of FIG. 22;

FIG. 24 is a schematic diagram of a refinement of the second polymerization processing module of FIG. 22;

FIG. 25 is a schematic diagram of an IO linked list according to an embodiment of the present disclosure;

FIG. 26 is a schematic diagram of an operation flow of a sub-set linked list according to an embodiment of the present application;

fig. 27 is a schematic diagram of writing data by a host according to an embodiment of the present application.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

In addition, technical features described below in the various embodiments of the present application may be combined with each other as long as they do not conflict with each other.

The technical scheme of the application is specifically described below with reference to the drawings in the specification.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a solid state disk according to an embodiment of the present application.

As shown in fig. 1, the solid state disk 100 includes a flash memory medium 110 and a solid state disk controller 120 connected to the flash memory medium 110. The solid state disk 100 is in communication connection with the host 200 through a wired or wireless manner, so as to implement data interaction.

The Flash memory medium 110, which is a storage medium of the solid state disk 100, is also called a Flash memory, a Flash memory or Flash particles, belongs to one type of storage device, is a nonvolatile memory, and can store data for a long time even without current supply, and has storage characteristics equivalent to a hard disk, so that the Flash memory medium 110 becomes a base of storage media of various portable digital devices.

The solid state disk controller 120 includes a data converter 121, a processor 122, a buffer 123, a flash memory controller 124, and an interface 125.

The data converter 121 is connected to the processor 122 and the flash memory controller 124, respectively, and the data converter 121 is used for converting binary data into hexadecimal data and vice versa. Specifically, when the flash controller 124 writes data to the flash memory medium 110, binary data to be written is converted into hexadecimal data by the data converter 121, and then written to the flash memory medium 110. When the flash controller 124 reads data from the flash memory medium 110, hexadecimal data stored in the flash memory medium 110 is converted into binary data by the data converter 121, and then the converted data is read from a binary data page register. The data converter 121 may include a binary data register and a hexadecimal data register, among others. The binary data register may be used to hold data converted from hexadecimal to binary, and the hexadecimal data register may be used to hold data converted from binary to hexadecimal.

The processor 122 is respectively connected to the data converter 121, the buffer 123, the flash memory controller 124 and the interface 125, where the processor 122 is connected to the data converter 121, the buffer 123, the flash memory controller 124 and the interface 125 through buses or other manners, and the processor is configured to run nonvolatile software programs, instructions and modules stored in the buffer 123, so as to implement any method embodiment of the present application.

The buffer 123 is mainly used for buffering the read/write command sent by the host 200 and the read data or write data obtained from the flash memory medium 110 according to the read/write command sent by the host 200.

A flash controller 124 connected to the flash medium 110, the data converter 121, the processor 122, and the buffer 123, for accessing the flash medium 110 at the back end and managing various parameters and data I/O of the flash medium 110; or, the interface and the protocol for providing access implement a corresponding SAS/SATA target protocol end or NVMe protocol end, obtain an I/O instruction sent by the host 200, decode and generate an internal private data result, and wait for execution; or for the core processing responsible for FTL (Flash translation layer ).

The interface 125 is connected to the host 200 and the data converter 121, the processor 122 and the buffer 123, and is configured to receive data sent by the host 200, or receive data sent by the processor 122, so as to implement data transmission between the host 200 and the processor 122, where the interface 125 may be a SATA-2 interface, a SATA-3 interface, a SAS interface, a MSATA interface, a PCI-E interface, an NGFF interface, a CFast interface, a SFF-8639 interface and an m.2nvme/SATA protocol.

Referring to fig. 2 again, fig. 2 is a schematic structural diagram of a solid state disk controller according to an embodiment of the present application; the solid state disk controller belongs to the solid state disk.

As shown in fig. 2, the solid state disk controller 120 includes: PCIe interface controller 126, DDR controller 127, NVMe interface controller 128, processor 122, peripheral module 129, data path module 1210, and flash controller 124.

Specifically, the PCIe interface controller 126 is configured to control a PCIe communication protocol, the DDR controller 127 is configured to control a dynamic random access memory, the NVMe interface controller 128 is configured to control an NVMe communication protocol, the peripheral module 129 is configured to control other related communication protocols, and the data path module 1210 is configured to control a data path, for example: management of write buffers, the flash controller 124 is used for data processing of the flash memory.

It is understood that a Flash memory (NAND Flash) is a non-volatile storage medium, and is characterized in that electrons can be stored in one unit, the number of which can be represented as a voltage value, and the voltage value can be divided into a plurality of areas. Storing only one bit (such Flash is called SLC), 2 states being required for correspondence; if 2 bits are stored (such Flash is called MLC), 4 states are required correspondingly; if 3 bits are stored (such Flash is called TLC), 8 states are required for each, and so on, the power of 2 is used as the number of stored bits to calculate, and 2 states are required for each. In general, N bits in a unit are coded and distributed among N data pages, which appear as different data pages, for example: the MLCFlash includes two data pages of LSB and MSB, and the TLCFlash includes three data pages of LSB, CSB and MSB.

Generally, a Flash memory (NAND Flash) error is mainly caused by a change in voltage of a Cell due to electron leakage, and a distribution area of the Cell changes to cause a read misjudgment, namely an erroneous bit. Since different cells are in different states, the distribution area changes to affect different data pages differently, and the original bit error rates (Raw Bit Error Rate, RBER) of different data pages are different from the external view of the flash memory.

Referring to fig. 3, fig. 3 is a schematic diagram of RBER distribution of a data page of TLC Flash according to an embodiment of the present application;

as shown in fig. 3, the TLC Flash includes three data pages LSB, CSB and MSB, where RBER of each data page is distributed differently, and error correction thresholds of different data pages are different under the same Erase-Program Cycle (EPC), that is, error correction capacities of different data pages are different in order to reach the EPC target value.

In an embodiment of the present application, the solid state disk includes at least one word line, and each word line includes at least two data pages, for example: each word line of the MLCFlash includes two data pages of LSB and MSB, each word line of the TLC Flash includes three data pages of LSB, CSB and MSB, for example, each word line of the QLC Flash includes four data pages, and each word line of the XLC Flash includes five data pages.

Referring to fig. 4, fig. 4 is a schematic diagram of a data page according to an embodiment of the present application;

as shown in fig. 4, each data page includes at least one error correction unit, wherein the error correction unit includes: valid data and verification data, the valid data comprising: user data and meta information. It is understood that the user data includes a logical block, and the meta information is information about information for describing the structure, semantics, usage, and the like of the information.

Referring to fig. 5 again, fig. 5 is a schematic diagram of a data page of TLC Flash according to an embodiment of the present application;

as shown in fig. 5, the spatial sizes of the meta information of each of the LSB data page, the CSB data page, and the MSB data page are the same, that is, the spatial sizes of the meta information of the LSB data page, the CSB data page, and the MSB data page are the same, and the spatial sizes of the error correction check data of the LSB data page, the CSB data page, and the MSB data page are the same.

Thus, it can be seen that the LSB data page, the CSB data page, and the MSB data page have completely identical data distributions, the same error correction unit, the same meta information size, and the same error correction check data size.

It will be appreciated that the error correction unit is composed of valid data and check data, the check data being used in the error correction algorithm, the size of which directly influences the size of the error correction capability, i.e. the more check data, the stronger the error correction capability. The effective data is divided into user data and meta information, the meta information is used for firmware algorithm management and at least comprises a logic address corresponding to a logic data block. From the user's perspective, both meta information and check data are redundant data. Since the determined flash memory type has a determined page size, that is to say a determined error correction unit size, the improvement of the error correction capability on this basis depends on the balance between meta information and check data.

As shown in the data distribution of fig. 5, the size of meta information corresponding to each logical block is the same, and if the error correction capability is to be improved, the size of meta information needs to be compressed as a whole, thereby increasing the space size of check data.

Currently, an error correction capability, that is, an error correction threshold is unified with the worst page, that is, the page with the highest original bit error rate as a standard, so that the error correction capability of each data page is higher than the error correction threshold, however, since different data pages have the same error correction capability, the probability of re-reading a page with the high original bit error rate (a weak page) is higher than a page with the low original bit error rate (a strong page), so that delay of reading different data pages is different, and service quality (QoS) is affected to some extent. In addition, the life cycle of the weak page is usually reached first, but the life cycle of the strong page is not consumed, so that the waste of the storage space is caused, and the whole service life of the solid state disk is further reduced.

Therefore, in order to prolong the overall service life of the solid state disk, the application provides a meta-information management method, and by adopting meta-information with different sizes for different data pages, the space which is more than the space for reducing the meta-information in the weak page is used as a verification data space, so that the error correction capability of the weak page is improved.

Referring to fig. 6, fig. 6 is a flowchart of a meta information management method according to an embodiment of the present application;

as shown in fig. 6, the meta information management method is applied to a solid state disk, and is characterized in that the solid state disk includes at least one word line, each word line includes at least two data pages, each data page includes at least one error correction unit, and the error correction unit includes: valid data and verification data, the valid data comprising: user data and meta information, the method comprising:

step S601: determining a first data page and at least a second data page of at least two data pages in each of the word lines according to the original bit error rate of each data page in each of the word lines, wherein the original bit error rate of the first data page is smaller than the original bit error rate of the second data page;

specifically, the original bit error rate of each page of data in each of the word lines is obtained, for example: and a certain word line comprises an LSB data page, a CSB data page and an MSB data page, wherein the LSB data page is determined to be a first data page, and the CSB data page and the MSB data page are determined to be second data pages on the premise that the original bit error rate of the LSB data page is minimum.

It will be appreciated that in practical cases the determination of the first data page and the second data page will be slightly different depending on the coding scheme of the particle manufacturer, i.e. the first data page and the second data page depend on the coding scheme in the voltage state distribution. For example: the original bit error rate of each data page may be determined by the manufacturer or experimental data to obtain the effect of the strength of the data page, thereby determining the first data page and the second data page.

Step S602: and moving part of meta information of at least one second data page to a space corresponding to the meta information of the first data page, and using the space corresponding to the moved meta information in the second data page to increase the check data length so that the total space size of the meta information corresponding to each word line is unchanged.

Specifically, part of meta information corresponding to one logic block in at least one data page is moved to a space corresponding to meta information of one logic block corresponding to the first data page, and the space corresponding to the moved meta information in each second data page is used for increasing the length of check data, namely increasing the space corresponding to error correction check data, so as to improve the error correction capability of the second data page.

Referring to fig. 7, fig. 7 is a schematic diagram illustrating meta information movement of a data page of TLC Flash according to an embodiment of the present application;

as shown in fig. 7, the LSB data page is determined to be a first data page, the CSB data page and the MSB data page are both second data pages, and a part of meta information corresponding to logical block 0 of the CSB data page and the MSB data page is moved to a space of meta information corresponding to the LSB data page, so that a space of error correction check data is increased to increase a check data length. It can be appreciated that since the space of meta information of the LSB data page increases, the space of error correction check data of the LSB data page decreases.

Since part of the meta information in the second data page is moved into the first data page, it can be acquired by reading the meta information of the first data page when it is necessary to read the moved meta information in the second data page.

Further, in order to determine the adjustment range of the meta information and the error correction check data, it is necessary to calculate a gap of the original bit error rates of the first data page and the second data page, that is, to set the adjustment range of the meta information and the check data to a degree that the RBER of the first data page (strong page) is lower than that of the second data page (weak page).

Referring to fig. 8, fig. 8 is a schematic diagram of an error correction threshold of a data page of TLC Flash according to an embodiment of the present application;

as shown in fig. 8, the vertical axis represents the original number of error bits (RBER) of each page, and the horizontal axis represents an Erase-Program cycle (EPC), and the error correction strength and the error correction threshold value are measured by using the original bit error rate (RBER) as a measure to determine the error correction strength or the error correction threshold value.

That is, from the overall point of view outside the flash memory, the number of original error bits (RBER) of the flash memory is evaluated to determine the reliability of the flash memory, which is mainly affected by an Erase-Program cycle (EPC), or a Program-Erase cycle (PEC), or a Write-Erase cycle (WEC), or an Erase Counter (EC). Obviously, the EPC and RBER are positively correlated, and after the EPC target value is increased, the weak page error correction strength, the error correction threshold value and the strong page error correction strength are all increased, but the weak page error correction strength is obviously required to be higher than the strong page error correction strength so as to meet the EPC target value.

It will be appreciated that the overall life extension of the solid state disk is manifested by a right shift in the EPC target value, i.e. an increase in the EPC target value, but that an increase in the EPC target value results in an increase in RBER, and therefore, an improvement in error correction capability is required, which is manifested by an increase in the check data length.

For a typical flash memory vendor, its nominal reliability refers to: the data read with is error free at the nominal erase times and the error correction capability requirements (ECC requirements) of the reading device. In short, the master's error correction engine capability must be greater than the error correction threshold.

Since the individual data pages have different RBER behavior, in other words, the number of original error bits occurring in the LSB data page (strong page) is smaller than in the MSB data page and CSB data page (weak page) in the same EPC case, the requirement is satisfied with a relatively weak error correction capability. Then the flash lifetime (increasing EPC value) is correspondingly increased overall, and it is apparent that the error correction capability needs to be increased for both the strong and weak pages.

The method and the device have the advantages that different error correction intensities (error correction capacities) are set for different data pages, and under the condition that an error correction algorithm is fixed, the error correction intensity is strongly related to the length of check data, namely, the longer the length of the check data is, the higher the error correction capacity is. But the data storage distribution is mostly fixed (a logical block containing user data, and metadata of management information within one error correction unit, the remainder being space for check data). Then for the improvement of metadata management, it is possible to achieve a difference in the space of the check data in the error correction units within different pages, and thus a difference in the error correction strength.

In an embodiment of the present application, the meta information includes a logical address, and the moving part of the meta information of at least one second data page to a space corresponding to the meta information of the first data page includes:

and moving the logical address of the at least one second data page to a space corresponding to the meta information of the first data page. For example: based on word line units, each of the general-purpose data pages has a space of 32Bytes, for example: one word line comprises three data pages, namely a first data page and two second data pages, wherein one first data page has a space of 32Bytes, one second data page has a space of 32Bytes, the logical address LMA of the second data page is 10Bytes, the logical address of the second data page is moved to the space corresponding to the meta-information of the first data page, the space size of the second data page is changed to 32-10=22 Bytes, and the space size of the first data page is 32+20=42 Bytes, so that the total size of the word line is still 32Bytes, 3=96 Bytes.

It can be understood that in the solid state disk software algorithm, meta information is mainly used for two stages: a garbage collection stage and a power-on reconstruction table stage. The present application alters the previously common approach to meta-information therein corresponding to the phase of the power-on reconstruction table: the management method using only data pages as units is changed to using word lines (wordlines) as units, and the overall size of the meta-information is kept unchanged, i.e. the meta-information with reduced weak pages is moved into the meta-information of strong pages. Specifically, the migration content of the meta information may be determined by a specific algorithm.

For example: the meta-information of the power-on re-establishment table phase typically contains logical addresses (LMA, otherwise known as LBN, LPA, etc.) for P2L (physical address to logical address mapping) relationship establishment. The general purpose type means that each meta information contains an LMA, and the LMA is typically 8 to 10 bytes in size. Depending on the available meta-information size of the first data page (strong page), the LMA of the second data page (weak page) may be moved in whole or in part into the meta-information of the strong page.

As shown in table 1 below, the LMAs of the second data page are all moved into the meta information of the first data page. Since the word line is used as a programming unit, only one time stamp (TimeStamp) is needed. Therefore, the space corresponding to the time stamp in the second data page can also be used to increase the space of the error correction check data.

TABLE 1

It will be appreciated that for a first data page (strong page) and a second data page (weak page), the original bit error rate (Raw Bit Error Rate, RBER) of the first data page is smaller than the original bit error rate (Raw Bit Error Rate, RBER) of the second data page under the same Erase-Program Cycle (EPC), that is, the required error correction strength of the first data page is smaller than that of the second data page, so that the space of the error correction check data of the first data page can be reduced for increasing the space of the meta information thereof, so that the space of the meta information of the first data page is used for recording the meta information of the second data page to increase the space of the error correction check data of the second data page, thereby increasing the error correction strength of the second data page.

Specifically, referring to fig. 9 again, fig. 9 is a schematic flow chart of determining a first adjustment interval and a second adjustment interval according to an embodiment of the present application;

as shown in fig. 9, the process of determining the first adjustment interval and the second adjustment interval includes:

step S901: acquiring data distribution of original bit error rates of a first data page and a second data page, and acquiring a preset first error correction intensity threshold value and a preset second error correction intensity threshold value;

specifically, referring to fig. 8 again, as shown in fig. 8, the LSB data page is a first data page, the MSB data page and the CSB data page are both second data pages, by acquiring data distributions of original bit error rates of the first data page and the second data page, determining an EPC target value under a preset error correction algorithm, and determining a first error correction intensity threshold corresponding to the first data page and a second error correction intensity threshold corresponding to the second data page based on the data distributions of the original bit error rates of the first data page and the second data page according to the EPC target value. In an embodiment of the present application, the error correction algorithm includes an LDPC error correction algorithm.

Step S902: determining a first error correction intensity corresponding to the first data page and a second error correction intensity corresponding to the second data page according to the data distribution of the original bit error rates of the first data page and the second data page and the first error correction intensity threshold and the second error correction intensity threshold;

Specifically, before the error correction intensities of the first data page and the second data page are not adjusted, the error correction intensities of the first data page and the second data page are both the error correction intensities of the general data page. It can be understood that the general data page is a unified error correction strength configuration without distinguishing strong pages from weak pages.

As shown in table 2 below, assuming that the length of the error correction unit (code) is 4KB, the error correction strength of the general-purpose data page is 240bit/4KB, and the error correction strength threshold of the general-purpose data page is 240bit/4KB, at this time, the error correction strength threshold of the first data page (strong page) is 210bit/4KB, and the error correction strength threshold of the second data page (weak page) is 240bit/4KB, in order to improve the error correction capability of the second data page (weak page), the determining the first error correction strength corresponding to the first data page and the second error correction strength corresponding to the second data page according to the data distribution of the original bit error rates of the first data page and the second data page and the first error correction strength threshold and the second error correction strength threshold includes:

determining that the first error correction strength corresponding to the first data page is (a first error correction strength threshold + a redundancy value);

And determining the second error correction intensity corresponding to the second data page as (error correction intensity threshold value of the general data page + (error correction intensity threshold value of the general data page-first error correction intensity threshold value-redundancy value)/N), wherein N is the number of the second data pages, and N is a positive integer.

For example:

if there is only one second data page, such as: the MLCFlash, LSB data page is the first data page, MSB data page is the second data page, confirm the first error correction intensity that the first data page corresponds to is (the first error correction intensity threshold value), confirm the second error correction intensity that the second data page corresponds to is (the error correction intensity threshold value + second error correction intensity threshold value-first error correction intensity threshold value of the general data page);

if there are two second data pages, such as: the TLC Flash, LSB data page is the first data page, CSB data page and MSB data page are the second data page, then confirm the first error correction intensity that the first data page corresponds to is (first error correction intensity threshold + redundant value), the second error correction intensity that the second data page corresponds to is (error correction intensity threshold+ (error correction intensity threshold-first error correction intensity threshold-redundant value of the general data page)/2);

similarly, if N second data pages exist, determining that the first error correction strength corresponding to the first data page is (first error correction strength threshold+redundancy value), and the second error correction strength corresponding to the second data page is (error correction strength threshold+ (error correction strength threshold of general data page-first error correction strength threshold-redundancy value)/N, where N is a positive integer and N is greater than or equal to 2;

In this embodiment of the present application, the redundancy value is a preset value, for example: taking TLC Flash as an example in table 2 below, two second data pages exist, and assuming that the redundancy value in table 2 below is 10bit/4KB, it is determined that the first error correction strength corresponding to the first data page is (first error correction strength threshold+redundancy value) = (210 bit/4kb+10bit/4 KB) =220 bit/4KB, and the second error correction strength corresponding to the second data page is (error correction strength threshold+ (error correction strength threshold of general data page-first error correction strength threshold-redundancy value)/2) = (240 bit/4kb+ (240 bit/4KB-210bit/4KB-10bit/4 KB)/2) =250 bit/4KB.

TABLE 2

Step S903: and determining a first adjustment interval of the check data length of the first data page and a second adjustment interval of the check data length of the second data page according to a preset error correction intensity conversion rule.

Specifically, the error correction strength conversion rule includes: error-correctable bit number = check data bit number/preset coefficient.

Specifically, the preset coefficient is determined by a preset error correction algorithm, for example: the error correction algorithm is an LDPC error correction algorithm, and when the preset coefficient is 16, the error correction strength conversion rule=t=p/16, where T is the number of bits of the error-correctable bits, and P is the number of bits of the Parity data bits.

As shown in table 2, on the premise that the length of the error correction unit is 4KB, the number of error-correctable bits of the first data page is 240 bits-220 bits=20 bits, and at this time, p=16t, the number of check data bits p=16x20bit=320 bits.

Specifically, the determining, according to a preset error correction strength conversion rule, a first adjustment interval of a check data length of a first data page and a second adjustment interval of a check data length of a second data page includes:

calculating a first check data bit number corresponding to the first data page, and determining a first adjustment interval;

and calculating a second check data bit number corresponding to the second data page, and determining a second adjustment interval.

As shown in table 2 above, on the premise that the length of the error correction unit is 4KB, the number of error-correctable bits of the first data page is 240 bits-220 bits=20 bits, and at this time, p=16t, the number of check data bits p=16x20bit=320 bits=40bytes, i.e. the first adjustment interval of the check data length of the first data page is [0, 40Bytes ]; similarly, the number of error-correctable bits of the second data page is 250 bits-240 bits=10 bits, where p=16t, and the number of check data bits p=16×10bit=160 bits=20 Bytes, that is, the second adjustment interval of the check data length of the second data page is [0, 20Bytes ].

Specifically, the method further comprises the following steps:

determining the check data length of the increased second data page according to the first adjustment interval of the check data length of the first data page and the second adjustment interval of the check data length of the second data page, and determining the check data length of the decreased first data page.

Specifically, according to the first adjustment interval of the check data length of the first data page, determining the check data length of the reduced first data page, where the check data length of the reduced first data page is located in the first adjustment interval, preferably, the check data length of the reduced first data page is the maximum value of the first adjustment interval, for example: if the first adjustment interval is [0, 40Bytes ], the check data length of the reduced first data page is 40Bytes;

specifically, according to the second adjustment interval of the check data length of the second data page, determining the check data length of the added second data page, where the check data length of the added second data page is located in the second adjustment interval, preferably, the check data length of the added second data page is the maximum value of the second adjustment interval, for example: if the first adjustment interval is [0, 20Bytes ], the check data length of the reduced first data page is 20Bytes.

Referring to fig. 10 again, fig. 10 is a schematic flow chart of issuing operation command symbols according to an embodiment of the present application;

as shown in fig. 10, the process of issuing the operation command symbol includes:

step S1001: different check matrixes are configured according to the set check data length;

specifically, according to the first check data length corresponding to the first data page, determining a first check matrix combination corresponding to the first check data length; and determining a second check matrix combination corresponding to the second check data length according to the second check data length corresponding to the second data page;

it will be appreciated that after the error correction strength of the first data page and the second data page is determined, the check data length is determined, that is, the first check data length corresponding to the first data page and the second check data length corresponding to the second data page, and the corresponding check data lengths need to be matched by different matrices and parameters.

In an embodiment of the present application, determining a check matrix combination according to a check data length includes: and selecting a limited check matrix under the check data length to determine a check matrix combination. Specifically, according to the first check data length corresponding to the first data page, determining a first check matrix combination corresponding to the first check data length; and determining a second check matrix combination corresponding to the second check data length according to the second check data length corresponding to the second data page. For example: the length space of the check data is 32Bytes, the error correction algorithm provides 4 check matrixes, the check data length is 24-34 Bytes, 28-40 Bytes, 34-48 Bytes and 42-54 Bytes respectively, then only 2 check matrixes can be selected, namely 24-34 Bytes and 28-40 Bytes respectively, and the check matrixes are determined to be (24-34 Bytes and 28-40 Bytes) in combination.

In an embodiment of the present application, the method further includes:

the error correction engine parameters are configured according to the set check data length, wherein the error correction engine parameters refer to the configuration of the control error correction engine, such as whether to select a high performance mode, an enhancement mode, whether to enable low power consumption, and the like.

Step S1002: setting corresponding operation command symbols according to different check matrixes;

specifically, according to the first check matrix combination, determining a corresponding first operation command symbol to determine a first operation command symbol corresponding to a first data page;

and determining a corresponding second operation command symbol according to the second check matrix combination so as to determine a second operation command symbol corresponding to a second data page.

Step S1003: identifying the type of the data page, issuing a corresponding operation command character, and performing data read-write operation;

specifically, after the data page type is identified, a corresponding operation command is issued to perform data read-write operation, wherein the data page type comprises a first data page or a second data page, and the operation command comprises a first operation command or a second operation command. For example: if the first data page is identified, a first operation command character is issued; if the second data page is identified, a second operation commander is issued. The data read-write operation comprises a decoding operation and an encoding operation. When the data page type is identified, a corresponding operation command character is selected, so that the error correction engine generates or identifies a corresponding check code when reading and writing data.

Referring to fig. 10, fig. 10 is a schematic diagram of another solid state disk according to an embodiment of the present disclosure;

as shown in fig. 10, the solid state disk 100 includes: the flash memory array 110 and the solid state disk controller 120, wherein the solid state disk controller 120 includes: the system comprises a processor 122, a buffer 123, an error correction engine 1211 and a flash memory controller 124, wherein the processor 122 is connected with the buffer 123, the error correction engine 1211 and the flash memory controller 124.

The processor 122 is configured to configure a corresponding error correction engine, and send out a read-write operation;

wherein, the buffer 123 is configured to store user data; in the embodiment of the present application, the buffer 123 is preferably a random access memory (Random Access Memory, RAM).

The flash controller 124 is configured to send a flash operation command and data.

The error correction engine 1211 is connected to the memory and the processor, and is configured to perform error correction encoding on the valid data to generate corresponding check data when writing the data; or, the device is used for decoding the error correction unit and correcting the effective data when the data is read;

in this embodiment of the present application, the error correction engine 1211 is an ECC engine (eccingine), and the error correction engine supports multiple error correction capabilities, for example, under an LDPC error correction algorithm, supports multiple check matrices, and may be applied to the same error correction unit (code) to generate different check data.

In the embodiment of the present application, taking write data as an example, please refer to fig. 12, fig. 12 is a schematic diagram of an error correction engine for generating error correction check data according to the embodiment of the present application;

as shown in fig. 12, the error correction engine generates different check data according to different check matrices, so when the error correction requirements (check code lengths) of the strong page and the weak page are determined, that is, when the error correction unit (code) is determined, the determined error correction check data length needs to be adjusted by different check matrices and error correction engine parameters to match the required check data length. When error correction coding is performed, the corresponding check matrix is selected, so that error correction check data with corresponding length can be generated.

In the embodiment of the application, the actual error correction strength of the strong page and the weak page can be enabled to be consistent through the improvement of meta information management, so that the error correction capability of the weak page is improved, the probability of reading errors of different data pages is enabled to be consistent, and the reading consistency (namely, the quality of service (QoS) is improved) is ensured. In addition, the service life of the solid state disk is prolonged due to the improvement of the error correction strength of the weak pages, so that the service life of the whole solid state disk can be prolonged.

In an embodiment of the present application, a meta information management method is provided and applied to a solid state disk, where the solid state disk includes at least one word line, each word line includes at least two data pages, and each data page includes at least one error correction unit, and the error correction unit includes: valid data and verification data, the valid data comprising: user data and meta information, the method comprising: determining a first data page and at least a second data page of at least two data pages in each of the word lines according to the original bit error rate of each data page in each of the word lines, wherein the original bit error rate of the first data page is smaller than the original bit error rate of the second data page; and moving part of meta information of at least one second data page to a space corresponding to the meta information of the first data page, and using the space corresponding to the moved meta information in the second data page to increase the check data length so that the total space size of the meta information corresponding to each word line is unchanged. By adopting different check data lengths for different data pages, the error correction capability of the weak pages can be improved, and the overall service life of the solid state disk can be prolonged.

At present, as the capacity of the solid state disk is larger and larger, the meta information needs to be increased, especially the meta information at least contains one logical address, and the bit domain occupies more than four bytes, so that the phenomenon not only begins to influence the improvement of certain error correction capability, but also has influence on the firmware algorithm, such as the power recovery speed.

Since the data in the same page or word line is not particularly optimized, the distribution range of the logical address corresponding to the data is 0 to the maximum, and then the logical address in the meta information must be stored in full address. However, the space occupied by storing the logical addresses in the form of full-scale addresses is too large, for example, a large-capacity disk needs to occupy more than four bytes, and how to optimize the storage of the logical addresses in meta-information becomes a problem to be solved.

Based on the above, the embodiment of the application provides a meta information management method, a solid state disk controller and a solid state disk, so as to solve the technical problem of the short overall service life of the current solid state disk.

Specifically, referring to fig. 13, fig. 13 is a flow chart of another meta information management method according to an embodiment of the present application;

as shown in fig. 13, the meta information management method includes:

Step S131: assigning the same base address to the logical addresses of data in the same data page or the same word line;

specifically, by data aggregation, the logical addresses of data within the same data page or the same word line have the same base address. Specifically, before the same base address is assigned to the logical address of the data in the same data page or the same word line, the method further includes:

based on a preset logic address subset rule, carrying out aggregation processing on data written into the flash memory, and dividing the logic address of the data written into the flash memory into a plurality of subsets, wherein the logic address subset rule comprises the following steps: each subset corresponds to one page or wordline of data one by one, the logical addresses of the data in each subset are determined to have the same base address, and each logical address is represented by a combination of base address and offset.

Specifically, the logical addresses are used as aggregation standards, and based on a preset logical address subset rule, the data are classified and collected into corresponding subsets according to the logical addresses of the data during data aggregation processing, and the condition that the same data page or the same word line of the flash memory is written is met.

Specifically, the aggregating processing is performed on the data written into the flash memory based on the preset logic address subset rule, and the logic address of the data written into the flash memory is divided into a plurality of subsets, including:

Assuming that the logical address of the data written to the flash memory is divided into N subsets, then:

where N is a positive integer, i is a non-negative integer, N is the number of subsets, base (N) is the Base address of the nth subset, and Mi is the size of the ith subset.

Where Base (1) =m0, base (2) =m0+m1, base (3) =m0+m1+m2, it will be appreciated that depending on the subset size of each subset, the starting position of the Base address of the subset may be determined, for example: if subset 0 has a subset size of 1024 (its address is 0-1023), then subset 1 starts with a base address of 1024.

Referring to fig. 14 again, fig. 14 is a schematic diagram of an aggregation process according to an embodiment of the present application;

as shown in fig. 14, data from a Host (Host) or Garbage Collection (GC) is aggregated before being written into a flash memory, and is divided into N subsets, LMA subset 1 to LMA subset N, respectively, wherein each subset has the same base address, and the logical address of data in the subset can be expressed as the base address plus an offset.

Step S132: the logical address of each meta-information within the same data page or same word line is stored in the form of a combination of base address and offset.

In the embodiment of the application, because N logic addresses in the same data page or the same word line are stored in the meta-information in the form of base address plus offset, the same base address is stored only in one part, so that the length of the logic addresses occupying the meta-information is reduced.

In an embodiment of the present application, the method further includes:

dividing the base address into N sub base addresses according to the quantity N of meta information in the same data page or the same word line, wherein N is a positive integer;

the storing of the logical address of each meta-information within the same data page or same word line in the form of a combination of base address and offset includes:

each meta-information is assigned a sub-base address in a one-to-one correspondence such that the logical address of each meta-information is stored in a combination of sub-base addresses and offsets.

As shown in table 3 below, the logical address of the meta information is stored in a base address type manner, that is, the combination of the sub base address and the offset is used for storing, compared with the general type logical address, the space for storing the logical address of the meta information can be saved, and the saved space is used for verifying the data length, so that the overall error correction capability of the solid state disk is improved, and the service life of the solid state disk is prolonged.

TABLE 3 Table 3

In the embodiment of the application, the logical addresses in the meta-information are stored in the form of base addresses plus offset, compared with the storage of the total logical addresses, N logical addresses in the same page or word line have the same base addresses, and only one base address is required to be stored in total, the base addresses are divided into N meta-information on average, and 1/N base addresses and at least one offset are arranged in each meta-information, so that occupation space of the meta-information is reduced, the overall error correction capability of the solid state disk is improved, and the service life of the solid state disk is prolonged.

Referring to fig. 15, fig. 15 is a schematic diagram of a storage manner of a logical address according to an embodiment of the present application;

as shown in fig. 15, meta information corresponding to a logical block in a page or a word line in the related art stores a logical address LMA, for example: the meta information 0 corresponding to the logical block 0 stores a logical address LMA0, which is directly stored in the meta information in the form of a full logical address;

the method for storing the logical address by the meta information corresponding to the logical block in the invention is as follows: 1/N base addresses (1/NBASE) and OFFSET (OFFSET), for example: the meta information 0 corresponding to the logical block 0 stores 1/N BASE addresses (1/N BASE) and OFFSET0 (OFFSET 0) corresponding to the logical address LMA 0.

Referring to fig. 16 again, fig. 16 is a schematic diagram showing a relationship between a logic address and a page or word line according to an embodiment of the present application;

as shown in fig. 16, the data in the same page or wordline of data within one physical block (block) has the same subset of logical addresses, but the specific value of the subset of logical addresses is not determined, conversely, the determined physical address does not belong to the determined subset of logical addresses, and each page or wordline of data has data of a different subset of logical addresses. That is, the data aggregation only needs to meet the data volume requirement of the same data page or the same word line, and the subset of logical addresses does not limit the physical address where the data is located.

Referring back to fig. 17, fig. 17 is a detailed flowchart of step S131 in fig. 13;

as shown in fig. 17, this step S131: assigning the same base address to the logical address of the data within the same data page or the same word line, comprising:

step S1311: acquiring a logic address corresponding to any logic block in the same data page or the same word line;

step S1312: determining subset information corresponding to the logical address according to the logical address;

it will be appreciated that, since each logic block in the same data page or the same word line corresponds to a unique subset of logic addresses, by determining the lookup table of the logic addresses and the logic subsets in advance, the logic address corresponding to any logic block in the same data page or the same word line is obtained, and the subset information corresponding to the logic address can be determined.

Specifically, the determining, according to the logical address, subset information corresponding to the logical address includes:

based on a pre-established logic address and a lookup table of a logic subset, inquiring the lookup table according to the logic address, and determining subset information corresponding to the logic address, wherein the subset information comprises base address information of the base address.

It will be appreciated that in meta-information management, a lookup table of logical addresses to logical subsets needs to be maintained, so that obtaining information of the relevant subset, such as the base address of the logical subset, etc., with the logical addresses is achieved. When the base address of the logic subset needs to be queried in the meta information, the base address of the logic subset corresponding to the logic address is acquired through the query table.

Step S1313: and acquiring a base address corresponding to the subset information according to the subset information.

Specifically, a base address is obtained according to the logical address subset information, and the base address is segmented into N meta-information of the same page or word line. The subset information contains information such as base address, and the base address is extracted, divided and stored in meta information.

It will be appreciated that a logical subset is a base + size, and that the logical address falling within that logical subset is the base + offset of that logical subset. By maintaining a lookup table of logical addresses and logical subsets, it is used to implement base address lookup based on logical addresses.

In an embodiment of the present application, the method further includes: allocating the same logic address range for the data in the same data page or the same word line; and according to the logic address range, the same base address is allocated to the logic address of the data in the same data page or the same word line, and the logic address of each meta information in the same data page or the same word line is stored in the form of a combination of the base address and the offset.

In this embodiment of the present application, if the meta information includes at least two logical addresses, the meta information includes at least two offsets, and each offset corresponds to one logical address one by one.

It will be appreciated that the management algorithm related to meta information uses the order rule as an index, that is, the first offset is used as the logical address offset corresponding to the data block, and the second offset is used as the logical address offset corresponding to the other data blocks. The main purpose of storing the logical address is that the data and the logical address can be corresponding, so that the relationship between the data and the logical address can be checked in some occasions, and in order to accelerate the determination of the checking relationship, the logical address of the adjacent data is also placed in the meta information of the data block, so that when reading, the corresponding relationship between two data and the logical address can be known by reading one data block, therefore, by setting a base address or a sub-base address in the meta information and combining at least two offsets, the logical addresses corresponding to a plurality of data can be stored.

Referring to fig. 18 again, fig. 18 is a flowchart illustrating a meta-information storage process according to an embodiment of the present application;

as shown in fig. 18, the flow of storing the meta information includes:

Step S181: n logic blocks and meta information are distributed according to the page or word line size;

specifically, according to the memory size of one data page or one word line, N logic blocks and N meta information are allocated, where each logic block corresponds to one meta information, for example: logical block 0 corresponds to meta-information 0, … … and logical block N-1 corresponds to meta-information N-1.

Step S182: obtaining a logic address corresponding to any logic block, and inquiring the information of the subset according to the logic address;

specifically, based on a pre-established lookup table of a logic address and a logic subset, the lookup table is queried according to the logic address, and subset information corresponding to the logic address, namely logic address subset information, is determined, wherein the subset information comprises base address information of the base address.

Step S183: obtaining a base address according to the logic address subset information, and dividing the base address into N meta information of the same page or word line;

specifically, the base address is obtained according to the logic address subset information, the base address is divided into N sub base addresses, the sub base addresses are in one-to-one correspondence with the meta information, namely one sub base address is in one-to-one correspondence with one meta information, so that the N sub base addresses are in one-to-one correspondence with the N meta information, and each sub base address is stored in the corresponding meta information.

Step S184: at least one logic address offset is allocated to each piece of meta information, and the logic address offset corresponds to a logic block where the meta information is located;

specifically, at least one logical address offset is assigned to each meta-information such that the meta-information includes at least one sub-base + offset.

Referring to fig. 19 again, fig. 19 is a schematic diagram illustrating a meta-information processing according to an embodiment of the present application;

as shown in fig. 19, after the logical addresses and the logical blocks are subjected to meta information processing, the base addresses are obtained by querying the subset rule.

Referring to fig. 20 again, fig. 20 is a schematic diagram illustrating another meta-information processing provided in the embodiment of the present application;

as shown in fig. 20, the information combination of the logical block data and the logical address transferred from the previous module is processed, wherein the logical block data is used as the effective data portion of the error correction unit, and the logical address is used as the query base address and the calculated offset. By obtaining the base address and the number of logical blocks within a page or word line, the base address value put to each meta information can be calculated, and how many logical blocks and meta information are allocated, i.e., the number of error correction units, is determined according to the size of the page or word line.

In an embodiment of the present application, by providing a meta information management method, the meta information management method is applied to a solid state disk, where the solid state disk includes at least one word line, each word line includes at least two data pages, and each data page includes at least one error correction unit, where the error correction unit includes: logic blocks and meta information, the method comprising: assigning the same base address to the logical addresses of data in the same data page or the same word line; the logical address of each meta-information within the same data page or same word line is stored in the form of a combination of base address and offset. The logical address is stored in the form of combination of the base address and the offset, the space occupied by the logical address for occupying meta information can be reduced, and the error correction check data length can be increased, so that the integral error correction capability of the solid state disk can be improved, and the service life of the solid state disk can be prolonged.

Referring to fig. 21 again, fig. 21 is a schematic structural diagram of a firmware system of a solid state disk controller according to an embodiment of the present application;

as shown in fig. 21, the solid state disk controller of the solid state disk includes a firmware system, where the firmware system is used to connect a host and a flash memory array to implement processing of data IO;

specifically, the firmware system 210 of the solid state disk controller includes:

a Front End module 211 (FE) for acquiring a Host command to generate an IO operation, where the Front End module is further configured to be responsible for operations such as a communication protocol with a Host (Host), a Host command, and an analysis of a solid state disk command;

a Data processing module 212 (DP) connected to the front end module 211, configured to receive the IO operation sent by the front end module 211 and Process the IO operation, where the Data processing module 212 is further configured to Process command Data, such as cache Data;

an algorithm module 213 (Flash Translation Layer, FTL) connected to the data processing module 212, for performing mapping processing on the IO operations to determine an issued flash memory array;

a Back End (BE) module 214 connected to the algorithm module 213, and configured to receive the IO operation sent by the algorithm module 213, so as to perform a read/write operation on the flash memory array;

The algorithm module 213 (Flash Translation Layer, FTL) sends the IO operation to the Back End module 214 (Back End, BE) of the solid state disk controller, so that the Back End module 214 of the solid state disk controller receives the IO operation sent by the algorithm module 213, and performs an operation to a corresponding FLASH array or FLASH medium according to the IO operation, that is, completes an operation process from data to FLASH, where the operation includes a read operation or a write operation.

The front end module 211 of the solid state disk controller processes the host command to generate an IO operation, and sequentially passes through the data processing module 212, the algorithm module 213 and the back end module 214 to operate the flash memory array.

Referring to fig. 22 again, fig. 22 is a schematic structural diagram of a firmware system of another solid state disk controller according to an embodiment of the present disclosure;

as shown in fig. 22, the firmware system includes:

a front end module 211, wherein the front end module 211 comprises: a command processing module 2111 for obtaining a host command to generate an IO operation;

the data processing module 212 is connected with the command processing module 2111, and is configured to receive the IO operation sent by the command processing module 2111 and process the IO operation;

The algorithm module 213 is connected to the data processing module 212, and is configured to receive the IO operation processed by the data processing module 212, and perform mapping processing on the IO operation to determine a flash memory array to be issued;

a back end module 214, wherein the back end module 214 comprises: the flash memory processing module 2141 is connected with the algorithm module 213 and is used for receiving IO operation sent by the algorithm module 213 so as to perform read-write operation on the flash memory array;

wherein the data processing module 212 comprises:

a first aggregation processing module 2121 connected to the command processing module 2111 for performing an aggregation operation;

wherein the algorithm module 213 includes:

the second aggregation processing module 2132 is connected to the flash memory processing module 2141 and is used for performing aggregation operations.

In the embodiment of the present application, the data processing module 212 further includes:

a first data buffering module 2122, connected to the first aggregation processing module 2121, for buffering data;

the algorithm module 213 further includes:

a second data buffering module 2133, connected to the second aggregation processing module 2132, for buffering data;

the meta information management module 2131 is connected to the first aggregation processing module 2121 and the second aggregation processing module 2132, and is configured to manage meta information.

It will be appreciated that in basic logic, there are two paths for data, one for host (host) writing and the other for Garbage Collection (GC), i.e. reading from and writing to NAND, both paths requiring an aggregation process. Host (Host) writes are aggregated at data processing module 212 and Garbage Collection (GC) writes are aggregated at algorithm module 213. While the meta information management module 2131 handles information processing after two path aggregation.

Referring to fig. 23 again, fig. 23 is a schematic diagram showing a refinement of the first aggregation processing module in fig. 22;

as shown in fig. 23, the first aggregation processing module 2121 includes:

a first rule management module 2101 for setting an aggregation rule, wherein the aggregation rule comprises: the number of subsets, the base address size of the subsets, and cache data brushing conditions;

the cache data flushing condition refers to the data size meeting the same address subset, wherein the same address subset refers to the address range of the subset where the addresses in the command fall in the same setting. The cache data brushing condition is set according to specific requirements, for example: if the data aggregation is limited to the data size of one data page or one word line, the cache data brushing condition is that the data size of one data page or one word line is taken as a threshold value, and the cache data brushing condition is met if the threshold value is met; if the data aggregation is limited to the data size of N data pages or N word lines, the cache data flushing condition is that the data size of N data pages or N word lines is taken as a threshold value, and the cache data flushing condition is met if the threshold value is met.

Such as: the cache data flushing condition is that the data size of one data page or one word line is used as a threshold value, at this time, the subset M0 is in the address range of 0-1023, the writing address of CMD0 is in the range of LBA 0-3, the writing address of CMD1 is in the range of LBA 32-39, CMD2 LBA 2048-2063 causes CMD0 and CMD1 to fall on M0, and if the total data amount of the operation of CDM0 and CMD1 meets the threshold value, the data amount required by one writing operation is aggregated, the cache data flushing condition is met, and at this time, flushing can be performed.

The first identifying and aggregating module 2102 is configured to identify a logical address, determine a subset corresponding to the logical address, mount an IO operation on a corresponding IO linked list, and apply for a cache space for the IO operation;

the first identifying and aggregating module 2102 is configured to complete aggregation of similar logical address operations, specifically, identify a logical address of a host command, split the host command according to a rule that a logical address in the host command falls in a subset, and mount the split host command to a corresponding subset IO linked list.

Referring to fig. 25 again, fig. 25 is a schematic diagram of an IO linked list according to an embodiment of the present application;

as shown in fig. 25, a command collector (CMD Fetcher) is responsible for obtaining a command from a previous module, converting the command into an IO operation, identifying a logical address of an input command, and loading the IO operation corresponding to the Command (CMD) on a corresponding IO linked list according to which subset the address falls on. The IO scheduler (IO Dispatcher) is responsible for taking IO operations out of the IO linked list, classifying the IO operations and distributing data buffers for the operation of the next module, wherein the next module is an algorithm module or a flash memory processing module, for example: IO operation is transmitted to the algorithm module, data is reserved in the Buffer, and the data is brushed out to the flash memory processing module. The IO operations with the same base address can be gathered on the same linked list through the operations of the command collector and the IO scheduler, namely, the gathered tasks are completed.

The first classification application module 2103 is used for processing the subset data, and brushing the subset data to the flash memory processing module when the subset data volume meets the cache data brushing condition;

specifically, the first classification application module 2103 is configured to complete processing of operation data of a same type of logical address, for example: processing the subset IO, applying for caching for data writing, and brushing IO operation to a next module when the subset data volume meets the data brushing condition, for example: an algorithm module;

referring to fig. 24 again, fig. 24 is a schematic diagram showing a refinement of the second polymerization processing module in fig. 22;

as shown in fig. 24, the second polymerization processing module 2132 includes:

a second rule management module 3201, configured to set an aggregation rule, where the aggregation rule includes: the number of subsets, the base address size of the subsets, and cache data brushing conditions;

specifically, the processing procedure of the second rule management module 3201 is the same as that of the first rule management module 2101, and reference may be made to the first rule management module 2101 described above, which is not described herein again.

The second identifying and aggregating module 3202 is configured to identify a logical address, determine a subset corresponding to the logical address, mount the IO operation on a corresponding subset linked list, i.e. an IO linked list, and apply for a buffer space for the IO operation;

Specifically, the processing procedure of the second recognition aggregation module 3202 is the same as that of the first recognition aggregation module 2102, and reference may be made to the first recognition aggregation module 2102, which is not described herein.

The second classification application module 3203 is configured to process the subset data, and brush the subset data out to the flash memory processing module when the subset data volume satisfies the cache data brushing condition.

Specifically, the second classification application module 3203 is configured to complete processing of operation data of a same type of logical address, for example: processing the subset IO, applying for caching for data writing, and brushing IO operation to a next module when the subset data volume meets the data brushing condition, for example: a flash memory processing module;

in the embodiment of the present application, the first aggregation processing module 2121 and the second aggregation processing module 2132 have the same functional module, and are both used for aggregation operation in the IO processing process.

Referring to fig. 26 again, fig. 26 is a schematic operation flow diagram of a sub-set linked list according to an embodiment of the present application;

as shown in fig. 26, the operation flow of the subset link list includes:

step S261: configuring corresponding parameters according to preset aggregation rules, and initializing;

specifically, the aggregation rule includes: the method comprises the steps of configuring parameters respectively corresponding to the number of subsets, the base address size of the subsets and the cache data brushing condition, and initializing the parameters to realize a preset aggregation rule.

Step S262: command checking is carried out according to the aggregation rule, and the command checking is split into IO and then is mounted to a corresponding subset linked list;

specifically, according to the received host command, the logical address is identified, the subset corresponding to the logical address is determined, and the IO operation is mounted on the corresponding IO linked list, namely the subset linked list.

Step S263: alternately processing the subset linked list, applying for the buffer memory to be distributed to IO, checking the subset data quantity, and brushing out to the next module when the data brushing condition is met;

specifically, subset data of the subset link list are processed in turn, a cache space is applied for IO operation, and when the subset data quantity meets a cache data brushing condition, the subset data is brushed out to an algorithm module or a flash memory processing module. The data brushing condition is a cache data brushing condition. Specifically, the cache data flushing condition refers to the data size meeting the same address subset, where the same address subset refers to the address range of the subset where the addresses in the command fall in the same setting. The cache data brushing condition is set according to specific requirements, for example: if the data aggregation is limited to the data size of one data page or one word line, the cache data brushing condition is that the data size of one data page or one word line is taken as a threshold value, and the cache data brushing condition is met if the threshold value is met; if the data aggregation is limited to the data size of N data pages or N word lines, the cache data flushing condition is that the data size of N data pages or N word lines is taken as a threshold value, and the cache data flushing condition is met if the threshold value is met.

Referring to fig. 27 again, fig. 27 is a schematic diagram of a host writing data according to an embodiment of the present application;

as shown in fig. 27, taking the example of writing data into a host, when the written data has commands with different logic address ranges, such as x, y, z represents the data with different address ranges, it is assumed that according to x, y, z is three logic address subsets, after aggregation, the data with different subsets are aggregated into different caches, when the cache management satisfies the data flushing condition, the data is flushed out to the flash memory, then the data have logic addresses with the same range, and then the addresses of the logic blocks can be expressed with the same base address plus different offsets when being saved in the meta information. Similarly, in garbage collection processing, the same processing method is adopted except that host writing is changed to garbage collection writing.

It will be appreciated that the present application does not focus on which page or word line data is written to, the particular page or word line data is written to being determined by the particular mapping algorithm.

In an embodiment of the present application, by providing a solid state disk controller, the method includes: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the meta information management method as described above. The logical address is stored in the form of combination of the base address and the offset, the space occupied by the logical address for occupying meta information can be reduced, and the error correction check data length can be increased, so that the integral error correction capability of the solid state disk can be improved, and the service life of the solid state disk can be prolonged.

The embodiments also provide a non-volatile computer storage medium storing computer executable instructions that are executable by one or more processors to cause the one or more processors to perform the meta-information management method in any of the method embodiments described above, for example, to perform the meta-information management method in any of the method embodiments described above.

The above-described embodiments of the apparatus or device are merely illustrative, in which the unit modules illustrated as separate components may or may not be physically separate, and the components shown as unit modules may or may not be physical units, may be located in one place, or may be distributed over multiple network module units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

From the above description of embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus a general purpose hardware platform, or may be implemented by hardware. Based on such understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the related art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for up to a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.

Claims

1. The meta-information management method is applied to a solid state disk and is characterized in that the solid state disk comprises at least one word line, each word line comprises at least two data pages, each data page comprises at least one error correction unit, and the error correction unit comprises: logic blocks and meta information, the method comprising:

storing the logical address of each meta information in the same data page or the same word line in the form of a combination of base address and offset;

the assigning the same base address to the logical addresses of the data in the same data page or the same word line comprises:

acquiring a logic address corresponding to any logic block in the same data page or the same word line;

determining subset information corresponding to the logical address according to the logical address;

acquiring a base address corresponding to the subset information according to the subset information;

the determining subset information corresponding to the logical address according to the logical address includes:

based on a pre-established logic address and a lookup table of a logic subset, inquiring the lookup table according to the logic address, and determining subset information corresponding to the logic address, wherein the subset information comprises base address information of the base address;

n logic blocks and meta information are distributed according to the size of a data page or a word line;

obtaining a logic address corresponding to any logic block, inquiring the lookup table according to the logic address, and determining subset information corresponding to the logic address;

according to the subset information corresponding to the logic address, obtaining a base address, and dividing the base address into N pieces of meta information of the same data page or word line;

at least one logical address offset is allocated to each meta-information, the logical address offset corresponding to the logical block in which the meta-information is located, such that the meta-information includes at least one sub-base address and an offset.

2. The method according to claim 1, wherein the method further comprises:

3. The method according to claim 1, wherein the method further comprises:

4. The method of claim 3, wherein the aggregating the data written to the flash memory based on the preset logical address subset rule divides the logical address of the data written to the flash memory into a plurality of subsets, and comprises:

wherein N is a positive integer, i is a non-negative integer, N is the number of subsetsBase () is the Base address of the nth subset and Mi is the size of the ith subset.

5. The method of any of claims 1-4, wherein if the meta-information includes at least two logical addresses, the meta-information includes at least two offsets, one logical address for each offset.

6. A solid state disk controller, comprising:

at least one processor; the method comprises the steps of,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the meta information management method of any one of claims 1-5.

7. The solid state disk controller of claim 6, wherein the solid state disk controller comprises a firmware system comprising:

the command processing module is used for acquiring a host command to generate IO operation;

the data processing module is connected with the command processing module and is used for receiving the IO operation sent by the command processing module and processing the IO operation;

the algorithm module is connected with the data processing module and is used for receiving the IO operation processed by the data processing module and carrying out mapping processing on the IO operation so as to determine the issued flash memory array;

the flash memory processing module is connected with the algorithm module and is used for receiving IO operation sent by the algorithm module so as to perform read-write operation on the flash memory array;

Wherein, the data processing module includes:

the first aggregation processing module is connected with the command processing module and is used for performing aggregation operation;

wherein, the algorithm module includes:

and the second aggregation processing module is connected with the flash memory processing module and is used for performing aggregation operation.

8. The solid state disk controller as claimed in claim 7, wherein,

the data processing module further comprises:

the first data caching module is connected with the first aggregation processing module and used for caching data;

the algorithm module further comprises:

the second data caching module is connected with the second polymerization processing module and is used for caching data;

and the meta information management module is connected with the first aggregation processing module and the second aggregation processing module and is used for managing meta information.

9. The solid state disk controller of claim 8 wherein,

the first aggregation processing module comprises:

the first rule management module is configured to set an aggregation rule, where the aggregation rule includes: the number of subsets, the base address size of the subsets, and cache data brushing conditions;

the first identification aggregation module is used for identifying the logic addresses, determining a subset corresponding to the logic addresses, mounting IO operations on a corresponding IO linked list, and applying for a cache space for the IO operations;

The first classification application module is used for processing the subset data, and brushing the subset data to the flash memory processing module when the subset data quantity meets the cache data brushing condition;

the second polymerization processing module comprises:

the second rule management module is configured to set an aggregation rule, where the aggregation rule includes: the number of subsets, the base address size of the subsets, and cache data brushing conditions;

the second recognition aggregation module is used for recognizing the logic address, determining a subset corresponding to the logic address, mounting IO operation on a corresponding IO linked list and applying for a cache space for the IO operation;

and the second classification application module is used for processing the subset data, and brushing the subset data to the flash memory processing module when the subset data quantity meets the cache data brushing condition.

10. A solid state disk, comprising:

the solid state disk controller of any of claims 6-9.