CN113722082A

CN113722082A - Task scheduling method, device, system and computer readable medium

Info

Publication number: CN113722082A
Application number: CN202010448027.2A
Authority: CN
Inventors: 王晓巍
Original assignee: Alibaba Group Holding Ltd
Current assignee: Alibaba Group Holding Ltd
Priority date: 2020-05-25
Filing date: 2020-05-25
Publication date: 2021-11-30

Abstract

The embodiment of the specification provides a task scheduling method, a task scheduling device, a task scheduling system and a computer readable medium, wherein the method comprises the following steps: forming at least two program copies of a task to be scheduled; placing the at least two program copies in program segments of at least two processors of an asymmetric multiprocessing system; determining a running processor running the task based on the current running conditions of the at least two processors; and running the corresponding program segment of the task on the running processor.

Description

Task scheduling method, device, system and computer readable medium

Technical Field

The present specification relates to the field of asymmetric multiprocessing technologies, and more particularly, to a task scheduling method for an asymmetric multiprocessing system, a task scheduling apparatus for an asymmetric multiprocessing system, an intelligent voice assistant system, and a computer-readable medium.

Background

Under an Asymmetric Multiprocessing (AMP) architecture, there are multiple processors (cores). These processors may include the same or different Central Processing Units (CPUs), or other processing devices. Each processor is assigned to perform a particular task at a particular time. A task is a basic unit of work to be performed by a processor and may be one or more sequences of instructions processed by a control program.

FIG. 8 illustrates an asymmetric multiprocessing system. At the hardware level in FIG. 8, the asymmetric multi-processing system 80 includes two processor CPUs 0, 1 and respective memories 0, 1. The memories 0, 1 are used to store programs, data, etc. of the respective processors. The memories 0, 1 may be two different memories or may be different partitions of the same memory.

At the software layer in FIG. 8, an operating system runs on each processor. Operating system OS0 runs on CPU0, and operating system OS1 runs on CPU 1. OS0 and OS1 are two separate operating systems. The OS0 may be designated as the main processor. The main processor OS0 allocates tasks to be performed to OS0 or OS 1.

In fig. 8, the OS0 executes tasks T0 and T1, and the OS1 executes tasks T2 and T3. Data may be transferred between the two operating systems through inter-processor communication. Tasks T0, T1, T2, T3 running on different processors are independent of each other.

In the asymmetric multiprocessing system of fig. 8, the tasks running on the different processors need to be determined at system compile time of the application. In the actual operation, sometimes, more tasks are run on the CPU1 and fewer tasks are run on the CPU 0. In this case, in the asymmetric multiprocessing system, the task of the CPU1 cannot be transferred to the CPU 0. In this case, the balance of the system is not facilitated.

Furthermore, when there is insufficient resources on the CPU0, the tasks of the CPU0 cannot be transferred to the CPU1 for execution. In this case, the processing of the system may be interrupted and processing efficiency is affected.

Therefore, there is a need for a task scheduling scheme for an asymmetric multiprocessing system that balances the processing loads of the different processors.

Disclosure of Invention

Embodiments of the present description provide a new task scheduling scheme for asymmetric multiprocessing systems.

According to a first aspect of the present specification, there is provided a task scheduling method for an asymmetric multiprocessing system, comprising: forming at least two program copies of a task to be scheduled; placing the at least two program copies in program segments of at least two processors of an asymmetric multiprocessing system; determining a running processor running the task based on the current running conditions of the at least two processors; and running the corresponding program segment of the task on the running processor.

According to a second aspect of the present specification, there is provided a task scheduling apparatus for an asymmetric multiprocessing system, comprising: a forming unit that forms at least two program copies of a task to be scheduled; a placing unit that places the at least two program copies in program segments of at least two processors of the asymmetric multiprocessing system; a determination unit that determines a running processor that runs the task based on current running conditions of the at least two processors; and an execution unit that executes a corresponding program segment of the task on the execution processor.

According to a third aspect of the present specification, there is provided an asymmetric multiprocessing system comprising: the scheduling method comprises a main processor and at least one subordinate processor, wherein at least two program copies of a task to be scheduled are placed in program segments of at least two processors of the main processor and the subordinate processors, and the main processor is used for determining a running processor for running the task and corresponding program segments of the task to be run by the running processor based on current running conditions of the at least two processors.

According to a fourth aspect of the present specification, there is provided an intelligent voice assistant system, comprising a master processor and at least one slave processor, wherein at least two program copies of a task to be scheduled are placed in program segments of at least two of the master processor and slave processors, the master processor being configured to determine a running processor to run the task based on current operating conditions of the at least two processors, and to run a corresponding program segment of the task by the running processor.

According to a fifth aspect of the present specification, there is provided a computer readable medium storing executable instructions that when executed implement the method described above.

According to a sixth aspect of the present specification, there is provided a method of task scheduling in an intelligent voice assistant system, wherein the intelligent voice system includes at least two asymmetric processors, and the method includes: compiling a task to be scheduled to generate at least two program copies; presetting the requirements of the tasks on the processor; placing the at least two program copies in program segments of the at least two asymmetric processors; determining a running processor to run the task based on the current operating conditions of the at least two processors and the requirement; and running the corresponding program segment of the task on the running processor.

In various embodiments, the load between processors is balanced by scheduling tasks to be executed between the different processors based on the current operating conditions of the processors.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of embodiments of the invention.

In addition, any one of the embodiments in the present specification is not required to achieve all of the effects described above.

Other features of embodiments of the present specification and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

In order to more clearly illustrate the embodiments of the present specification or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the embodiments of the present specification, and other drawings can be obtained by those skilled in the art according to the drawings.

FIG. 1 shows a schematic flow diagram of a task scheduling method for an asymmetric multiprocessing system according to one embodiment.

FIG. 2 shows a schematic block diagram of a task scheduling apparatus for an asymmetric multiprocessing system according to an embodiment.

FIG. 3 illustrates an exemplary system architecture of an asymmetric multi-processing system according to one embodiment.

FIG. 4 illustrates a schematic hardware block diagram of an asymmetric multiprocessing system according to one embodiment.

FIG. 5 illustrates an exemplary system architecture of an asymmetric multi-processing system in accordance with another embodiment.

FIG. 6 illustrates a schematic block diagram of an intelligent voice assistant system according to one embodiment.

FIG. 7 illustrates a network diagram including an asymmetric multiprocessing system according to one embodiment.

FIG. 8 shows an exemplary system architecture for an asymmetric multi-processing system.

Detailed Description

In the following, different embodiments and examples of the present description are described with reference to the drawings.

As shown in FIG. 1, at step S12, at least two program copies of a task to be scheduled are formed.

At step S14, the at least two program copies are placed in program segments of at least two processors of the asymmetric multiprocessing system. At least two processors of the asymmetric multiprocessing system may be homogeneous, i.e. the same processor; or may be heterogeneous, i.e., different types of processors.

A task is a basic work element to be executed by a processor. For example, in the application context of the intelligent voice assistant, the task of controlling voice reception, the task of packaging voice, the task of sending a language packet to the cloud end, the task of receiving a returned response data packet, the task of decoding a corresponding response data packet, and the task of playing the response data packet may be included. In addition, the intelligent voice assistant may also include tasks to monitor power conditions, monitor network conditions, monitor whether the input signal is user voice, and the like. In an asymmetric multiprocessing system, these tasks may be performed in different processors.

In step S16, a running processor that runs the task is determined based on the current operating conditions of the at least two processors.

In step S18, the corresponding program segment of the task is run on the run processor.

In an asymmetric multiprocessing system, the manner in which the application is compiled may be calculated in various manners and the various tasks may be distributed to the operating systems assigned to the various processors. However, this task scheduling approach is a priori. In this case, it is impossible to select an appropriate processor in real time to execute the task currently to be executed according to the current operating condition of the processor. Furthermore, this can be an inefficient way of operating the system if each processor is scheduled for performance, etc., by merely adjusting the hardware resources (e.g., memory resources, power, etc.) allocated to each processor. Furthermore, the degree of freedom of this scheduling approach is limited.

At least two copies of the program are provided in program segments of at least two processors, respectively. Thus, the appropriate processor can be selected in real time to perform the task based on the current operating conditions of the processor. In this way, the load on the processor can be made more balanced than in the prior art.

The running processor running the task may be determined from the current occupancy of the different processors. For example, an asymmetric multiprocessing system includes two processors, CPU0 and CPU 1. The current occupancy of the processor CPU0 is 80%, and the current occupancy of the processor CPU1 is 50%. In this case, the processor CPU1 may be determined to be running a processor and running the current task on the CPU 1. Thereby making the load on both processors more even.

It is also possible to estimate the occupancy of each task to different processors in advance and store these occupancies in a configuration file. In determining to run the processors, the running processors may be determined based on the current occupancy of at least two processors and the occupancy in the configuration file. For example, the current occupancy of the processor CPU0 is 60%, and the current occupancy of the processor CPU1 is 50%. The occupancy rate of the tasks to be executed for the CPU0 is 10%, and the occupancy rate for the CPU1 is 25%. In this case, the processor CPU0 may be selected to run the task. In this way, large differences in the occupancy of different processors can be avoided.

The requirements of each task in the application program for the processor can be preset at the time of application program development, and when determining to run the processor, the running processor for executing the task is determined based on the requirements. For example, in the context of an intelligent voice assistant application, the task of monitoring whether the input signal is user speech requires less processor computing power, but requires that the task be run throughout the entire run of the system. Such tasks may be associated with slower processing and lower power processors at the time of application development. Further, the task of decoding the response packet, for example, requires a high processor effort, but does not require a long processor time. Such tasks may be associated with processors that process faster at the time of application development. In determining the operating processor, the operating processor may be determined in consideration of these requirements, thereby providing efficiency in use of the system.

In some cases, the processors of an asymmetric multi-processing system are located in different physical electronic devices or locations. For example, in a multi-room sound system, one processor may be provided in each sound, and these processors may be combined into an asymmetric multi-processor system. In this case, each entity device may include a battery so as to be able to have high mobility. Determining the running processor based on battery power of an electronic device in which at least two processors are located. In this way, it is possible to make it possible to consume the respective electronic devices on average to some extent, thereby extending the use time of the entire system.

Furthermore, in an asymmetric multiprocessing system, the power consumption of some processors is higher and the power consumption of some processors is lower. The processor with lower power consumption may be preferentially determined as the running processor, thereby reducing power consumption of the entire system.

In addition, by the mode, a protection mechanism of the system can be realized, and the influence on the use of a user due to the fact that equipment cannot run caused by faults is avoided. For example, in the case of an exception of the currently running processor, another of the at least two processors may be set as a standby running processor, and the corresponding program segment of the current task is run on the standby running processor. In this way, when a processor fails, the entire system can still operate, which does not cause an immediate stop for the user's use.

In an asymmetric multiprocessing system, one of the at least two processors may be set as a master processor. The running processor may be determined by the main processor.

In one example, to further enhance the user's use experience, the running processor may also be determined based on how often the user uses the task. For example, in the context of an application of an intelligent voice assistant, a user often issues instructions. In this case, it is necessary to receive a voice instruction of the user and transmit the voice instruction to the network. Therefore, the task for packaging the voice and the task for sending the language package to the cloud end can be distributed to the processor with higher speed, so that the instruction of the user can be responded in time, and the use experience of the user is improved.

The above described method may be embodied in a computer readable medium and the above described solution may be deployed by the computer readable medium into an asymmetric multiprocessing system. The computer readable medium can store executable instructions that when executed perform the above-described method.

As shown in fig. 2, the task scheduler 20 includes: a forming unit 22 that forms at least two program copies of a task to be scheduled; a placing unit 24 that places the at least two program copies in program segments of at least two processors of the asymmetric multiprocessing system; a determination unit 26 that determines a running processor that runs the task based on current operating conditions of the at least two processors; and an execution unit 28, on which the respective program segments of the tasks are executed.

The task scheduler 20 shown in fig. 2 may perform the steps of the method shown in fig. 1. For example, the determination unit 26 may determine the running processor based on the current occupancy of the different processors.

The task scheduling device 20 may further comprise an estimation unit (not shown) for estimating the occupancy of the processor by the tasks and storing the occupancy in a configuration file. The determination unit 26 may also determine the running processor based on the current occupancy of the at least two processors and the occupancy in the configuration file.

The determination unit 26 may also determine the running processor based on the battery level of the electronic device in which the at least two processors are located.

The determination unit 26 may further determine a processor with lower power consumption of the at least two processors as the running processor.

In addition, the task scheduling device 20 may set another of the at least two processors as a standby running processor in case of an exception of the currently running processor; and running the corresponding program segment of the task on the standby running processor.

One of the at least two processors may be set as a main processor. The determination means 26 may be provided in the main processor to determine the running processor.

As shown in fig. 3, at the hardware level, the asymmetric multiprocessing system 30 includes: a master processor CPU0 and at least one slave processor CPU 1. Although only one coprocessor CPU1 is shown, the asymmetric multiprocessing system 30 may also include other coprocessors. Fig. 3 also shows memory 0 and memory 1 for storing data and programs for the processors CPU0 and CPU1, respectively. Memory 0 and memory 1 may be two different memories or may be the same and/or different partitions of the same memory.

At the software level, at least two program copies of a task to be scheduled may be placed in program segments of at least two of the master processor CPU0 and the slave processor CPU 1. In the embodiment shown in FIG. 3, program copies are placed into the master processor CPU0 and slave processor CPU1, respectively. As shown in fig. 3, operating system OS0 runs on CPU0, and operating system OS1 runs on CPU 1. OS0 and OS1 may be the same or different operating systems. In the program segment of the CPU0, task copies T0, T1, T2, T3 are placed; in the program segment of the CPU1, task copies T0 ', T1', T2 ', T3' are placed.

The main processor CPU0 may determine the running processor running the task and the corresponding program segment for the running processor to run the task based on the current operating conditions of the at least two processors CPU0, CPU 1.

The processor shown in fig. 3 may perform the method described in fig. 1, and a repeated description thereof will not be provided.

Fig. 3 illustrates an architecture in which a software layer and a hardware layer are combined in an asymmetric multiprocessing system. At the hardware level, an asymmetric multiprocessing system may also include many other hardware components. Fig. 4 shows a schematic hardware block diagram according to an asymmetric multiprocessing system.

As shown in FIG. 4, an asymmetric multiprocessing system 400 includes a plurality of processors 402 and a plurality of memories 404. As previously described, the processors 402 may be homogeneous or heterogeneous. The multiple memories 404 may be multiple physical memories or may be different/same partitions of the same memory.

The asymmetric multi-processing system 400 may also include a display screen 410, a user interface 412, a camera 414, an audio/video interface 416, a sensor 418, and a communications component 420, among other things. The asymmetric multiprocessor system 400 may further include a power management chip 406, a battery 408, and the like. The asymmetric multi-processing system 400 may be implemented with a variety of intelligent devices, and the like.

The processor 402 may be various processors. The memory 404 may store the underlying software, system software, application software, data, etc. needed for the operation of the asymmetric multi-processing system 400. The memory 404 may include various forms of memory, such as ROM, RAM, Flash, etc.

The display screen 410 may be a liquid crystal display screen, an OLED display screen, or the like. In one example, the display screen 410 may be a touch screen. The user can perform an input operation through the display screen 410. In addition, the user can also perform fingerprint identification and the like through the touch screen.

The user interface 412 may include a USB interface, a lightning interface, a keyboard, and the like.

The camera 414 may be a single camera or multiple cameras. In addition, camera 414 may be used for face recognition by the user.

The audio/video interface 416 may include, for example, a speaker interface, a microphone interface, a video transmission interface such as HDMI, and the like.

The sensors 418 may include, for example, gyroscopes, accelerometers, temperature sensors, humidity sensors, pressure sensors, and the like. For example, the environment around the asymmetric multiprocessing system, etc. may be determined by sensors.

The communication component 420 may include, for example, a WiFi communication component, a bluetooth communication component, a 3G, 4G, and 5G communication component, and the like. Through communications component 420, asymmetric multiprocessing system 400 may be arranged in a network.

The power management chip 406 may be used to manage the power of the input asymmetric multiprocessor system 400 and may also manage the battery 408 to ensure greater utilization efficiency. The battery 408 is, for example, a lithium ion battery or the like.

The asymmetric multi-processing system shown in FIG. 4 is illustrative only and is not intended to limit the embodiments herein, their applications, or uses in any way.

The asymmetric multi-processing system 50 shown in fig. 5 includes a master device 50a and at least one slave device 50 b. The master processor CPU0 is located in the master device 50a, and the at least one slave processor CPU1 is located in the at least one slave processor CPU1, respectively. Master device 50a and at least one slave device 50b communicate via a signal connection. The signal connection here may be a wired signal connection, a wireless signal connection, or the like.

The asymmetric multi-processing system 50 may also include speakers 51a, 51b,

microphones

52a, 52b,

communication components

53a, 53b, and power supplies 54a, 54b, etc.

The various devices of the asymmetric multi-processing system shown in fig. 5 may be distributed in a number of different locations. In this case, the tasks to be executed can be distributed equally among the various devices by the solution presented here. In this way, the processing amount of each device can be equalized, and the power consumption of each device can be equalized. In addition, a protection mechanism can be started under the condition that a certain device fails, and the interruption of the whole asymmetric multiprocessing system is prevented.

FIG. 6 illustrates a schematic block diagram of an intelligent voice assistant system according to one embodiment. The technical solution disclosed herein is employed in the intelligent voice assistant system of fig. 6. As shown in FIG. 6, the intelligent voice assistant system 60 comprises a master processor CPU0 and at least one slave processor CPU 1.

At least two program copies of the task to be scheduled are placed in program segments of at least two of the master processor CPU0 and the coprocessor CPU1, respectively. As shown in fig. 6, operating system OS0 runs on CPU0, and operating system OS1 runs on CPU 1. OS0 and OS1 may be the same or different operating systems. In the program segment of the CPU0, task copies T0, T1, T2, T3 are placed; in the program segment of the CPU1, task copies T0 ', T1', T2 ', T3' are placed.

The main processor CPU0 is used to determine the running processor to run the task based on the current operating conditions of at least two processors. And executing the corresponding program segment of the task by the execution processor.

The asymmetric multi-processing system 60 may also include a speaker 61, a microphone 62, a communication component 63, a power supply 64, and the like.

FIG. 7 illustrates a network diagram including an intelligent voice assistant system according to one embodiment.

As shown in fig. 7, the network 710 includes

servers

722, 724. The servers in the network 710 may also be referred to as "cloud". The intelligent voice assistant system 730 is connected to the network 710 and to the cloud.

The intelligent voice assistant system 730 includes a master processor CPU0 and at least one slave processor CPU 1. The intelligent voice assistant system 730 also includes memory 0 and memory 1. The intelligent voice assistant system 730 also includes a speaker 731, a microphone 732, a communication component 733, and a power supply 734, among other things.

For example, the processor CPU0 performs voice processing tasks and the CPU1 performs voice playback tasks. The user may speak a command voice, e.g., "temperature today," to the intelligent voice assistant system 730. The processor CPU0 receives the command voice signal through the microphone 732. The processor CPU0 sends the command voice signal to the cloud 722 for processing at 724 via the communication component 733. The cloud returns the processing results to the intelligent voice assistant system 730. The CPU1 processes the processing result, for example, "temperature today is 20 degrees". The CPU1 controls the speaker 731 to play sound: "today's temperature is 20 degrees".

Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer-readable media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.

From the above description of the embodiments, it is clear to those skilled in the art that the embodiments of the present disclosure can be implemented by software plus necessary general hardware platform. Based on such understanding, the technical solutions of the embodiments of the present specification may be essentially or partially implemented in the form of a software product, which may be stored in a computer-readable medium, such as a ROM/RAM, a magnetic disk, an optical disk, or the like, and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute the methods described in the embodiments or some parts of the embodiments of the present specification.

The systems, devices, modules or units illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product with certain functions. A typical implementation device is a computer, which may take the form of a personal computer, laptop computer, cellular telephone, camera phone, smart phone, personal digital assistant, media player, navigation device, email messaging device, game console, tablet computer, wearable device, or a combination of any of these devices.

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment. The above-described apparatus embodiments are merely illustrative, and the modules described as separate components may or may not be physically separate, and the functions of the modules may be implemented in one or more software and/or hardware when implementing the embodiments of the present disclosure. And part or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of the embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.

The foregoing is only a specific embodiment of the embodiments of the present disclosure, and it should be noted that, for those skilled in the art, a plurality of modifications and decorations can be made without departing from the principle of the embodiments of the present disclosure, and these modifications and decorations should also be regarded as the protection scope of the embodiments of the present disclosure.

Claims

1. A method of task scheduling for an asymmetric multiprocessing system, comprising:

forming at least two program copies of a task to be scheduled;

placing the at least two program copies in program segments of at least two processors of an asymmetric multiprocessing system;

determining a running processor running the task based on the current running conditions of the at least two processors; and

and running the corresponding program segment of the task on the running processor.

2. The method of claim 1, wherein determining a running processor to run the task based on current operating conditions of the at least two processors comprises:

determining the running processor based on the current occupancy of the different processors.

3. The method of claim 1, further comprising:

estimating the occupancy rate of the task to a processor; and

storing the occupancy in a configuration file,

wherein determining a running processor to run the task based on the current operating conditions of the at least two processors comprises:

determining the running processor based on the current occupancy of the at least two processors and the occupancy in the configuration file.

4. The method of claim 1, wherein determining a running processor to run the task based on current operating conditions of the at least two processors comprises:

determining the running processor based on battery power of the electronic device where the at least two processors are located.

5. The method of claim 1, further comprising:

and determining a processor with lower power consumption in the at least two processors as the running processor.

6. The method of claim 1, further comprising:

under the condition that the current running processor is abnormal, setting another processor of the at least two processors as a standby running processor; and

and running the corresponding program segment of the task on the standby running processor.

7. The method of claim 1, further comprising:

setting one of the at least two processors as a master processor;

wherein determining a running processor to run the task based on the current operating conditions of the at least two processors comprises: determining, by the main processor, the running processor.

8. A task scheduler for an asymmetric multiprocessing system, comprising:

a forming unit that forms at least two program copies of a task to be scheduled;

a placing unit that places the at least two program copies in program segments of at least two processors of the asymmetric multiprocessing system;

a determination unit that determines a running processor that runs the task based on current running conditions of the at least two processors; and

and the operation unit is used for operating the corresponding program segment of the task on the operation processor.

9. An asymmetric multiprocessing system comprising: a master processor and at least one slave processor,

wherein at least two program copies of a task to be scheduled are placed in program segments of at least two of the master processor and co-slave processors, the master processor being configured to determine a running processor to run the task based on current operating conditions of the at least two processors, and to run the corresponding program segment of the task by the running processor.

10. The system of claim 9, comprising: the master device is positioned in the master device, the at least one slave processor is respectively positioned in the at least one slave device, and the master device and the at least one slave device are communicated through signal connection.

11. An intelligent voice assistant system comprises a main processor and at least one assistant processor,

12. A computer-readable medium storing executable instructions that, when executed, implement the method of any one of claims 1-7.

13. A method of task scheduling in an intelligent voice assistant system, wherein the intelligent voice system includes at least two asymmetric processors, and the method comprises:

compiling a task to be scheduled to generate at least two program copies;

presetting the requirements of the tasks on the processor;

placing the at least two program copies in program segments of the at least two asymmetric processors;

determining a running processor to run the task based on the current operating conditions of the at least two processors and the requirement; and

14. The method of claim 13, wherein determining a running processor to run the task based on current operating conditions of the at least two processors and the requirements comprises:

determining the running processor based on a frequency with which the task is used.

15. The method of claim 14, wherein determining the running processor based on the frequency with which the task is used comprises:

for the task with higher use frequency, the processor with higher processing speed in the at least two processors is determined as the running processor.

16. The method of claim 13, wherein the task is a basic work element to be executed by the processor.