CN113721132A - LED circuit board testing method - Google Patents
LED circuit board testing method Download PDFInfo
- Publication number
- CN113721132A CN113721132A CN202111044722.3A CN202111044722A CN113721132A CN 113721132 A CN113721132 A CN 113721132A CN 202111044722 A CN202111044722 A CN 202111044722A CN 113721132 A CN113721132 A CN 113721132A
- Authority
- CN
- China
- Prior art keywords
- test
- testing
- sub
- network
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 346
- 239000011159 matrix material Substances 0.000 claims abstract description 48
- 230000003287 optical effect Effects 0.000 claims abstract description 27
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000005476 soldering Methods 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 14
- 229910000679 solder Inorganic materials 0.000 claims description 43
- 238000006073 displacement reaction Methods 0.000 claims description 6
- 238000010899 nucleation Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 239000011324 bead Substances 0.000 description 3
- 238000010998 test method Methods 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- G01B11/00—Measuring arrangements characterised by the use of optical techniques
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
The invention relates to the technical field of circuit board testing, and discloses a method for testing an LED circuit board, which comprises the following steps: based on a preset region splitting mode, splitting a soldering tin surface test lattice of the LED circuit board into N test sub-network lattices, wherein each test sub-network lattice has the same circuit connection relation, the test lattice has the same electrical connection relation with the part surface test lattice of the LED circuit board, the soldering tin surface test lattice and the test sub-network lattice are determinant matrixes, arranging M alignment optical points on each test sub-network lattice, seeding test needles on a test fixture according to the part surface test lattice and the test sub-network lattice, arranging a CCD camera device on the test fixture, capturing the positions of the alignment optical points through the CCD camera device, the testing sub-network dot matrix is positioned, and the testing jig with the testing needles is adopted to sequentially test the N testing sub-network dot matrices, so that the density and the number of the testing dot matrices in the same testing area are reduced, and the testing precision of the LED circuit board is improved.
Description
Technical Field
The invention relates to the technical field of circuit board testing, in particular to a method for testing an LED circuit board.
Background
In recent years, the commercial application of LED screens is more and more extensive, and the pixel dot matrix required for the screens is more and more dense, so that Mini LED circuit boards and Micro LED circuit boards are simultaneously emerging, wherein the Mini LED circuit boards require the LED chip size to be less than 100 micrometers, and the Micro LED circuit boards require the LED chip size to be less than 50 micrometers. The size of the testing bonding pad of the Mini LED circuit board and the Micro LED circuit board is the same as that of the LED chip, the testing bonding pad is only 50-100 micrometers, the integration density is high, when the Mini LED circuit board and the Micro LED circuit board are tested, the number of testing points reaches hundreds of thousands, even hundreds of thousands, and the testing precision reaches +/-10 micrometers. The denser the lattice density, the greater the test difficulty, the test precision within the industry at present is +/-34 microns, and the test precision requirements of the Mini LED circuit board and the Micro LED circuit board are far less.
Disclosure of Invention
The embodiment of the invention provides a method for testing an LED circuit board, which reduces the density and the number of test lattices in the same test area so as to improve the test precision of the LED circuit board.
In order to solve the above technical problem, an embodiment of the present application provides a method for testing an LED circuit board, including:
splitting a soldering tin surface test lattice of the LED circuit board into N test sub-network lattices based on a preset region splitting mode, wherein each test sub-network lattice has the same circuit connection relation and has the same electric connection relation with a part surface test lattice of the LED circuit board, the soldering tin surface test lattice and the test sub-network lattices are determinant matrixes, the soldering tin surface test lattices correspond to LED pads on the LED circuit board one by one, the part surface test lattices correspond to component pads on the LED circuit board one by one, and N is a positive integer greater than 0;
setting M alignment optical points on each test sub-network lattice, wherein M is a positive integer greater than 0;
planting a test needle on a test fixture according to the part surface test dot matrix and the test sub-network dot matrix, wherein the test fixture is provided with CCD camera equipment;
when the LED circuit board is tested, the position of the alignment optical point is captured through the CCD camera shooting equipment;
and positioning the sub-network dot matrix according to the position of the alignment optical point, and sequentially testing the N sub-network dot matrixes by adopting a testing jig with testing needles.
The circuit board testing method provided by the embodiment of the invention is characterized in that based on a preset region splitting mode, a soldering tin surface testing lattice of an LED circuit board is split into N testing sub-network lattices, each testing sub-network lattice has the same circuit connection relation and has the same electric connection relation with a part surface testing lattice of the LED circuit board, the soldering tin surface testing lattice and the testing sub-network lattices are row-column matrixes, the soldering tin surface testing lattice corresponds to LED pads on the LED circuit board one by one, the part surface testing lattice corresponds to component pads on the LED circuit board one by one, wherein N is a positive integer larger than 0, M contraposition optical points are arranged on each testing sub-network lattice, M is a positive integer larger than 0, testing needles are planted on a testing jig according to the part surface testing lattice and the testing sub-network lattices, and the testing jig is provided with a CCD camera device, when the LED circuit board is tested, the position of the alignment optical point is captured through the CCD camera equipment, the sub-network testing dot matrix is positioned according to the position of the alignment optical point, and the testing jig with the testing pins is adopted to sequentially test the N sub-network testing dot matrices, so that the density and the number of the testing dot matrices in the same testing area are reduced, and the testing precision of the LED circuit board is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
FIG. 1 is a flow chart of one embodiment of an LED wiring board testing method of the present application;
FIG. 2 is a schematic diagram of a solder surface test dot matrix division according to an embodiment of the LED circuit board test method of the present application;
FIG. 3 is a schematic diagram of a solder surface test dot matrix division of another embodiment of the LED circuit board test method of the present application;
FIG. 4 is a schematic diagram of a solder surface test dot matrix division of an embodiment of the LED circuit board test method of the present application;
fig. 5 is a schematic structural diagram of a testing machine according to an embodiment of the LED circuit board testing method of the present application.
Detailed Description
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "including" and "having," and any variations thereof, in the description and claims of this application and the description of the above figures are intended to cover non-exclusive inclusions.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 shows a testing method of an LED circuit board according to an embodiment of the present invention, which is detailed as follows:
s101: the method comprises the steps that a soldering tin surface test dot matrix of the LED circuit board is split into N test sub-network dot matrixes based on a preset region splitting mode, each test sub-network dot matrix has the same circuit connection relation and has the same electric connection relation with a part surface test dot matrix of the LED circuit board, the soldering tin surface test dot matrix and the test sub-network dot matrix are determinant matrixes, the soldering tin surface test dot matrixes correspond to LED bonding pads on the LED circuit board one by one, the part surface test dot matrixes correspond to component bonding pads on the LED circuit board one by one, and N is a positive integer larger than 0.
Specifically, the preset area division mode is mainly characterized in that circuit networks of the LED circuit boards are screened according to corresponding conduction and insulation logic relation rules through circuit board analysis software, the LED circuit board welding surface test dot matrixes are divided into N test sub-network dot matrixes, it is ensured that each test sub-network dot matrix is completely the same, each test sub-network dot matrix has the same conduction relation and insulation relation, component bonding pads are used for a plurality of welding components, the LED bonding pads are used for welding a plurality of LED lamp beads, the components are used for controlling the work of the LED lamp beads, such as the brightness and the darkness of the LED lamp beads, the LED circuit boards include but are not limited to Mini LED circuit boards and Micro LED circuit boards, and the circuit networks of the soldering tin surface test dot matrixes of the LED circuit boards are characterized in a high-density matrix distribution mode.
S102: and arranging M alignment optical points on each test sub-network lattice, wherein M is a positive integer larger than 0.
Specifically, the alignment optical point of the test sub-network may be disposed above each row of solder surface test points in each test sub-network dot matrix, and in this step, the test sub-network dot matrix is positioned by the alignment optical point, so as to determine the position of each test sub-network dot matrix on the LED circuit board, thereby improving the test accuracy of the LED circuit board.
Optionally, the circuit network of the soldering tin surface test lattice based on the LED circuit board is distributed in a high-density matrix form, and alignment optical points are arranged around the LED bonding pads on the LED circuit board for positioning each LED bonding pad, so as to determine the positions of each soldering tin surface point and the part surface lattice in each test sub-network lattice on the LED circuit board, thereby improving the test precision of the LED circuit board.
S103: and (4) planting test needles on the test fixture according to the part surface test dot matrix and the test sub-network dot matrix, wherein the test fixture is provided with CCD camera equipment.
Specifically, the test fixture comprises an upper part and a lower part, and is a fixture specially used for testing the circuit of the LED circuit board, the CCD camera equipment is camera equipment with a CDD (charge coupled device), the CCD camera equipment is arranged on an upper die of the test fixture, the upper die of the test fixture is used for testing the sub-network dot matrix, and the lower die of the test fixture is used for testing the part surface test dot matrix.
S104: when the LED circuit board is tested, the position of the alignment optical point is captured through CCD camera equipment.
Specifically, the positions of the alignment optical points of the sub-network dot matrixes to be tested on the LED circuit board are captured through the CCD camera equipment, so that the positions of the sub-network dot matrixes to be tested can be determined, and the testing precision of the LED circuit board is improved.
S105: and positioning the sub-network dot matrix according to the position of the alignment optical point, and sequentially testing the N sub-network dot matrixes by adopting a testing jig with testing needles.
Specifically, the test sub-network dot matrix is determined by aligning the position of the optical point, then the test jig with the test needle is adopted to sequentially test the N test sub-network dot matrixes according to the arrangement sequence of each test sub-network dot matrix on the LED circuit board, or the test sub-network dot matrix is determined by aligning the position of the optical point, and then the test jig with the test needle is adopted to randomly sequentially test the N test sub-network dot matrixes on the LED circuit board.
The circuit board testing method provided by the embodiment of the invention is characterized in that based on a preset region splitting mode, a soldering tin surface testing lattice of an LED circuit board is split into N testing sub-network lattices, each testing sub-network lattice has the same circuit connection relation and has the same electric connection relation with a part surface testing lattice of the LED circuit board, the soldering tin surface testing lattice and the testing sub-network lattices are row-column matrixes, the soldering tin surface testing lattice corresponds to LED pads on the LED circuit board one by one, the part surface testing lattice corresponds to component pads on the LED circuit board one by one, wherein N is a positive integer larger than 0, M contraposition optical points are arranged on each testing sub-network lattice, M is a positive integer larger than 0, testing needles are planted on a testing jig according to the part surface testing lattice and the testing sub-network lattices, and the testing jig is provided with a CCD camera device, when the LED circuit board is tested, the position of the alignment optical point is captured through the CCD camera equipment, the sub-network testing dot matrix is positioned according to the position of the alignment optical point, and the testing jig with the testing pins is adopted to sequentially test the N sub-network testing dot matrices, so that the density and the number of the testing dot matrices in the same testing area are reduced, and the testing precision of the LED circuit board is improved.
In some optional implementation manners of this embodiment, in step S105, sequentially testing the N test sub-network lattices by using the test fixture includes:
the testing jig is installed on a testing machine, wherein the testing jig comprises an upper die and a lower die, the upper die is used for planting testing needles corresponding to the sub-network testing dot matrix, the lower die is used for planting testing needles corresponding to the part surface testing dot matrix, the testing machine comprises an upper table board and a lower table board, the lower film is installed on the lower table board, the upper die is installed on the upper table board, and the upper table board has a displacement testing function.
And arranging the LED circuit board between the lower die and the upper die through the clamping jaw mechanism, wherein the test sub-network dot matrix is contacted with the upper die, and the part surface test dot matrix is contacted with the lower die.
When the LED circuit board is tested, the upper table top is moved to sequentially test the sub-network testing lattices, and the lower table top is kept still.
Specifically, as shown in fig. 5, a testing jig with a testing needle is mounted on a testing machine with a displacement function and fixed, then an LED circuit board is placed between an upper die and a lower die of the testing jig through a clamping jaw mechanism, a CCD camera mounted on the testing jig is used for grabbing the counterpoint optical points of the lattice of the testing sub-network on the LED circuit board during testing and transmitting the counterpoint optical points to a control system through a data line, the control system controls the testing machine to test the testing sub-network on the LED circuit board, in this step, the CCD camera mounted on the testing jig is used for grabbing the counterpoint optical points of the lattice of the testing sub-network on the LED circuit board, and the accuracy of the position of the lattice of the testing sub-network can reach +/-10um through the counterpoint optical points.
In one embodiment, sequentially testing the sub-network lattices by moving the upper table comprises:
after one of the N test sub-network lattices is tested, the upper table top automatically moves to the next positioned test sub-network lattice for testing until the tests of the N test sub-network lattices are sequentially completed.
Specifically, a displacement distance can be set for the upper table top of the testing machine through the control system, the displacement distance can be set according to an actual application scene, the upper table top of the testing machine can automatically move to each testing sub-network dot matrix according to the displacement distance to perform testing until the testing of the N testing sub-network dot matrices is completed in sequence, and in the process of performing mobile testing on the upper table top of the testing machine, the lower table top of the testing machine is kept still, so that the testing needles on the lower die of the testing jig are continuously kept in contact with the part surface testing dot matrix.
In this embodiment, the same test fixture is used to test each sub-network dot matrix, so that the number of test points of the LED circuit board is reduced, the test density is reduced, the test yield is effectively improved, and the manufacturing cost of the test fixture is reduced, for example, a set of test fixture with 20 ten thousand test points can be divided into 10 tests, and 2 ten thousand test points at a time. Only 2 ten thousand test needles are needed, and 18 ten thousand test needles are saved.
In one embodiment, the part surface test lattice comprises Y part surface test points, the number of the seed test needles is Y, the test sub-network lattice comprises X solder surface test points, the number of the seed test needles is Y/N, and X, Y is a positive integer larger than 0.
For example, as shown in fig. 4, the LED circuit board includes two sub-network test dot matrixes, where the first sub-network test dot matrix is 3 solder surface test points identified as 1, the second sub-network test dot matrix is 2 solder surface test points identified as 2, and the number of the part surface test points is 1.
In one embodiment, the component surface test points are in electrical connection with the corresponding solder surface test points.
For example, as shown in fig. 4, the LED circuit board includes two sub-network test dot matrixes, where the first sub-network test dot matrix is composed of 3 solder surface test points and component surface test points, the second sub-network test dot matrix is composed of 2 solder surface test points and component surface test points, and the component surface test points and the solder surface test points are electrically connected.
In one embodiment, N-1 columns of solder surface test points are arranged between the N column of solder surface test points and the N +1 column of solder surface test points in the test sub-network dot matrix, wherein the N-1 columns of solder surface test points are the N column of solder surface test points of the rest test sub-network dot matrix, and N is a positive integer greater than 0.
For example, as shown in fig. 2, assuming that there are 2 test sub-network lattices, and n is 1, 1 column of solder surface test points is spaced between a first column of solder surface test points and a second column of solder surface test points in one test sub-network lattice, and the column of solder surface test points is the first column of solder surface test points in another test sub-network lattice.
In the embodiment, the LED circuit board is divided into the plurality of sub-network testing lattices for testing, so that the testing density is reduced, and the testing yield is effectively improved.
In one embodiment, the nth column of the test sub-network lattice is adjacent to the (N + 1) th column of solder face test points, and the (N + 1) th column of the test sub-network lattice and the (N + 2) th column of the solder face test points are spaced by 2 x (N-1) columns of solder face test points, wherein the 2 x (N-1) columns of solder face test points are the nth column and the (N + 1) th column of solder face test points of the remaining test sub-network lattice, and N is a positive integer greater than 0.
For example, as shown in fig. 3, assuming that there are 2 test sub-network lattices, and n is 1, 2 rows of solder plane test points are spaced between a second row of solder plane test points and a third row of solder plane test points in one test sub-network lattice, where the 2 rows of solder plane test points are a first row of solder plane test points and a second row of solder plane test points in another test sub-network lattice.
In the embodiment, the LED circuit board is divided into the plurality of sub-network testing lattices for testing, so that the testing density is reduced, and the testing yield is effectively improved.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
It is to be understood that the above-described embodiments are merely illustrative of some, but not restrictive, of the broad invention, and that the appended drawings illustrate preferred embodiments of the invention and do not limit the scope of the invention. This application is capable of embodiments in many different forms and is provided for the purpose of enabling a thorough understanding of the disclosure of the application. Although the present application has been described in detail with reference to the foregoing embodiments, it will be apparent to one skilled in the art that the present application may be practiced without modification or with equivalents of some of the features described in the foregoing embodiments. All equivalent structures made by using the contents of the specification and the drawings of the present application are directly or indirectly applied to other related technical fields and are within the protection scope of the present application.
Claims (7)
1. A method for testing an LED circuit board is characterized by comprising the following steps:
splitting a soldering tin surface test lattice of the LED circuit board into N test sub-network lattices based on a preset region splitting mode, wherein each test sub-network lattice has the same circuit connection relation and has the same electric connection relation with a part surface test lattice of the LED circuit board, the soldering tin surface test lattice and the test sub-network lattices are determinant matrixes, the soldering tin surface test lattices correspond to LED pads on the LED circuit board one by one, the part surface test lattices correspond to component pads on the LED circuit board one by one, and N is a positive integer greater than 0;
setting M alignment optical points on each test sub-network lattice, wherein M is a positive integer greater than 0;
planting a test needle on a test fixture according to the part surface test dot matrix and the test sub-network dot matrix, wherein the test fixture is provided with CCD camera equipment;
when the LED circuit board is tested, the position of the alignment optical point is captured through the CCD camera shooting equipment;
and positioning the sub-network dot matrix according to the position of the alignment optical point, and sequentially testing the N sub-network dot matrixes by adopting a testing jig with testing needles.
2. The method for testing an LED circuit board according to claim 1, wherein the part surface test lattice comprises Y part surface test points, the number of the seed test pins is Y, the sub-network test lattice comprises X solder surface test points, the number of the seed test pins is Y/N, and X, Y is a positive integer greater than 0.
3. The method of claim 2, wherein the component plane test points are in electrical connection with the corresponding solder plane test points.
4. The LED circuit board testing method of any one of claims 1 to 3, wherein the N-1 columns of solder surface test points are spaced from the N +1 th column of solder surface test points in the test sub-network lattice, wherein the N-1 columns of solder surface test points are the N-1 th columns of solder surface test points in the remaining test sub-network lattice, and N is a positive integer greater than 0.
5. The method for testing an LED circuit board according to any one of claims 1 to 3, wherein the nth column of the test sub-network lattice is adjacent to the (N + 1) th column of solder face test points, and the (N + 1) th and the (N + 2) th columns of solder face test points are spaced by 2 (N-1) columns of solder face test points, wherein the 2 (N-1) columns of solder face test points are the nth and the (N + 1) th columns of solder face test points of the remaining test sub-network lattice, wherein N is a positive integer greater than 0.
6. The method for testing the LED circuit board according to claim 1, wherein the step of sequentially testing the N sub-network lattices by using the testing jig with the testing pins comprises the steps of:
the testing jig is installed on a testing machine, wherein the testing jig comprises an upper die and a lower die, the upper die is used for planting testing needles corresponding to the testing sub-network dot matrix, the lower die is used for planting testing needles corresponding to the part surface testing dot matrix, the testing machine comprises an upper table surface and a lower table surface, the lower film is installed on the lower table surface, the upper die is installed on the upper table surface, and the upper table surface has a displacement testing function;
arranging the LED circuit board between the lower die and the upper die through a clamping jaw mechanism, wherein the testing sub-network lattice is contacted with the upper die, and the part surface testing lattice is contacted with the lower die;
when the LED circuit board is tested, the sub-network dot matrixes are sequentially tested by moving the upper table top, and the lower table top is kept still.
7. The method for testing the LED circuit board according to claim 6, wherein the sequentially testing the sub-network lattices by moving the upper table comprises:
after one of the N test sub-network lattices is tested, the upper table top automatically moves to the next positioned test sub-network lattice to test until the test of the N test sub-network lattices is completed in sequence.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111044722.3A CN113721132A (en) | 2021-09-07 | 2021-09-07 | LED circuit board testing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111044722.3A CN113721132A (en) | 2021-09-07 | 2021-09-07 | LED circuit board testing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113721132A true CN113721132A (en) | 2021-11-30 |
Family
ID=78682335
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111044722.3A Pending CN113721132A (en) | 2021-09-07 | 2021-09-07 | LED circuit board testing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113721132A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1111357A (en) * | 1994-01-06 | 1995-11-08 | 国际商业机器公司 | Printed circuit board test fixture and method |
| CN105866655A (en) * | 2015-01-23 | 2016-08-17 | 大族激光科技产业集团股份有限公司 | PCB test fixture with alignment detection mechanism |
| CN209342866U (en) * | 2018-12-06 | 2019-09-03 | 瑞统科技股份有限公司 | Circuit board testing device |
| CN110736911A (en) * | 2018-07-18 | 2020-01-31 | 大族激光科技产业集团股份有限公司 | Flying probe testing method, flying probe testing device, flying probe testing apparatus, and storage medium |
| CN210720649U (en) * | 2019-08-30 | 2020-06-09 | 广东派捷智能装备有限公司 | PCBA board test equipment |
-
2021
- 2021-09-07 CN CN202111044722.3A patent/CN113721132A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1111357A (en) * | 1994-01-06 | 1995-11-08 | 国际商业机器公司 | Printed circuit board test fixture and method |
| CN105866655A (en) * | 2015-01-23 | 2016-08-17 | 大族激光科技产业集团股份有限公司 | PCB test fixture with alignment detection mechanism |
| CN110736911A (en) * | 2018-07-18 | 2020-01-31 | 大族激光科技产业集团股份有限公司 | Flying probe testing method, flying probe testing device, flying probe testing apparatus, and storage medium |
| CN209342866U (en) * | 2018-12-06 | 2019-09-03 | 瑞统科技股份有限公司 | Circuit board testing device |
| CN210720649U (en) * | 2019-08-30 | 2020-06-09 | 广东派捷智能装备有限公司 | PCBA board test equipment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101889338B (en) | Method for wafer test and probe card for the same | |
| EP0791833B1 (en) | Device for converting the test point grid of a machine for electrically testing unassembled printed circuit boards | |
| US4567433A (en) | Complex probe card for testing a semiconductor wafer | |
| CA1167976A (en) | Circuit board having encapsulatd wiring on component side | |
| WO2006060485A1 (en) | Methods for assembling a stack package for high density integrated circuits | |
| US20070035318A1 (en) | Donut-type parallel probe card and method of testing semiconductor wafer using same | |
| US20200141974A1 (en) | Systems and Methods for Depopulating Pins from Contactor Test Sockets for Packaged Semiconductor Devices | |
| KR20050106581A (en) | Structure of flip chip semiconductor package for testing a bump and method of fabricating the same | |
| CN113721132A (en) | LED circuit board testing method | |
| CN212625492U (en) | LED chip detection device | |
| US3753046A (en) | Multi-layer printed circuit board | |
| KR100674938B1 (en) | Probe card for testing multi-chips | |
| US6642727B1 (en) | Chip carrier device and method for the production of a chip carrier device with an electrical test | |
| US6864697B1 (en) | Flip-over alignment station for probe needle adjustment | |
| KR102273832B1 (en) | Manufacturing method of middle platform device for testing of led chips before transferring process of led chips into display pannel | |
| KR100798724B1 (en) | Method for wafer test and probe card for the same | |
| CN114755556A (en) | Multi-station high-speed testing device and method | |
| US5455518A (en) | Test apparatus for integrated circuit die | |
| US20040124507A1 (en) | Contact structure and production method thereof | |
| CN116609897B (en) | Mixed packaging structure of large-scale optical switching chip and verification method | |
| KR101946450B1 (en) | Interface board of a testing head for a test equipment of electronic devices and corresponding testing head | |
| KR20190109130A (en) | Method for arraying micro LED chips for manufacturing a LED display. | |
| CN118119100B (en) | Method for detecting copper exposure of circuit board solder mask | |
| CN113985252B (en) | Lamp panel jig regional testing method | |
| US7411295B2 (en) | Circuit board, device mounting structure, device mounting method, and electronic apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |