CN113709604A

CN113709604A - Rapid reconfigurable non-blocking full-connection router based on annular turntable bus architecture

Info

Publication number: CN113709604A
Application number: CN202110748597.8A
Authority: CN
Inventors: 范柱平; 何建军
Original assignee: Zhejiang University ZJU
Current assignee: Zhejiang University ZJU
Priority date: 2021-07-02
Filing date: 2021-07-02
Publication date: 2021-11-26
Anticipated expiration: 2041-07-02
Also published as: CN113709604B

Abstract

The invention discloses a reconfigurable non-blocking full-connection router based on a ring turntable bus architecture. The input/output ports are connected through a ring-shaped turntable bus architecture; the annular turntable bus architecture is provided with N-1 annular buses, and the ith annular bus is distributed with N +1-i basic switching units; the input end of the basic switching unit on the outermost ring bus is connected with the input port I, the output end of a basic switching unit on the ith ring bus is connected with the output port O, and the output ends of the other basic switching units are respectively connected with the input end of each basic switching unit on the (I + 1) th ring bus through the bent waveguide. The invention utilizes the ring turntable bus architecture to obtain the reconfigurable non-blocking fully-connected network among the layers in the vertical direction, and the network has N! The non-blocking replacement realizes the rapid reconfigurable cross connection among the multiple layers of passive waveguides by only one layer of active waveguide, and has the advantages of simple topological structure, low loss, expandability, high-speed reconfiguration and the like.

Description

Rapid reconfigurable non-blocking full-connection router based on annular turntable bus architecture

Technical Field

The invention relates to a fully connected router in the field of optical interconnection communication, in particular to a fast reconfigurable non-blocking fully connected router network based on an NxN novel annular turntable bus architecture.

Background

With the push of internet/internet of things technology and fifth generation mobile communication technology, the explosive growth of communication data will bring great challenges to information technology: the data exchange routing throughput between CPU/storage in communication networks, data centers and high performance computers will be up to the Tb/s or even Pb/s level. With the continuous improvement of the integration level, the processing rate of a large-scale integrated circuit chip on a unit area is greatly improved. However, further improvements in the data transfer switching throughput of electronic chips have met with bottlenecks due to crosstalk, heat generation, quantum effects, etc. resulting from dense integration. The silicon photonics technology combines photonics and CMOS technology, and is a main technical means for solving the electronic bottleneck problem.

Furthermore, limited by the optical diffraction limit, the size of optical devices is typically much larger than the device size (nanometer scale) of current large scale integrated circuits, so that the integration of optical devices cannot be matched to electrical chips, typically using separate chips and processes. In recent years, the integration level of microelectronic chips is improved by three-dimensional integrated circuit technology based on the TSV through hole technology. Correspondingly, three-dimensional integrated optical chips based on photonic technology are also beginning to get the attention of researchers. By increasing the integration space of one dimension (vertical direction), the device integration level can be greatly improved. A full-interactive on-chip optical network route which is more than 100,000 nodes and based on an array waveguide grating route is provided in the Journal of High-density wafer-scale 3-D silicon-photonic integrated circuits [ J ]. IEEE Journal of Selected topocs in Quantum Electronics,2018,24(6):1-10 ", of Davis university, California, and the photonic data exchange of 1.6Tb/s can be processed. 3D photonic integration can be achieved by femtosecond laser direct writing technology, and can also be based on vertical coupling (heterojunction) between the silicon layer and the silicon nitride waveguide layer. The university of Toronto, Canada proposed a three-layer silicon nitride-silicon dioxide heterojunction structure to achieve vertical interlayer light crossover, reported in "Tri-layer silicon nitride-on-silicon photonic platform for ultra-low-loss cross-correlations" Optics Express,2017,25(25): 30862) 30875. These studies are still in the initiative for three-dimensional photonic integration.

In three-dimensional photonics, there is currently no layer based on high-speed optical switchingInter-dynamic optical crossing. In order to realize flexible networking, a traditional two-dimensional photonic integrated chip generally adopts two-dimensional planar waveguide structures such as a micro-ring array, a mach zehnder interferometer array (MZI), an Arrayed Waveguide Grating (AWG) and the like to realize cross routing. Common fully-connected optical cross-routing based on optical switch arrays includes: crossbar type, Clos type and Benes type, etc. Wherein the Benes network is a special case of a 2 x 2 switching fabric for all switching elements in a Clos network. The Crossbar optical cross-connect network is a completely non-blocking network, has simple expansion and control and does not need a complex routing algorithm. The disadvantage is that the required optical switch is N²The overhead is large. The Benes type exchange network is a reconfigurable non-blocking multilevel interconnection network, which is the network with the least number of switches used in the realization of non-blocking optical cross connection at present, and the disadvantage is that the scale N of the network can only be 2^m(m is a natural number), and the addressing control system is complicated. Moreover, the optical cross full-connection topological structure realized based on the two-dimensional planar waveguide structure cannot be directly applied to three-dimensional photonic integration, and cannot realize dynamic reconfigurable cross connection of less than 10 nanoseconds (high-speed optical switch).

Disclosure of Invention

In order to overcome the defects of the background art, the invention provides a quick reconfigurable non-blocking full-connection router based on a ring turntable bus architecture. The three-dimensional photon routing device can be matched with a high-speed high-capacity optical network, and full-connection network interconnection of any NxN port in multilayer passive waveguides based on a heterostructure is achieved.

The technical scheme adopted by the invention is as follows:

as shown in fig. 8, the router structure includes N input ports I and N output ports O, where N is a natural number greater than 1, and N input ports I are I respectively₁,I₂,……,I_NN output ports O are respectively O₁，O₂,……,O_N(ii) a The input port and the output port are connected through a ring-shaped turntable bus architecture consisting of a plurality of same basic switching units;

the annular turntable bus architecture comprises N-1 annular buses, wherein the serial number of each annular bus from outside to inside is i, i is 1,2, … …, N-1, and N +1-i basic switching units are distributed on the ith annular bus.

The input end of each basic switching unit on the outermost ring bus is respectively connected with N input ports I, and the output end of only one basic switching unit on the ith ring bus and one output port O which is uniquely corresponding to the basic switching unit on the ith ring bus from the outer side to the inner side_iThe output ends of other basic switching units on the ith ring bus are respectively correspondingly connected with the input ends of the basic switching units on the (i + 1) th ring bus positioned at the adjacent inner side of the ith ring bus one by one through the bent waveguides and are transmitted to the active layer waveguide through the bent waveguides, and the arrangement and the connection are arranged to cover the N-1 ring buses which are suitable for being used from the outermost side to the innermost side until the output ends of the two basic switching units of the (N-1) th ring bus at the innermost side are respectively connected with the output port O_N-1，O_NAnd (4) connecting.

The basic switching units connected in series on the ring buses from the outer side to the inner side through the bent waveguides jointly form a group of transmission lines from the input port I to the output port O, j is numbered inwards from the basic switching units on the outermost ring bus, j is 1,2, … … and N, and the basic switching unit is numbered MZ_ij，MZ_ijA basic switching element representing the jth transmission line on the ith ring bus.

In the specific implementation, the numbers j, j being 1,2, … …, N of each group of transmission lines are numbered according to the sequence of input ports or output ports, that is, the transmission lines and the input ports I and the output ports O where the transmission lines are located have the same numbers in a one-to-one correspondence, and the number of the corresponding basic switching unit is MZ_ij，MZ_ijShowing the jth basic switch unit on the ith ring bus.

The optical signals on the single ring buses of the transmission lines are transmitted to the connected inner side or outer side ring buses through the basic switching units on the ring buses in a crossed mode.

The N input ports I and the N output ports O are respectively arranged in the N passive layer waveguides, namely the jth input port I and the jth output port O are both positioned in the jth passive layer waveguide, and the adjacent passive layer waveguides are coupled through interlayer S-bend coupling to realize interlayer waveguide coupling.

The basic switching units on each ring bus share the active layer waveguide, namely share one active layer waveguide, and the active layer waveguide is ring-shaped. So that the present invention has only one active layer waveguide and N passive layer waveguides.

The basic exchange unit adopts an in-layer Mach-Zehnder optical switch designed based on a two-dimensional photonic integrated platform or a vertical direction interlayer Mach-Zehnder (MZI) optical switch designed for a three-dimensional photonic integrated platform.

The existing switching fabric is shown in fig. 2, and includes a first input port, a second input port, a first output port, a second output port, a first layer inner coupler, a second layer inner coupler, a reference arm and a tuning arm, which are located in the same waveguide layer; the first input port and the second input port are respectively connected to two input ends of the first-layer inner coupler, two output ends of the first-layer inner coupler are respectively connected to one ends of a reference arm and one end of a tuning arm, the reference arm and the tuning arm are arranged in a coupling mode, the other ends of the reference arm and the tuning arm are respectively connected to two input ends of the second-layer inner coupler, and two output ends of the second-layer inner coupler are respectively connected with the first output port and the second output port.

The specific implementation adopts a Mach-Zehnder optical switch between layers in the vertical direction. The passive waveguide positioned on the first layer is used as a reference arm, the active silicon waveguide positioned on the SOI layer is used as a switch arm, and the high-speed regulation and control are carried out by utilizing an electrogenerated refractive index change mechanism formed by injecting free carriers of the silicon-based PIN junction. As shown in fig. 3, the present invention changes the existing switch fabric, and the basic switch unit includes a first input port, a second input port, a first output port, a second output port, a reference arm, and a tuning arm, which are located in different waveguide layers (301, 302), wherein the second input port, the reference arm, and the second output port are located in the upper waveguide layer, and the first input port, the tuning arm, and the first output port are located in the lower waveguide layer; the first input port and the second input port are respectively connected to two input ends of a first interlayer coupler, two output ends of the first interlayer coupler are respectively connected to one ends of a reference arm and a tuning arm, the reference arm and the tuning arm are arranged in a coupling mode, the other ends of the reference arm and the tuning arm are respectively connected to two input ends of a second interlayer coupler, and two output ends of the second interlayer coupler are respectively connected with a first output port and a second output port; the first and second interlayer couplers are each disposed vertically across the upper and lower waveguide layers.

The upper waveguide layer and the lower waveguide layer are made of different materials. The upper waveguide layer is made of low-loss passive materials, such as silicon oxide and silicon nitride; the lower waveguide layer is made of active material with high-speed carrier response and is an active layer, such as silicon. The basic switching units on each ring bus share a lower waveguide layer, namely the lower waveguide layers are the same, a ring active layer waveguide is arranged on the lower waveguide layer, and a first input port, a reference arm and a first output port in each basic switching unit on each ring bus are all positioned on the ring active layer waveguide. The ring bus is arranged in the active layer silicon waveguide layer, the passive waveguide positioned in the upper waveguide layer is used as a reference arm, the active waveguide positioned in the lower waveguide layer is used as a tuning arm, and high-speed regulation and control can be performed by utilizing an electro-induced refractive index change mechanism formed by free carrier injection of a silicon-based PIN junction. Not only provides high speed electro-optic response, but also the larger refractive index difference makes it have lower bending loss, making the device more compact.

Aiming at the three-dimensional integrated photonic platform, N upper waveguide layers are arranged above the lower waveguide layer, the upper waveguide layers are all passive layer waveguides, and interlayer waveguide coupling is realized between the upper waveguide layers through interlayer low-loss S-bend coupling, as shown in figure 4; the N input ports I and the N output ports O are respectively arranged in the N upper waveguide layers, and the jth input port I and the jth output port O are positioned in the N input ports I and the N output ports O. J th input port I_jAnd the jth output port O_jAll located on the same passive layer waveguide.

The interlayer coupler is a directional coupler. According to the coupling mode theory and the grating auxiliary phase matching principle, a simulation model is established, the distance between the upper waveguide layer and the lower waveguide layer, the grating period and the duty ratio are optimized, and 50% is realized in an extremely short distance: 50 power allocation.

The invention realizes N!from any N inputs to any N outputs among the multilayer passive waveguides by the structure! Full connection non-blocking replacement is adopted.

The annular turntable bus structure can be integrated on the same chip through a two-dimensional or three-dimensional photonic integration technology.

In the embodiments of the present invention, the passive layer is a silicon nitride (SIN) platform, and the active layer is an SOI platform. In the passive SIN interlayer waveguide coupling aspect, according to the bending resistance characteristic of a high-refractive-index-difference silicon nitride waveguide and the conformal smooth deposition characteristic of a dielectric film, as shown in FIG. 4, an ultra-small interlayer low-loss S-bend coupling connection is realized by adopting a slope etching and multilayer deposition etching method, and an upper layer passive waveguide (a 2 nd-N layer passive waveguide) and a middle layer passive waveguide (a 1 st layer passive waveguide) are coupled and connected to a bottom layer passive waveguide (a 1 st layer passive waveguide) to serve as corresponding input waveguides I.

The input waveguide I from different passive SIN waveguide layers realizes the cross transmission of the passive SIN layer and the active Si waveguide layer of the ring bus through a 2 x 2 heterogeneous MZI high-speed optical switch on the ring turntable bus, realizes the fast reconfigurable optical cross to the output waveguide O through the ring turntable bus, and then connects back to the corresponding passive waveguide layer through the vertical S-bend coupling, thereby realizing the N!from any N input to any N output among the multilayer passive waveguides! And (4) full connection replacement.

The invention utilizes the heterostructure to obtain the method for realizing the reconfigurable non-blocking full-connection network between the layers in the vertical direction, can efficiently realize the quick reconfigurable cross connection between the multilayer passive waveguides by only using a single active switch layer, and can realize the N!from any N inputs to any N outputs! The non-blocking replacement has the advantages of simple topological structure, low loss, expandability, high-speed reconfiguration and the like.

The rapid reconfigurable non-blocking fully-connected router based on the annular turntable bus architecture can be integrated on the same chip through a two-dimensional or three-dimensional photonic integration technology.

Compared with the background technology, the invention has the following beneficial effects:

1. the invention has simple topological structure, the required switch number is between Crossbar type and Benes type networks, and the invention has clear construction rule.

2. The network is constructed as a reconfigurable non-blocking network, is expandable, and can realize the N!from any N inputs to any N outputs! Non-blocking replacement. The network size N may be any natural number equal to or greater than 2.

3. The switch unit can be designed in a layered mode in the vertical direction, and is suitable for vertical direction interlayer quick reconfigurable optical cross connection obtained based on a heterostructure. A feasible scheme is provided for meeting the requirements of optical cross full connection of the three-dimensional integrated optical chip.

4. The tuning arm of the vertical MZI switch can be independently designed in an active silicon layer (or other active layers), high-speed regulation and control are carried out by utilizing an electrogenerated refractive index change mechanism formed by injecting free carriers of a silicon-based PIN junction, the switching speed of the switch is improved, and high-speed reconfigurable optical cross routing is realized.

5. The active layer and the passive layer are designed in a layered mode, only one layer of ring bus active waveguide layer is used for assisting in completing optical switching, and the complexity of the process can be reduced. And the optical signal is transmitted in a back-and-forth crossing manner between the active waveguide and the passive waveguide, so that the high-speed optical exchange is ensured, the integral loss of the device can be effectively reduced, and the transmission quality of the optical signal is improved.

Description of the drawings:

FIG. 1 is a schematic diagram of optical signal transmission of a Mach-Zehnder optical switch with tuning arm phases of π and 0;

FIG. 2 is a schematic diagram of a Mach-Zehnder optical switch based on a two-dimensional photonic integrated platform design;

FIG. 3 is a schematic diagram of a vertical inter-layer Mach-Zehnder optical switch for three-dimensional photonic integrated platform design;

FIG. 4 is a schematic diagram of a passive interlayer coupling structure of lower waveguide layers of different basic switching units;

FIG. 5 is a 2 × 2 port heterogeneous integrated optical cross-over single ring architecture based on a ring bus architecture;

FIG. 6 is a 3 × 3 port heterogeneous integrated optical cross-over single ring architecture based on a ring bus architecture;

FIG. 7 is a 3 × 3 port heterogeneous integrated optical cross full connection non-blocking dual ring architecture based on a ring carousel bus architecture;

FIG. 8 is a schematic diagram of a 3 × 3 port fast reconfigurable non-blocking fully connected router based on a ring carousel bus architecture according to the present invention;

FIG. 9 is a schematic diagram of a 4 × 4 port fast reconfigurable non-blocking fully connected router based on a ring carousel bus architecture according to the present invention;

fig. 10 is a flow chart of the process of establishing the routing table according to the present invention.

Fig. 11A and 11B show a full-connection replacement routing table according to embodiment 2 of the present invention.

In the figure: a second input port 201, a first input port 202, a first output port 204, a second output port 203; an upper waveguide layer 301, a lower waveguide layer 302, a reference arm 303, a tuning arm 304, a first in-layer coupler 305, a second in-layer coupler 306, a first inter-layer coupler 307, a second inter-layer coupler 308, an outer ring bus OR, an inner ring bus IR.

The specific implementation mode is as follows:

the invention is further illustrated by the following figures and examples.

The fast reconfigurable non-blocking fully connected router embodied by the present invention is based on a ring carousel bus architecture design, which includes I, N output ports O of N input ports, (N +2) x (N-1)/2 x 2 basic switching elements 001, N-1 ring buses. N is a natural number greater than 1, and N input ports I are I respectively₁,I₂,……,I_NN output ports O are respectively O₁，O₂,……,O_N(ii) a The input port and the output port are connected through a ring turntable bus architecture consisting of a plurality of same basic switching units (001); the basic switching element is a mach-zehnder optical switch MZ of 2 x 2. Wherein N is any natural number more than or equal to 2.

The ring turntable bus architecture comprises N-1 ring buses, wherein the ring buses are numbered from outside to inside, i is 1,2, … … and N-1, and N +1-i basic switching units are distributed on the ith ring bus;

the input end of each basic switching unit on the outermost ring bus is respectively connected with N input ports I, and the output end of only one basic switching unit on the ith ring bus and one output port O which is uniquely corresponding to the basic switching unit on the ith ring bus from the outer side to the inner side_iThe output ends of other basic switching units on the ith ring bus are respectively correspondingly connected with the input ends of the basic switching units on the (i + 1) th ring bus adjacent to the ith ring bus one by one through bent waveguides until the output ends of the two basic switching units of the (N-1) th ring bus at the innermost side are respectively connected with the output port O_N-1，O_NAnd (4) connecting.

The ring buses from the outer side to the inner side are connected in series through the bent waveguides and the basic switching units connected with the bent waveguides to form a group of transmission lines from the input port I to the output port O, and the transmission lines of the group are numbered according to the sequence of the input port or the output port, wherein j is 1,2, … …, N, namely the input port I, the output port O and the transmission lines have the same number in a one-to-one correspondence mode. The corresponding basic switching unit is numbered MZ_ij，MZ_ijShowing the jth basic switch unit on the ith ring bus.

Fig. 1 is a schematic diagram of optical signal transmission of the mach-zehnder optical switch when the phase of tuning arm 304 is pi and 0. By controlling the phase of tuning arm 304, the mach-zehnder optical switch may achieve two states: "straight-through" and "cross". The binary code "0" or "1" is used to represent the phase of the tuning arm is pi, and the optical switch is in the through state; a "1" indicates that the phase of the tuning arm is 0, indicating that the optical switch is in the crossed state. By the regulation and control of the two-way system, the addressing route control can be realized more conveniently.

The invention provides a Mach-Zehnder optical switch which comprises an intra-layer Mach-Zehnder optical switch (shown in figure 2) designed based on a two-dimensional photonic integration platform and a vertical direction interlayer Mach-Zehnder optical switch (shown in figure 3) designed for a three-dimensional photonic integration platform.

As shown in fig. 2, the structure includes a first input port 202, a second input port 201, a first output port 204, a second output port 203, a first layer inner coupler 305, a second layer inner coupler 306, a reference arm 303, and a tuning arm 304 located within the same waveguide layer 301; the first input port 202 and the second input port 201 are respectively connected to two input ends of a first-layer inner coupler 305, two output ends of the first-layer inner coupler 305 are respectively connected to one ends of a reference arm 303 and a tuning arm 304, the other ends of the reference arm 303 and the tuning arm 304 are respectively connected to two input ends of a second-layer inner coupler 306, and two output ends of the second-layer inner coupler 306 are respectively connected with a first output port 204 and a second output port 203; all structures are designed in the same layer 301 using the same waveguide material. Such as silicon, silicon dioxide, silicon nitride materials, and the like. The first-layer inner coupler 305 and the second-layer inner coupler 306 can realize a splitting ratio of 3dB by using a conventional structure such as a directional coupler or a multimode waveguide.

FIG. 3 shows a schematic diagram of a vertical inter-layer Mach-Zehnder optical switch for a three-dimensional photonic integrated platform design. The vertical-direction interlayer mach-zehnder optical switch, namely a 2 × 2 heterogeneous MZI high-speed optical switch, includes a first input port 202, a second input port 201, a first output port 204, a second output port 203, a reference arm 303 and a tuning arm 304 which are located in different waveguide layers 301 and 302, wherein the second input port 201, the reference arm 303 and the second output port 203 are located in the upper waveguide layer 301, and the first input port 202, the tuning arm 304 and the first output port 204 are located in the lower waveguide layer 302; the first input port 202 and the second input port 201 are respectively connected to two input ends of a first interlayer coupler 307, two output ends of the first interlayer coupler 307 are respectively connected to one ends of a reference arm 303 and a tuning arm 304, the other ends of the reference arm 303 and the tuning arm 304 are respectively connected to two input ends of a second interlayer coupler 308, and two output ends of the second interlayer coupler 308 are respectively connected with a first output port 204 and a second output port 203; the first interlayer coupler 307 and the second interlayer coupler 308 are each arranged vertically across the upper waveguide layer 301 and the lower waveguide layer 302.

The upper waveguide layer 301 and the lower waveguide layer 302 are made of different materials. The upper waveguide layer 301 is made of passive materials such as silicon oxide and silicon nitride; the lower waveguide layer 302 is formed of an active material such as silicon.

The basic switching units on each ring bus share the active layer waveguide, and the active layer waveguide is a ring waveguide, namely, is used as a ring bus. The passive waveguide positioned in the upper waveguide layer 301 is used as a reference arm, and the active waveguide positioned in the lower waveguide layer 302 is used as a tuning arm, for example, the high-speed regulation and control can be performed by utilizing an electric refractive index change mechanism formed by the injection of free carriers of a silicon-based PIN junction. Not only provides a high speed electro-optic response, but the large index difference results in low bending losses.

The first interlayer coupler 307 and the second interlayer coupler 308 are directional couplers, and according to a coupling mode theory and a grating auxiliary phase matching principle, a simulation model is established, the distance between the upper waveguide layer 301 and the lower waveguide layer 302, the grating period and the duty ratio are optimized, and 50 is realized in an extremely short distance (for example, the SIN-SI waveguide can be less than 10 um): 50 power allocation.

The invention realizes N!from any N inputs to any N outputs among the multilayer passive waveguides by the structure! And (4) full connection replacement.

The reconfigurable non-blocking fully-connected router based on the annular turntable bus architecture can be integrated on the same chip through a two-dimensional or three-dimensional photonic integration technology.

Fig. 4 shows a schematic diagram of a passive interlayer coupling structure. The three-dimensional photonic integrated platform often has a plurality of layers of passive waveguide layers, in order to realize passive interlayer coupling connection, according to the bending resistance characteristic of a high-refractive-index-difference passive waveguide (such as a silicon nitride waveguide) and the conformal smooth deposition characteristic of a dielectric film, a slope etching and multilayer deposition etching method is adopted to realize ultra-small-size interlayer low-loss S-bend coupling connection, an upper layer passive waveguide (a 2 nd-N layer passive waveguide) and a middle layer passive waveguide (a 1 st layer passive waveguide) are coupled and connected to a bottom layer passive waveguide (a 1 st layer passive waveguide), the 1 st layer passive waveguide and a 0 th layer active waveguide realize rapid reconfigurable optical cross under an annular turntable bus architecture formed by vertical direction interlayer Mach-Zehnder optical switches, and cross output optical signals are coupled and connected to corresponding passive layers through the same S-bend structure.

Fig. 5 shows a 2 × 2 port heterogeneous integrated optical cross-connect single-ring architecture based on a ring bus architecture, that is, an optical cross-connect between 2 layers of passive waveguides is realized, which is a specific example N ═ 2 under the architecture system of the present invention, there are only 1 ring bus in the active layer waveguides, and two 2 × 2 heterogeneous MZI high-speed optical switches MZ are arranged₁₁、 MZ₁₂. When the optical signals from the 1 st and 2 nd passive layer waveguides need to be output in a crossed manner, the optical signal of the 2 nd passive layer waveguide is firstly coupled to the input port I of the 1 st passive layer waveguide through S-bend coupling₂Then separately MZ₁₁、MZ₁₂State "1", i.e. the cross state, is set. Input port I from original 1 st passive layer waveguide₁Passes through the MZ connected thereto₁₁Cross into the ring bus and transmit to MZ via the ring bus₁₂Then, again from MZ₁₂Cross slave output port O₂Outputting; similarly, input port I from the 2 nd passive layer waveguide₂From the output port O₁The cross output of (c). From the output port O₂The output optical signals are connected back to the corresponding 2 nd passive layer waveguide through S-bend coupling. Because the tuning arm of the vertical M-ray Z switch is independently designed on the active silicon layer (or other active layers), the change mechanism of the electric induced refractive index formed by injecting free carriers of the silicon-based PIN junction is utilized to carry out high-speed regulation and control, and the switching speed of the switch is improved.

The following default multilayer passive waveguides are connected to the layer 1 passive waveguide through S-bend coupling before optical crossing, and are connected back to the corresponding passive waveguide through S-bend coupling after optical crossing is achieved. Aiming at passive interlayer coupling, not much description is provided, and how the layer 1 passive waveguide and the layer 0 active waveguide realize rapid reconfigurable optical crossing under a ring turntable bus architecture is mainly discussed.

When the network is extended to N-3, if there are still only 1 ring bus, as shown in fig. 6, the architecture can only complete a partial non-blocking permutation, for example I₂-O₁,I₃-O₂,I₁-O₃The permutation of (a) cannot be realized.

So to complete 3! One method is to add an inner ring bus IR directly to the full-link permutation (6), and to add an inner ring bus IR to a 2 × 2 MZI high-speed optical switch MZ₁₁、MZ₁₂、MZ ₁₃3 groups of Mach-Zehnder optical switches LMZ are added between every two optical switches₂₁、LMZ₂₂、LMZ₂₃The three groups of intra-layer mach-zehnder optical switches are all in the 0 th layer active waveguide, and optical intersection between the outer annular bus OR and the inner annular bus IR is realized, as shown in fig. 7. Active layer internal optical switch LMZ₂₁、LMZ₂₂、LMZ₂₃When the state "0" is set, i.e., the pass-through state, the design is simplified to a single-loop architecture as shown in fig. 6. When all switches are set to the cross state '1', I can be completed₂-O₁,I₃-O₂,I₁-O₃Replacement of (2). However, this design increases the number of switches, which in principle is N x (N-1), and is less advantageous for further expansion.

In order to further reduce the number of switches and improve the practicability of a full-connection network based on a ring-shaped bus architecture, the invention provides a quick reconfigurable non-blocking router based on a ring-shaped turntable bus architecture.

For convenience of explaining the full-connection routing mechanism of the present invention and simplifying the addressing routing control algorithm, the present invention makes the following calibration on the output port number, as shown in fig. 8-9. When j is<When is equal to N-2, wherein N>J denotes the number of the output port, output port O_jAnd a 2 x 2 heterogeneous MZI high-speed optical switch MZ on the jth ring bus_j1To the first output port 204; when j is N-1, N, the output port O_N-1、O_NRespectively connected with MZ on inner ring bus IR_(N-1)1、MZ_(N-1)2The first output port 204 is connected. By such scaling, the routing can be addressed according to O₁，O₂,……,O_NIs addressed step by step.

Fig. 10 is a flow chart of the process of establishing the routing table according to the present invention. Where i denotes the number of ring buses (from the outer ring bus OR to the inner ring bus IR), j denotes the number of output ports, and k denotes the position of the routing table. Routing Table A, article of manufacture, of the inventionPhysical meaning means that a slave I is established_A(k)To O_kI.e. a (k) is the source address, corresponding to the number of the input port, k is the destination address, corresponding to the number of the output port.

The routing table is established in such a way that the output port is from O to the inner ring bus IR from the outer ring bus OR₁To O_NThe principle of sequential addressing stage by stage.

The first step is as follows: all optical switches are set to state "0", corresponding to I₁-O₁,I₂-O₂,......,I_j-O_j,......,I_N-O_NI.e. initializing the routing

table R ═

1,2, …, N]。

To complete a specific routing a, it is necessary to sequentially discriminate from the outer ring bus OR to the inner ring bus IR, and reset the corresponding optical switch.

The second step is that: for the ith ring bus i<N-1, only the optical signal I on the transmission line k needs to be judged_R(k)Whether it meets the output port O_jThe desired source address (i.e., a (j) ═ r (k). If yes, directly jumping to the next step; if not, sequentially making k equal to i +1, … and N-i +1, continuously traversing other transmission lines k, judging until the k is equal to the k, and connecting the ith ring bus with the optical switch MZ of the transmission line j, k_ij, MZ_ikIs set to "1".

The third step: and updating the routing table. Signal I in transmission line k_R(k)From the output port O_jAnd outputting R (j) R (k), and updating the signal on the transmission line j to the transmission line k, namely updating the source address R (k) R (j) on the transmission line k.

The fourth step: addressing the source address of the next output port j ═ j +1, configuring the optical switch state of i ═ i +1 on the next ring bus, and making k ═ j.

The second to fourth steps are then repeated, and sequential addressing is performed step by step until the state of the optical switch on the inner ring bus IR is configured (i ═ N-1), that is, all connections are established.

The following describes the routing network topology provided by the embodiment of the present invention in detail.

Example 1:

as shown in fig. 8, when N is 3, the reconfigurable non-blocking fully-connected router based on the ring-type rotating disk bus architecture is formed by interconnecting 3 input/output ports, 5 2 × 2 heterogeneous MZI high-speed optical switches, 2 ring buses and 3 transmission lines.

Input/output port I₁/O₁，I₂/O₂And I₃/O₃Connected to

transmission lines

101, 102, 103, respectively, to which are connected the first output port 204, the reference arm 303 and the first input port 202 of the 2 x 2 hetero MZI high speed optical switch. The ring bus is connected with the second output port 203, the tuning arm 304 and the second input port 201 of the 2 × 2 heterogeneous MZI high-speed optical switch, all the input ports are distributed on the outer ring bus OR, I₁、I₂、I₃Arranged clockwise in the direction of light propagation. Output port O₁Distributed on the outer ring bus OR, connected with 2 × 2 heterogeneous MZI high-speed optical switch numbers MZ₁₁The other 2 multiplied by 2 heterogeneous MZI high-speed optical switches on the ring bus are numbered clockwise in sequence₁₂，MZ₁₃. Output port O₂，O₃Distributed on the inner ring bus IR, and connected 2 × 2 heterogeneous MZI high-speed optical switches are numbered as MZ in sequence₂₁，MZ₂₂。

Random establishment of I₁-O₃，I₂-O₁，I₃-O₂A routing table a ═ 2,3,1 of the set of connections of (a)]The configuration process of the 2 × 2 heterogeneous MZI high-speed optical switch of the reconfigurable non-blocking fully-connected router with 3 × 3 ports based on the ring turntable bus architecture proposed by the present invention is explained with reference to the flowchart of FIG. 10.

The first step is as follows: all 2 × 2 heterogeneous MZI high-speed optical switches are set to be 0, namely the through state. From input port I₁，I₂，I₃，I₄On the

transmission lines

101, 102, 103, respectively, the routing table R is initialized to [1,2,3 ═ 1,2,3]。

The second step is that: determining output port O on the 1 st ring bus (i.e., outside ring bus OR)₁Wherein i is 1, j is 1, k is j, i represents a ringThe number of the bus (from the outer ring bus OR to the inner ring bus IR), j denotes the number of the output port, and k denotes the position of the routing table. If the output port O₁Is from I₁(that is, a (1) ═ 1), the state of the 2 × 2 heterogeneous MZI high-speed optical switch on the outer ring bus is unchanged, no optical switching occurs on the outer ring bus, and the next step is skipped; otherwise, successively changing k to k +1, and continuously searching and judging the output port O₁Source address of (I)_kSuch that a (1) ═ r (k). In this example, when k is 2, a (1) is R (2), i.e., the output port O₁The output source address of is input port I₂And I is₂On the transmission line 102(k is 2), MZ connecting the outer ring bus OR with the transmission lines 101(j is 1), 102(k is 2)₁₁、MZ₁₂The optical switch is set to '1' and in a crossed state. At this time, the slave input port I₂The input optical signal passes through MZ₁₂Cross-input to the outer ring bus OR and then through MZ₁₃A second output port is directly output to the MZ₁₁Due to MZ₁₁In a crossed state, and is thus input to the MZ₁₁The optical signal of the second input port is crossly output to MZ₁₁First output port to output port O₁. Similarly, from input port I₁To the MZ₁₂Into the transmission line 102(k 2).

The third step: and updating the routing table. To this end, input port I is completed₂To the output port O₁From the input port I (R (1) ═ 2)₁To the switching transmission line 102(R (2) ═ 1). I is₁And I₃Will continue to be transmitted on the 2 nd ring bus, i.e. the inner ring bus IR in this example, in

transmission lines

102 and 103, when the routing table R is [2,1,3 ]]。

The fourth step: and e, enabling i to be 2, enabling k to be j, repeating the second step to the third step, and determining an output port O on the 2 nd ring bus₂To output of (c). . . In this example, a (2) ═ 3, i.e., output port O₂Is from input port I₃From the input port I₃On the transmission line 103 (r (k) ═ 3)(k 3), MZ connected to the transmission line 103(k 3) is required₂₂And MZ connected to transmission line 102 (j-2)₂₁Is set to "1", i.e. the cross state. On the inner ring bus IR there are only two MZ switches connected to the output port O₂，O₃. Thus, on transmission line 103(k 3) from input port I₃To the output port O₂Output on transmission line 102(k 2) from input port I₁(R (2) ═ 1) optical signal is switched to output port O₃And (6) outputting. Update the routing table I₃-O₂(R(2)＝3)，I₁-O₃(R (3) ═ 1), to this point, routing table establishment is complete R ═ 2,3,1]. The specific implementation steps include the states of the 2 × 2 hetero MZI high-speed optical switch and the signals on the corresponding transmission lines as shown in the following table:

in the table, "1" represents that the corresponding 2 × 2 heterogeneous MZI high-speed optical switch is in the cross state, and the phase on the tuning arm is 0 at this time; a "0" indicates that the corresponding 2 x 2 hetero MZI high speed optical switch is in the on state, when the phase on the tuning arm is pi. The grey shaded areas indicate that the corresponding output ports have completed switching.

Based on the configuration mechanism of the optical switch, all 6 ═ 3! The state of the corresponding 2 × 2 hetero MZI high-speed optical switch and the associated connections are shown in the following table:

example 2

The embodiment is based on the idea of designing a novel ring turntable bus structure with 3 × 3 ports, and is extended to a ring turntable bus structure with 4 × 4 ports.

Referring to fig. 9, fig. 9 is a reconfigurable non-blocking fully connected router with 4 × 4 ports based on a ring carousel bus architecture when the present invention is applied to N ═ 4. As shown, the dotted lineThe topology structure contained in the box 002 is a reconfigurable non-blocking fully-connected router based on the 3 × 3 port ring carousel bus architecture in embodiment 2 (see fig. 8). It can be seen that, based on the ring carousel bus architecture, 4 × 4 ports are added with a ring bus based on the novel ring carousel bus structure 002 of 3 × 3 ports. Original 3X 3 port 2X 2 heterogeneous MZI high-speed optical switch serial number based on novel ring turntable bus structure is formed by MZ_ijChange to MZ_i+1,j(ii) a Output port O₁，O₂， O₃Renumbered as O₂，O₃，O₄. 4 2 multiplied by 2 heterogeneous MZI high-speed optical switches are distributed on the outer ring bus OR, and one 2 multiplied by 2 heterogeneous MZI high-speed optical switch is numbered as MZ₁₁Is connected to the input port I₁To the output port O₁And the other 2 multiplied by 2 heterogeneous MZI high-speed optical switches are numbered clockwise in sequence₁₂，MZ₁₃，MZ₁₄I.e. corresponding to the connection input port I₂，I₃，I₄。MZ₁₂，MZ₁₃，MZ₁₄Is connected in turn to the MZ₂₁，MZ₂₂，MZ₂₃And a second input port 201.

In the following, a group I is arbitrarily established₁-O₄，I₂-O₁，I₃-O₂，I₄-O₃For example, its target routing table a is [2,3,4,1 ═ 2]Referring to the flowchart of fig. 10, a 2 × 2 heterogeneous MZI high-speed optical switch configuration process of the reconfigurable non-blocking fully-connected router with 4 × 4 ports based on a ring carousel bus architecture according to the present invention is explained. .

First, all 2 × 2 heterogeneous MZI high-speed optical switch states are set to "0", which is a through state. From input port I₁，I₂，I₃，I₄On

transmission lines

101, 102, 103, 104, respectively, initializing routing

table R ═

1,2,3,4]。

Next, similarly to embodiment 1, the output port O connected to the outer ring bus (first-day ring bus) is determined₁The source address of (1). In this example, the output port O₁Is from input port I₂(A (1) ═ 2), because of the output port O₁On transmission line 101, from input port I₂The optical signal of (2) is on the transmission line 102, the MZ connected with the

transmission lines

101, 102 is needed₁₁、MZ₁₂Is set to "1", i.e. the cross state. From input port I₂Through MZ₁₂Cross into the outer ring bus OR, transmit a round and then go through MZ₁₁Is output to the output port O₁(i.e., update routing table R (1) ═ 2). From input port I for the same reason₁Through MZ₁₁Cross into the outer ring bus OR, transmit a round and then go through MZ₁₂The first output port of (2) is output to the transmission line 102 (the updated routing table R (2) ═ 1), and is transmitted to the 2 nd ring bus via the curved waveguide. At this point, the input port I is completed₂To the output port O₁The exchange of (2). From input port I₃，I₄Is still transmitted on the 2 nd ring bus in

transmission lines

103 and 104. At this time, the updated complete routing

table R ═

2,1,3,4]。

From input port I₁，I₃And I₄The optical signal enters the 2 nd ring bus, and the following steps are equivalent to the step I₁-O₄，I₃-O₂，I₄-O₃The switching, that is, the routing process of the 3 × 3 port reconfigurable non-blocking fully connected router based on the ring carousel bus architecture according to the present invention in embodiment 1, is not described again. The specific implementation steps are shown in the following table:

FIGS. 11A and 11B show an example of the present invention, 24 ═ 4! A 4 × (3 |) full connection non-blocking permutation routing table.

According to the implementation principle and the implementation process of the embodiment 1 and the embodiment 2 of the invention, the N × N port reconfigurable non-blocking full-connection router based on the ring turntable bus architecture can be easily expanded. N is a natural number arbitrarily larger than 1.

The embodiment of the invention provides a photonic integrated chip which comprises the NxN port fast reconfigurable non-blocking full-connection router based on the annular turntable bus architecture.

The embodiment of the invention provides an optical router, which comprises the photonic integrated chip provided by the embodiment of the invention.

The above examples are intended to illustrate the invention, but not to limit it. Any modification and variation of the present invention within the spirit of the present invention and the scope of the claims will fall within the scope of the present invention.

Claims

1. A reconfigurable non-blocking full-connection router based on a ring turntable bus architecture is characterized in that:

the system comprises N input ports I and N output ports O, wherein the input ports I and the output ports are connected through a ring turntable bus architecture formed by a plurality of same basic switching units (001); the annular turntable bus architecture comprises N-1 annular buses, each annular bus is numbered from outside to inside, and N +1-i basic switching units are distributed on the ith annular bus; the input ends of all basic switching units on the outermost ring bus are respectively connected with the N input ports I, from the outer side to the inner side, the output end of only one basic switching unit on the ith ring bus is connected with one output port which is uniquely corresponding to the ith ring bus, and the output ends of the rest basic switching units on the ith ring bus are respectively connected with the input ends of all basic switching units on the (I + 1) th ring bus which is adjacent to the ith ring bus in a one-to-one correspondence mode through bent waveguides.

2. The reconfigurable non-blocking fully-connected router based on the ring carousel bus architecture as claimed in claim 1, wherein: the N input ports I and the N output ports O are respectively arranged in the N passive layer waveguides, namely, the jth input port I and the jth output port O are both positioned in the jth passive layer waveguide, and interlayer waveguide coupling is realized between the passive layer waveguides through an interlayer coupler; the basic switching units on each ring bus share one layer of active layer waveguide.

3. The reconfigurable non-blocking fully-connected router based on the ring carousel bus architecture as claimed in claim 1, wherein: the basic exchange unit adopts an in-layer Mach-Zehnder optical switch designed based on a two-dimensional photonic integrated platform or a vertical direction interlayer Mach-Zehnder (MZI) optical switch designed for a three-dimensional photonic integrated platform.

4. The fast reconfigurable non-blocking fully connected router based on the ring carousel bus architecture as claimed in claim 3, wherein: comprises a first input port (202), a second input port (201), a first output port (204), a second output port (203), a first layer inner coupler (305), a second layer inner coupler (306), a reference arm (303) and a tuning arm (304) which are positioned in the same waveguide layer (301); the first input port (202) and the second input port (201) are respectively connected to two input ends of a first layer inner coupler (305), two output ends of the first layer inner coupler (305) are respectively connected to one ends of a reference arm (303) and a tuning arm (304), the other ends of the reference arm (303) and the tuning arm (304) are respectively connected to two input ends of a second layer inner coupler (306), and two output ends of the second layer inner coupler (306) are respectively connected with a first output port (204) and a second output port (203).

5. The fast reconfigurable non-blocking fully connected router based on the ring carousel bus architecture as claimed in claim 3, wherein: the basic switching unit comprises a first input port (202), a second input port (201), a first output port (204), a second output port (203), a reference arm (303) and a tuning arm (304) which are positioned in different waveguide layers (301, 302), wherein the second input port (201), the reference arm (303) and the second output port (203) are positioned in an upper waveguide layer (301), and the first input port (202), the tuning arm (304) and the first output port (204) are positioned in a lower waveguide layer (302); the first input port (202) and the second input port (201) are respectively connected to two input ends of a first interlayer coupler (307), two output ends of the first interlayer coupler (307) are respectively connected to one ends of a reference arm (303) and a tuning arm (304), the other ends of the reference arm (303) and the tuning arm (304) are respectively connected to two input ends of a second interlayer coupler (308), and two output ends of the second interlayer coupler (308) are respectively connected with a first output port (204) and a second output port (203); the first interlayer coupler (307) and the second interlayer coupler (308) are each arranged vertically across the upper waveguide layer (301) and the lower waveguide layer (302).

6. The fast reconfigurable non-blocking fully connected router based on the ring carousel bus architecture as claimed in claim 4, wherein: the materials of the upper waveguide layer (301) and the lower waveguide layer (302) are different, the lower waveguide layer (302) is shared by the basic switching units on each ring bus, a ring-shaped active layer waveguide is arranged on the lower waveguide layer (302), and the first input port (202), the tuning arm (304) and the first output port (204) in each basic switching unit on each ring bus are all located on the ring-shaped active layer waveguide.

7. The fast reconfigurable non-blocking fully connected router based on the ring carousel bus architecture as claimed in claim 5, wherein: n upper waveguide layers (301) are arranged on the lower waveguide layer (302), the upper waveguide layer (301) is a passive layer waveguide, N input ports I and N output ports O are respectively arranged in the N upper waveguide layers (301), namely, the jth input port I and the jth output port O are both positioned in the jth upper waveguide layer (301), and interlayer waveguide coupling is realized between the upper waveguide layers (301) through an interlayer coupler.