CN113707556A - Manufacturing method of thin film transistor, thin film transistor and display device - Google Patents

Manufacturing method of thin film transistor, thin film transistor and display device Download PDF

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Publication number
CN113707556A
CN113707556A CN202110929938.1A CN202110929938A CN113707556A CN 113707556 A CN113707556 A CN 113707556A CN 202110929938 A CN202110929938 A CN 202110929938A CN 113707556 A CN113707556 A CN 113707556A
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layer
semiconductor layer
photoresist
forming
source
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胡道兵
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TCL China Star Optoelectronics Technology Co Ltd
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TCL China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

The application provides a manufacturing method of a thin film transistor, the thin film transistor and a display device, wherein the thin film transistor comprises a grid electrode, a grid insulating layer and a first semiconductor layer which are sequentially stacked on a substrate, and the thin film transistor further comprises: the etching barrier layer is arranged on the first semiconductor layer, and a source drain region is arranged on the etching barrier layer; the second semiconductor layer is arranged on the etching barrier layer and is in contact with the first semiconductor layer through the source drain region; and the source drain layer is arranged on the second semiconductor layer. According to the method, the photoresist layer is coated on the first semiconductor layer and is patterned, the patterned photoresist layer in the first semiconductor layer is stripped after the etching barrier layer is formed on the first semiconductor layer, so that the source drain region is formed on the etching barrier layer, and the photoresist layer can be removed in an exposure and development mode, so that the channel region is prevented from being bombarded by plasma to shorten the length of the channel region, and the method is favorable for improving the precision of a thin film transistor manufacturing process.

Description

Manufacturing method of thin film transistor, thin film transistor and display device
Technical Field
The present disclosure relates to the field of display device technologies, and in particular, to a method for manufacturing a thin film transistor, and a display device.
Background
Currently, in the technology for manufacturing oxide thin film transistors, there are three main device structures: back Channel Etched (BCE), Etch-Stop Layer (ESL), and Top Gate (Top Gate, TG).
The back channel etching type structure has a simple process and low cost, but the back channel etching type process omits a composition process of an etching barrier layer, but the source and drain layers are patterned on the active layer by wet etching, so that the semiconductor layer is corroded and damaged by etching liquid to cause difficulty in manufacturing the thin film transistor device or abnormal characteristics, the etching barrier layer structure can effectively protect the active layer, but due to process limitation, the length of a channel region is shortened in the manufacturing process of the process at present, so that the influence of a gate of the thin film transistor on heavily doped regions on two sides of the channel region is increased, and the short channel effect in the channel region becomes more obvious, so that the characteristics of the thin film transistor become poor.
Disclosure of Invention
The application provides a manufacturing method of a thin film transistor, the thin film transistor and a display device, and aims to solve the problem that a channel region is easy to damage.
In a first aspect, the present application provides a method for manufacturing a thin film transistor, including:
forming a first semiconductor layer on a substrate;
coating a photoresist layer on the first semiconductor layer;
patterning the photoresist layer;
forming an etching barrier layer on the first semiconductor layer;
stripping the patterned photoresist layer in the first semiconductor layer to form a source drain region on the etching barrier layer;
and forming a source drain layer on the etching barrier layer.
In one possible implementation manner of the present application, the material of the etching barrier layer is organic siloxane;
the step of forming an etching barrier layer on the first semiconductor layer further includes:
and carrying out oxidation treatment on the etching barrier layer by adopting ozone so that the organic siloxane forms silicon oxide.
In one possible implementation manner of the present application, the photoresist layer includes a first photoresist portion and a second photoresist portion, the first photoresist portion is disposed on the photoresist layer corresponding to the source/drain region, and the second photoresist portion is disposed on the photoresist layer corresponding to a region other than the source/drain region;
the step of patterning the photoresist layer comprises:
and exposing and developing the photoresist layer to reserve the first photoresist part and remove the second photoresist part.
In a possible implementation manner of the present application, the step of forming the source drain layer on the etching stopper layer further includes:
forming a second semiconductor layer on the etching barrier layer, wherein the second semiconductor layer is in contact with the first semiconductor layer through the source drain region;
and forming the source drain layer on the second semiconductor layer.
In a possible implementation manner of the present application, the step of forming the source/drain layer on the second semiconductor layer further includes:
forming a first metal layer on the second semiconductor layer;
etching the middle part of the first metal layer by a yellow light process and a wet etching method to form a source drain layer in a source drain region;
and etching the middle part of the second semiconductor layer by a dry etching method to form a channel region, wherein the channel region penetrates through the source drain layer and the second semiconductor layer.
In a possible implementation manner of the present application, the source and drain regions include a source region and a drain region that are arranged at an interval, and the step of forming the second semiconductor layer on the etching blocking layer further includes:
and etching the second semiconductor layer corresponding to the source region to form a first hole, and etching the second semiconductor layer corresponding to the drain region to form a second hole.
In one possible implementation manner of the present application, before the step of forming the first semiconductor layer on the substrate, the method further includes:
a second metal layer formed on the substrate by physical vapor deposition;
patterning the second metal layer;
and depositing a gate insulating layer on the second metal layer.
In a possible implementation manner of the present application, the step of forming the source drain layer on the etching stopper layer further includes:
and manufacturing a passivation layer on the source drain layer by adopting a vapor deposition method.
In a second aspect, the present application further provides a thin film transistor fabricated by the method.
In a third aspect, the present application further provides a display device comprising the thin film transistor.
The application provides a manufacturing method of a thin film transistor, the thin film transistor and a display device. Compared with the method for manufacturing the etching barrier layer by adopting a dry etching process, the method has the advantages that the photoresist layer can be removed by adopting an exposure and development mode, so that the length of the channel region can be prevented from being shortened due to the bombardment of plasma on the channel region, the precision of the thin film transistor manufacturing process is improved, and the stability of the performance of the thin film transistor is ensured.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic flow chart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.
Fig. 2 is a schematic diagram of step S101 in a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.
Fig. 3 is a schematic diagram of step S102 in the method for manufacturing a thin film transistor according to the embodiment of the present application.
Fig. 4 is a schematic diagram of step S103 in the method for manufacturing a thin film transistor according to the embodiment of the present application.
Fig. 5 is a schematic diagram of step S104 in the method for manufacturing a thin film transistor according to the embodiment of the present application.
Fig. 6 is a schematic diagram of step S105 in the method for manufacturing a thin film transistor according to the embodiment of the present application.
Fig. 7 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
Embodiments of the present invention provide a method for manufacturing a thin film transistor, and a display device, which are described in detail below.
First, an embodiment of the present invention provides a method for manufacturing a thin film transistor, please refer to fig. 1, which includes the following steps S101 to S106.
S101, a first semiconductor layer 40 is formed on the substrate 10.
As shown in fig. 2, the first semiconductor layer 40, i.e., the active layer, may be one of Amorphous Silicon (a-Si), Low Temperature Polysilicon (LTPS), and a metal Oxide semiconductor, such as Indium Gallium Zinc Oxide (IGZO).
S102, coating a photoresist layer 90 on the first semiconductor layer 40.
The Photoresist layer 90 may be Photoresist (PR), and the Photoresist layer 90 may be a positive Photoresist or a negative Photoresist, and may be coated by static coating or dynamic coating. And is not particularly limited herein.
S103, patterning the photoresist layer 90.
As shown in fig. 3, when the second semiconductor layer 60 is fabricated through the process steps of exposure, development, etching, etc., the target region of the first semiconductor layer 40 is masked by the photoresist layer 90, so that the target region portion in the first semiconductor layer 40 is remained as the first semiconductor layer 40 region.
And S104, forming an etching barrier layer 50 on the first semiconductor layer 40.
As shown in fig. 4, an Etch Stop Layer (ESL) structure is used to prevent channel Etch damage to the thin film transistor. The etch barrier layer 50 may be one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (sion x), or the like.
S105, stripping the patterned photoresist layer 90 in the first semiconductor layer 40, so as to form a source/drain region 51 on the etch stop layer 50.
As shown in fig. 5, the patterned photoresist layer 90 may also be stripped by exposure and development, and the source/drain regions 51 are formed at the positions of the stripped photoresist layer 90.
And S106, forming a source drain layer 70 on the etching barrier layer 50.
The source drain layer 70 includes a source and a drain.
The embodiment of the present application provides a method for manufacturing a thin film transistor, which includes coating a photoresist layer 90 on a first semiconductor layer 40, patterning the photoresist layer 90, forming an etching barrier layer 50 on the first semiconductor layer 40, and then stripping the patterned photoresist layer 90 in the first semiconductor layer 40, so that a source/drain region 51 is formed on the etching barrier layer 50 to form a source/drain electrode layer 70. Compared with the method for manufacturing the etching barrier layer 50 by adopting the dry etching process, the method has the advantages that the photoresist layer 90 can be removed by adopting an exposure and development mode, so that the length of the channel region can be prevented from being shortened due to the bombardment of plasma on the channel region, the precision of the thin film transistor manufacturing process can be improved, and the stability of the performance of the thin film transistor can be ensured.
In some embodiments, the material of the etch stop layer 50 is an organosiloxane. The step S104 of forming the etching stop layer 50 on the first semiconductor layer 40 further includes the following steps:
1) and oxidizing the etch stop layer 50 with ozone to form silicon oxide from the organosiloxane.
Using ozone (O)3) To etchingThe barrier layer 50 is subjected to oxidation treatment, so that inorganic silicon oxide is formed on the surface of the organic siloxane, then the inorganic silicon oxide is heated and cured to obtain a silicon oxide layer, and the silicon oxide layer is used as the etching barrier layer 50.
Of course, in addition to the ozone process, in other embodiments, the etching barrier layer 50 may also be formed by other preparation processes such as a magnetron sputtering deposition process, a plasma chemical vapor deposition process, a low pressure chemical vapor deposition process, an atmospheric pressure chemical vapor deposition process, and the like, which is not limited herein.
In some embodiments, the photoresist layer 90 includes a first photoresist portion 91 and a second photoresist portion 92, the first photoresist portion 91 is disposed on the photoresist layer 90 corresponding to the source and drain regions 51, and the second photoresist portion 92 is disposed on the photoresist layer 90 corresponding to a region other than the source and drain regions 51;
referring to fig. 3-4, the step S103 of patterning the photoresist layer 90 includes:
s301, exposing and developing the photoresist layer 90 to retain the first photoresist portion 91 and remove the second photoresist portion 92.
The photoresist layer 90 may be a positive photoresist or a negative photoresist. For positive photoresist, the exposed portions are soluble in the developer, and the unexposed portions are insoluble in the developer; for negative tone photoresists, the exposed portions are insoluble in the developer solution and the unexposed portions are soluble in the developer solution.
In some embodiments, the step S106, forming the source/drain layer 70 on the etch stop layer 50, further includes the following steps S601-S602.
S601, forming a second semiconductor layer 60 on the etching barrier layer 50, wherein the second semiconductor layer 60 is in contact with the first semiconductor layer 40 through the source-drain region 51.
The second semiconductor layer 60 is a P-type doped amorphous silicon layer, and may specifically be P-type heavily doped amorphous silicon, the heavily doped means may be an ion implantation method, the ion implantation gas may be phosphine (PH3), and the implantation amount and the implantation time may be adjusted according to the film thickness of the first semiconductor layer 40.
S602, forming the source/drain layer 70 on the second semiconductor layer 60.
The connecting parts corresponding to the source electrode and the drain electrode in the source drain electrode layer 70 can be doped with impurities with concentration higher than that of the channel part, the trailing of the semiconductor formed in the first wet etching is subjected to P-type heavy doping, the trailing of the amorphous silicon of the first semiconductor layer 40 which can generate photoelectric effect originally is converted into the heavily doped amorphous silicon which is insensitive to illumination, the trailing of the semiconductor is eliminated, the capacitance change caused by the photoelectric effect when the trailing of the semiconductor at the position of the thin film transistor is started in a backlight mode is avoided, the poor water ripple is effectively avoided, the poor water ripple cannot be caused by the heavily doped amorphous silicon of the conductor property, the channel area 601 is still the polycrystalline silicon of the semiconductor property, namely the active layer, and the switching characteristic of the transistor is ensured to be unchanged.
Of course, it is understood that the second semiconductor layer 60 may be doped P-type or N-type, and is not limited herein.
In some embodiments, the step S602 of forming the source drain layer 70 on the second semiconductor layer 60 further includes the following steps S603 to S604.
And S603, forming a first metal layer on the second semiconductor layer 60.
And S604, etching away the middle part of the first metal layer through a yellow light process and a wet etching method to form a source drain layer 70 in the source drain region 51.
The photomask for patterning the first metal film by the yellow light process and the wet etching method is a gray-scale photomask or a halftone photomask.
And S605, etching the middle part of the second semiconductor layer 60 by a dry etching method to form a channel region 601, wherein the channel region 601 penetrates through the source/drain layer 70 and the second semiconductor layer 60.
Since the second semiconductor layer 60 is disposed on the channel region 601, the first semiconductor layer 40 of the channel region 601 is protected from being damaged by etching, which is beneficial to improving the stability of the thin film transistor.
The channel region 601 is opposite to the gate layer 20 of the transistor, and when a voltage signal applied to the gate layer 20 reaches a certain value, a carrier path is formed in the channel region 601, so that the source and the drain of the thin film transistor are conducted.
In some embodiments, referring to fig. 5, the source and drain regions 51 include a source region 511 and a drain region 512 that are spaced apart from each other.
A source region 511 is disposed corresponding to the source, and the second semiconductor layer 60 is partially located in the source region 511. The drain region 512 is disposed corresponding to the drain, and the source region 511 and the drain region 512 are disposed at intervals.
The step S601 of forming the second semiconductor layer 60 on the etching stopper layer 50 further includes:
and S606, etching the second semiconductor layer 60 corresponding to the source region 511 to form a first hole 61, and etching the second semiconductor layer corresponding to the drain region 512 to form a second hole 62.
By providing the first hole 61 and the second hole 62 in the second semiconductor layer 60 corresponding to the source region 511 and the drain region 512, respectively, the source-drain layer 70 can be better contacted with the first semiconductor layer 40, thereby ensuring good switching characteristics of the transistor.
In some embodiments, referring to fig. 1, the step S101, before the step of forming the first semiconductor layer 40 on the substrate 10, further includes the following steps S11-S13.
And S11, forming a second metal layer on the substrate 10 by adopting physical vapor deposition.
The second metal layer is a grid metal layer.
And S12, patterning the second metal layer.
The gate layer 20 is formed by patterning the second metal layer.
And S13, depositing a gate insulating layer on the second metal layer.
In some embodiments, referring to fig. 7, in the step S106, forming a source/drain layer 70 on the etch stop layer 50, further includes the following step S606:
and S606, manufacturing a passivation layer on the source drain layer 70 by adopting a vapor deposition method.
The passivation layer 80 is disposed on the source/drain electrode layer 70, and the passivation layer contacts the second semiconductor layer 60 through the channel region 601, so that the source/drain electrode layer 70 can be protected through the passivation layer, and the reliability and stability of the thin film transistor can be further improved.
In order to better implement the manufacturing method of the thin film transistor, the application also provides a thin film transistor manufactured by the manufacturing method. Since the thin film transistor is manufactured by the manufacturing method, all the same beneficial effects are achieved, and the details are not repeated herein.
In order to better implement the manufacturing method of the thin film transistor, the application also provides a display device which comprises the thin film transistor. The embodiment of the application is not specifically limited to the application of the display device, and the display device can be any product or part with a display function, such as a television, a notebook computer, a tablet computer, wearable display equipment (such as an intelligent bracelet, an intelligent watch and the like), a mobile phone, virtual reality equipment, augmented reality equipment, vehicle-mounted display, an advertising lamp box and the like.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In a specific implementation, each unit or structure may be implemented as an independent entity, or may be combined arbitrarily to be implemented as one or several entities, and the specific implementation of each unit or structure may refer to the foregoing method embodiment, which is not described herein again.
The above detailed description is made on the manufacturing method of the thin film transistor, and the display device provided in the embodiments of the present application, and specific examples are applied in this text to explain the principle and implementation manner of the embodiments of the present application, and the description of the embodiments is only used to help understanding the technical solution and the core idea of the embodiments of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims (10)

1. A method for manufacturing a thin film transistor includes:
forming a first semiconductor layer on a substrate;
coating a photoresist layer on the first semiconductor layer;
patterning the photoresist layer;
forming an etching barrier layer on the first semiconductor layer;
stripping the patterned photoresist layer in the first semiconductor layer to form a source drain region on the etching barrier layer;
and forming a source drain layer on the etching barrier layer.
2. The method of claim 1, wherein the etch stop layer is made of an organosiloxane;
the step of forming an etching barrier layer on the first semiconductor layer further includes:
and carrying out oxidation treatment on the etching barrier layer by adopting ozone so that the organic siloxane forms silicon oxide.
3. The method according to claim 1, wherein the photoresist layer includes a first photoresist portion and a second photoresist portion, the first photoresist portion is disposed on the photoresist layer corresponding to the source and drain regions, and the second photoresist portion is disposed on the photoresist layer corresponding to a region other than the source and drain regions;
the step of patterning the photoresist layer comprises:
and exposing and developing the photoresist layer to reserve the first photoresist part and remove the second photoresist part.
4. The method of claim 1, wherein the step of forming a source drain layer on the etch stop layer further comprises:
forming a second semiconductor layer on the etching barrier layer, wherein the second semiconductor layer is in contact with the first semiconductor layer through the source drain region;
and forming the source drain layer on the second semiconductor layer.
5. The method of claim 4, wherein the step of forming the source drain layer on the second semiconductor layer further comprises:
forming a first metal layer on the second semiconductor layer;
etching the middle part of the first metal layer by a yellow light process and a wet etching method to form a source drain layer in a source drain region;
and etching the middle part of the second semiconductor layer by a dry etching method to form a channel region, wherein the channel region penetrates through the source drain layer and the second semiconductor layer.
6. The method according to claim 2, wherein the source and drain regions comprise source and drain regions arranged at intervals, and the step of forming the second semiconductor layer on the etch stop layer further comprises:
and etching the second semiconductor layer corresponding to the source region to form a first hole, and etching the second semiconductor layer corresponding to the drain region to form a second hole.
7. The method of manufacturing of claim 1, wherein the step of forming the first semiconductor layer on the substrate further comprises, prior to the step of forming the first semiconductor layer on the substrate:
a second metal layer formed on the substrate by physical vapor deposition;
patterning the second metal layer;
and depositing a gate insulating layer on the second metal layer.
8. The method of any of claims 1-7, wherein the step of forming a source drain layer on the etch stop layer further comprises:
and manufacturing a passivation layer on the source drain layer by adopting a vapor deposition method.
9. A thin film transistor formed by the manufacturing method according to any one of claims 1 to 8.
10. A display device comprising the thin film transistor according to claim 9.
CN202110929938.1A 2021-08-13 2021-08-13 Manufacturing method of thin film transistor, thin film transistor and display device Pending CN113707556A (en)

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Application publication date: 20211126