CN113707094B - Display panel, driving circuit and driving method of display panel - Google Patents
Display panel, driving circuit and driving method of display panel Download PDFInfo
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- CN113707094B CN113707094B CN202110984318.8A CN202110984318A CN113707094B CN 113707094 B CN113707094 B CN 113707094B CN 202110984318 A CN202110984318 A CN 202110984318A CN 113707094 B CN113707094 B CN 113707094B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
Abstract
The disclosure provides a display panel, a driving circuit of the display panel and a driving method. The drive circuit includes: the source driving chips can output a first data signal; the time schedule controller can be in communication matching with the source electrode driving chips according to a preset communication protocol and can output a matching signal according to the result of the communication matching; and the control circuit can receive the matching signal and a first data signal output by at least one source driving chip and output a control signal to the pixel circuit according to the first data signal and the matching signal. The present disclosure can prevent an excessive load.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a display panel, a driving circuit of the display panel, and a driving method of the display panel.
Background
Compared to a TFT-LCD Display (Thin Film Transistor-Liquid Crystal Display), an AMOLED Display (AMOLED) has more advantages, such as: the liquid crystal display panel has the advantages of no need of backlight, high response speed, high contrast, wide viewing angle, low energy consumption, capability of realizing soft display and the like, and has great development in the field of panel display in the future. However, the large-sized AMOLED display is excessively loaded.
Disclosure of Invention
The present disclosure provides a display panel, a driving circuit of the display panel, and a driving method of the display panel, which can prevent an excessive load.
According to an aspect of the present disclosure, there is provided a driving circuit of a display panel connected with a pixel circuit of the display panel, the driving circuit including:
the source driving chips can output a first data signal;
the time schedule controller can be in communication matching with the source electrode driving chips according to a preset communication protocol and can output a matching signal according to a communication matching result;
and the control circuit can receive the matching signal and a first data signal output by at least one source driving chip and output a control signal to the pixel circuit according to the first data signal and the matching signal.
Further, when the timing controller and the source driving chips are successfully matched in a communication mode, the timing controller outputs a first matching signal, the control circuit outputs the first data signal to the display panel according to the first data signal and the first matching signal, and the first data signal forms the control signal.
Further, the pixel circuit is composed of P-type transistors, when the communication matching between the timing controller and at least one of the source driving chips fails, the timing controller outputs a second matching signal, and the control circuit outputs a high-level control signal to the pixel circuit according to the first data signal and the second matching signal.
Further, the pixel circuit is composed of N-type transistors, when the communication matching between the timing controller and at least one of the source driving chips fails, the timing controller outputs a second matching signal, and the control circuit outputs a low-level control signal to the pixel circuit according to the first data signal and the second matching signal.
Furthermore, the number of the control circuits is multiple, and the multiple control circuits can correspondingly receive the first data signals output by the multiple source driver chips one to one.
Further, the driving circuit further includes:
and the power supply management chip is connected with the source electrode driving chip and is used for sending the binding voltage signal of the gray scale to the source electrode driving chip.
Further, the driving circuit further includes:
and the electroluminescent chip is connected with the pixel circuit and used for sending a driving power supply voltage signal and a low-level power supply voltage signal to the pixel circuit.
Furthermore, the time schedule controller and the control circuit are arranged on the same circuit board.
Furthermore, the circuit board is connected with the pixel circuit through a chip on film, and the chip on film is provided with the source driving chip.
Further, the display panel comprises a display area and a peripheral area surrounding the display area, and the source driving chip, the timing controller and the control circuit are all located in the peripheral area.
Further, when the timing controller is successfully matched with the source driving chips in a communication mode, the timing controller outputs a second data signal to the source driving chips, and the source driving chips generate the first data signal according to the second data signal.
According to one aspect of the present disclosure, a display panel is provided, which includes the driving circuit.
According to an aspect of the present disclosure, there is provided a driving method of a display panel, the driving method employing the driving circuit, the driving method including:
enabling a plurality of source driving chips to output first data signals;
enabling the time schedule controller to be in communication matching with the source electrode driving chips according to a preset communication protocol, and enabling the time schedule controller to output matching signals according to the result of the communication matching;
and enabling the control circuit to receive the matching signal and a first data signal output by at least one source electrode driving chip, and enabling the control circuit to output a control signal to the pixel circuit according to the first data signal and the matching signal.
According to the display panel, the driving circuit of the display panel and the driving method of the display panel, the control circuit can receive the matching signal and the first data signal output by the at least one source electrode driving chip and output the control signal to the pixel circuit according to the first data signal and the matching signal, so that the control signal output to the pixel circuit can be adjusted by the control circuit when the communication matching between the time schedule controller and the source electrode driving chip fails, the transistors in the pixel circuit are prevented from being turned on, high-brightness pictures are prevented from appearing, and the load is prevented from being overlarge.
Drawings
Fig. 1 is a schematic view of a display panel according to an embodiment of the present disclosure.
Fig. 2 is a block diagram of a drive circuit of an embodiment of the present disclosure.
Fig. 3 is a block diagram of a source driver chip in the driving circuit of the embodiment of the present disclosure.
Fig. 4 is a timing diagram of a pixel circuit of the display panel of the embodiment of the present disclosure.
Fig. 5 is a timing diagram of a clock signal and a match signal of an embodiment of the disclosure.
FIG. 6 is another timing diagram of the clock signal and the match signal of an embodiment of the disclosure.
Description of reference numerals: 1. a time schedule controller; 2. a source driver chip; 201. an analog-to-digital converter; 3. a control circuit; 4. a pixel circuit; 5. a power management chip; 6. an electroluminescent chip; 7. a circuit board; 8. a chip on film; 9. a connecting wire; 100. a display area; 200. a peripheral region.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary implementations below do not represent all implementations consistent with the present disclosure. Rather, they are merely examples of devices consistent with certain aspects of the present disclosure, as detailed in the appended claims.
The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in the description and claims does not indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" or "a number" means two or more. Unless otherwise indicated, "front," "back," "lower," and/or "upper," and the like are for convenience of description, and are not limited to one position or one spatial orientation. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in this disclosure and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
In the related art, the driving circuit of the large-sized AMOLED display includes a Timing Controller (TCON) and a plurality of Source driving chips (Source ICs). In practical application, each source driving chip can normally work only when the time schedule controller is successfully communicated and matched with all the source driving chips, otherwise, a low-potential signal can be output. When a pixel circuit of the AMOLED display is composed of PMOS tubes, a low potential signal output by a source electrode driving chip can open the PMOS tubes to cause a short-time high-brightness picture, so that the load of an electroluminescent chip (ELIC) is greatly increased, the ELIC can normally work only by being completely restarted, and meanwhile, because the load of the electroluminescent chip (ELIC) is large, a large amount of heat is easily accumulated in a short time, and the product is easily burnt.
The embodiment of the disclosure provides a driving circuit of a display panel. As shown in fig. 1 and fig. 2, the display panel may include a display area 100 (AA area for short) and a peripheral area 200 surrounding the display area 100. The display area 100 may include light emitting elements arranged in an array. The Light emitting element may be an Organic Light-emitting diode (OLED). Each light emitting element may be provided with a pixel circuit 4 for driving the light emitting element to emit light. The pixel circuit 4 may be constituted by a plurality of transistors. The transistor may be a P-type transistor, such as a PMOS transistor, but the disclosure is not limited thereto, and the transistor may also be an N-type transistor, such as an NMOS transistor. The display panel may further include a plurality of gate lines and a plurality of data lines. The pixel circuits 4 of the light emitting elements in the same row among the light emitting elements in the array arrangement may be connected to the same gate line, and the pixel circuits 4 of the light emitting elements in the same column among the light emitting elements in the array arrangement may be connected to the same data line. The driving circuit of the display panel of the present disclosure may include a source driving chip 2, a timing controller 1, and a control circuit 3, wherein:
the number of the source driver chips 2 is plural, and each source driver chip 2 can output a first data signal. The timing controller 1 can perform communication matching with the plurality of source driving chips 2 according to a preset communication protocol, and can output a matching signal according to a result of the communication matching. The control circuit 3 is capable of receiving a matching signal and a first data signal output by at least one source driver chip 2, and outputting a control signal to the pixel circuit 4 according to the first data signal and the matching signal.
In the driving circuit of the display panel according to the embodiment of the present disclosure, the control circuit 3 can receive the matching signal and the first data signal output by the at least one source driving chip 2, and output the control signal to the pixel circuit 4 according to the first data signal and the matching signal, so that when the communication matching between the timing controller 1 and the source driving chip 2 fails, the control circuit 3 can adjust the control signal output to the pixel circuit 4, thereby avoiding turning on the transistor in the pixel circuit 4, preventing a highlight picture from occurring, and preventing an overload from occurring.
The following describes each part of the driving circuit of the display panel according to the embodiment of the present disclosure in detail:
the timing controller 1 may be disposed in the peripheral region 200 of the display panel. The timing controller 1 can perform communication matching with a plurality of source driving chips 2 according to a preset communication protocol. The predetermined communication protocol may be XHI, PHI, CHPI, or the like. The timing controller 1 is also capable of outputting a matching signal according to the result of communication matching. The matching signal may include a first matching signal and a second matching signal. When the timing controller 1 and the plurality of source driving chips 2 are successfully matched in a communication manner, the timing controller 1 outputs a first matching signal. The first matching signal may be a high level signal, and of course, the first matching signal may also be a low level signal. When the timing controller 1 fails to communicate with at least one source driving chip 2 for matching, the timing controller 1 outputs a second matching signal. The second matching signal may be a high level signal, and of course, the second matching signal may also be a low level signal. For example, the first matching signal is a high level signal, and the second matching signal is a low level signal. In addition, after the timing controller 1 is successfully matched in communication with each of the plurality of source driving chips 2, the timing controller 1 can input a second data signal to each of the source driving chips 2. The second data signal may be a digital signal, but the disclosed embodiments are not limited thereto. The second data signal may include image data information of the display panel. When the communication matching between the timing controller 1 and at least one of the source driving chips 2 fails, the timing controller 1 cannot input the second data signal to each of the source driving chips 2.
As shown in fig. 4, the display process of the display panel may include a data writing phase S1 and a blanking phase S2. The blanking phase S2 may be a vertical blanking (V-blanking) phase. The above-described communication matching process of the timing controller 1 and the source driving chip 2 may occur in the blanking period S2. Taking a preset communication protocol as PHI as an example, in the blanking period S2, the process of the timing controller 1 performing communication matching with the plurality of source driver chips 2 includes: as shown in fig. 5, the timing controller 1 transmits a clock signal BCLC and a matching signal BCLD to each source driving chip 2. At each rising edge of the clock signal BCLC, the timing controller 1 tries to handshake with the source driving chips 2, only the timing controller 1 successfully handshakes with all the source driving chips 2, and the timing controller 1 successfully communicates with all the source driving chips 2, the timing controller 1 pulls up and holds the potential of the matching signal BCLD, and at the same time, the timing controller 1 outputs a second data signal to each source driving chip 2.
The source driver chip 2 may be disposed in the peripheral region 200 of the display panel. The number of the Source driver chips 2 (Source ICs) may be two, three, four, or more. The source driving chip 2 may include a first signal input terminal. The first signal input terminal is used for receiving a second data signal sent by the timing controller 1. The source driving chip 2 may include a second signal input terminal and a third signal input terminal. The second signal input terminal is used for receiving the clock signal transmitted by the timing controller 1. The third signal input terminal is used for receiving the matching signal sent by the timing controller 1. The source driving chip 2 may further include a data signal output terminal. The data signal output terminal is capable of outputting a first data signal. When the source driving chip 2 receives the second data signal output from the timing controller 1, the source driving chip 2 may generate the first data signal according to the second data signal. The second data signal includes image data information of the display panel, so that the first data signal generated according to the second data signal also includes the image data information of the display panel. The first data signal generated according to the second data signal may be an analog signal, but this is not particularly limited in the embodiments of the present disclosure. As shown in fig. 3, the source driver chip 2 of the present disclosure is provided with an analog-to-digital converter 201, an input end of which can receive the second data signal, and an output end of which can output the first data signal, so as to convert the digital signal into an analog signal. In addition, when the source driving chip 2 does not receive the second data signal, the data signal output terminal of the source driving chip 2 may output the first data signal of a low level, but the disclosure is not limited thereto.
The control circuit 3 may be disposed in the peripheral region 200 of the display panel, and of course, the control circuit 3 may also be disposed in the display region 100 of the display panel. The number of the control circuits 3 may be one, two, three or more. Taking the number of the control circuits 3 as a plurality of examples, the number of the control circuits 3 may be the same as the number of the source driver chips 2, and of course, the number of the control circuits 3 may also be smaller than the number of the source driver chips 2, but the embodiment of the present disclosure is not limited thereto. The control circuit 3 may be connected to a data signal output terminal of at least one source driver chip 2 to receive a first data signal output from the data signal terminal. Taking the same number of the control circuits 3 as the number of the source driver chips 2 as an example, the plurality of control circuits 3 are connected to the plurality of source driver chips 2 in a one-to-one correspondence manner, that is, the signal output end of each source driver chip 2 is connected to one control circuit 3, so that the plurality of control circuits 3 receive the first data signals sent by the plurality of source driver chips 2 in a one-to-one correspondence manner.
The control circuit 3 may also receive a matching signal sent by the timing controller 1. The control circuit 3 may output a control signal based on the received first data signal and the match signal. Taking the example that the matching signal includes the first matching signal, when the control circuit 3 receives the first matching signal and the first data signal, the control circuit 3 may output the received first data signal. The control circuit 3 may be connected to the pixel circuit 4 to output the first data signal to the pixel circuit 4. Specifically, the output terminal of the control circuit 3 may be connected to the data line described above to output the first data signal to the pixel circuit 4 through the data line. Since the first data signal generated according to the second data signal contains the image data information of the display panel, the pixel circuit 4 can receive the image data information and drive the display panel to display the image according to the image data information.
For example, when the control circuit 3 receives the second matching signal and the low-level first data signal, and when the timing controller 1 fails to communicate with the source driver chip 2, that is, when the timing controller 1 is disconnected from the source driver chip 2, the control circuit 3 may output a high-level control signal to the pixel circuit 4 at a communication matching failure stage T1 to turn off the P-type transistor in the pixel circuit 4, so that the light-emitting element connected to the pixel circuit 4 cannot emit light, and a black frame is inserted to reduce the brightness of the display panel when the timing controller 1 fails to communicate with the source driver chip 2, thereby solving the problem that the display panel is burned by a large current due to an excessively high brightness; in the above communication matching failure stage T1, the timing controller 1 will continuously perform communication matching with the source driver chip 2, and the timing controller 1 will continuously try to perform handshake with the source driver chip 2 until the communication matching success stage T2 is entered, and the timing controller 1 will pull up the potential of the matching signal BCLD and keep it. Taking the example where the matching signal includes the second matching signal and the pixel circuit 4 is configured by an N-type transistor, when the control circuit 3 receives the second matching signal and the first data signal at a low level, the control circuit 3 may output a control signal at a low level to the pixel circuit 4 to turn off the N-type transistor in the pixel circuit 4.
The control circuit 3 may be composed of a combination of logic gates. Those skilled in the art will appreciate that various combinations of logic gates may be provided to implement the function of the control circuit 3, and the combination of logic gates is not listed in this disclosure.
As shown in fig. 2, the driving circuit of the display panel according to the embodiment of the disclosure may further include a Power Management IC (PMIC) chip 5. The power management chip 5 is connected to each of the plurality of source driver chips 2. The power management chip 5 is configured to send a gray-scale binding voltage signal to each source driver chip 2. The gray level binding voltage is a gamma voltage reference voltage. The source driver chip 2 is configured to convert the second data signal into the first data signal according to the tie voltage.
As shown in fig. 2, the driving circuit of the display panel of the embodiment of the present disclosure may further include an Electro-Luminescence chip 6 (ELIC). The electro-luminescence chip 6 may be connected to the pixel circuit 4 for transmitting a driving power voltage signal ELVDD and a low-level power voltage signal ELVSS to the pixel circuit 4 to cause the pixel circuit 4 to drive the light emitting element to emit light. The source driving chip 2 may send a light emission enable signal to the electro-luminescence chip 6, and the electro-luminescence chip 6 responds to the light emission enable signal and sends a driving power voltage signal ELVDD and a low-level power voltage signal ELVSS to the pixel circuit 4.
As shown in fig. 2, the display panel of the embodiment of the present disclosure may further include a circuit board 7. The circuit board 7 may be disposed in the peripheral region 200 of the display panel. The timing controller 1, the control circuit 3, the power management chip 5 and the electroluminescent chip 6 can be disposed on the circuit board 7, that is, the timing controller 1, the control circuit 3, the power management chip 5 and the electroluminescent chip 6 are disposed on the same circuit board 7. The circuit board 7 may further have a power chip thereon to supply power to the timing controller 1, the control circuit 3, the power management chip 5, and the electroluminescent chip 6. The circuit board 7 may be connected to the pixel circuits 4 of the display panel through a flip-chip film 8. The chip on film 8 may be provided with the source driver chip 2. The number of the above-mentioned circuit boards 7 may be plural, and the plural circuit boards 7 may be connected by a connection line 9. At the connection lines 9, the display panel may be folded.
The embodiment of the disclosure also provides a driving method of the display panel. The driving method may employ the driving circuit described in any of the above embodiments. The driving method may include: making the plurality of source driving chips 2 output first data signals; enabling the time schedule controller 1 and the source electrode driving chips 2 to carry out communication matching according to a preset communication protocol, and enabling the time schedule controller 1 to output matching signals according to the result of the communication matching; the control circuit 3 is enabled to receive the matching signal and the first data signal output by the at least one source driving chip 2, and the control circuit 3 is enabled to output a control signal to the pixel circuit 4 according to the first data signal and the matching signal.
The embodiment of the disclosure also provides a display panel. The display panel may include the driving circuit described in any of the above embodiments. The display panel can be applied to any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
The driving circuit of the display panel, the driving method of the display panel and the display panel provided by the embodiments of the disclosure belong to the same inventive concept, and the description of the relevant details and the beneficial effects can be referred to each other and are not repeated.
Although the present disclosure has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure.
Claims (12)
1. A driving circuit of a display panel, connected to a pixel circuit of the display panel, the driving circuit comprising:
the source driving chips can output a first data signal;
the time schedule controller can be in communication matching with the source driving chips according to a preset communication protocol and can output a matching signal according to a communication matching result;
the control circuit can receive the matching signal and a first data signal output by at least one source electrode driving chip and output a control signal to the pixel circuit according to the first data signal and the matching signal;
when the communication matching between the time schedule controller and the source electrode driving chips is successful, the time schedule controller outputs a first matching signal, the control circuit outputs the first data signal to the display panel according to the first data signal and the first matching signal, and the first data signal forms the control signal.
2. The driving circuit according to claim 1, wherein the pixel circuit is formed of P-type transistors, the timing controller outputs a second matching signal when the timing controller fails to communicate with at least one of the source driver chips, and the control circuit outputs a high-level control signal to the pixel circuit according to the first data signal and the second matching signal.
3. The driving circuit according to claim 1, wherein the pixel circuit is formed of N-type transistors, the timing controller outputs a second matching signal when the timing controller fails to communicate with at least one of the source driver chips, and the control circuit outputs a low-level control signal to the pixel circuit according to the first data signal and the second matching signal.
4. The driving circuit according to claim 1, wherein the number of the control circuits is plural, and the plural control circuits can receive the first data signals output by the plural source driver chips in a one-to-one correspondence.
5. The driving circuit according to claim 1, further comprising:
and the power supply management chip is connected with the source electrode driving chip and is used for sending the binding voltage signal of the gray scale to the source electrode driving chip.
6. The driving circuit according to claim 1, further comprising:
and the electroluminescent chip is connected with the pixel circuit and used for sending a driving power supply voltage signal and a low-level power supply voltage signal to the pixel circuit.
7. The driving circuit of claim 1, wherein the timing controller and the control circuit are disposed on a same circuit board.
8. The driving circuit of claim 7, wherein the circuit board is connected to the pixel circuit through a chip on film, and the chip on film is provided with the source driver chip.
9. The driving circuit of claim 1, wherein the display panel comprises a display area and a peripheral area surrounding the display area, and the source driving chip, the timing controller and the control circuit are all located in the peripheral area.
10. The driving circuit according to claim 1, wherein when the timing controller is successfully matched with the plurality of source driving chips, the timing controller outputs a second data signal to the source driving chips, and the source driving chips generate the first data signal according to the second data signal.
11. A display panel comprising the driver circuit according to any one of claims 1 to 10.
12. A driving method of a display panel, the driving method using the driving circuit according to any one of claims 1 to 10, the driving method comprising:
enabling a plurality of source driving chips to output first data signals;
enabling the time schedule controller to be in communication matching with the source electrode driving chips according to a preset communication protocol, and enabling the time schedule controller to output matching signals according to the result of the communication matching;
and enabling the control circuit to receive the matching signal and a first data signal output by at least one source electrode driving chip, and enabling the control circuit to output a control signal to the pixel circuit according to the first data signal and the matching signal.
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| WO2023221101A1 (en) * | 2022-05-20 | 2023-11-23 | 京东方科技集团股份有限公司 | Power supply circuit and drive method therefor, printed circuit board, and display module and apparatus |
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| KR102522805B1 (en) * | 2016-10-31 | 2023-04-20 | 엘지디스플레이 주식회사 | Display Device |
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| CN113707094A (en) | 2021-11-26 |
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