CN113704150B - DMA data cache consistency method, device and system in user mode - Google Patents
DMA data cache consistency method, device and system in user mode Download PDFInfo
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/28—DMA
- G06F2213/2806—Space or buffer allocation for DMA transfers
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention discloses a method, a device, a system and a computer readable storage medium for DMA data cache consistency under a user state, wherein the method comprises the following steps: determining a target memory according to the data storage completion notification sent by the DMA in the user mode; judging whether each cache has a target cache corresponding to the target memory, if so, acquiring data information in the target cache, and checking the data information; if the data information stored in the target memory does not exist, directly acquiring the data information stored in the target memory, and ending the operation; when the verification is successful, the data information in the target cache is consistent with the data information stored in the target memory, and the operation is ended; when the verification fails, the step of judging whether the target cache corresponding to the target memory exists in each cache is executed after the preset time is delayed until the target cache corresponding to the target memory does not exist or the verification is successful; the consistency of the data in the cache and the memory can be improved, and the system performance and the user experience are improved.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a method, an apparatus, a system, and a computer readable storage medium for DMA data cache consistency in a user state.
Background
DMA (Direct Memory Access ) may take over the bus to complete the data transfer, freeing the CPU (Central Processing Unit/Processor, central Processor) to allow the CPU to do other tasks. However, if the DMA cache is provided with a cache (cache memory) and the CPU is provided with a prefetch function, after the receiving end receives the data, the data in the cache and the data in the memory may be inconsistent, thereby causing data errors. Experiments prove that when the CPU Cache is larger and the automatic failure time of the Cache is longer, the probability of occurrence of the problem is larger.
When the CPU changes the data in a certain cache line, the data in the cache line is newer than the data in the corresponding memory, and this cache line needs to be marked as modified (updated) at this time, so that when necessary (for example, the cache line is full, the cache line needs to be released, and bits are vacated to the new cache line) the content flush in the cache line is synchronized to the memory. The operation of maintaining consistency by the cache can be divided into flush and invalidate, when DMA is used, data transmitted from a peripheral device (such as a network card) can be directly transmitted to the memory without passing through the CPU, and at this time, the data in the memory is newer than the data in the corresponding cache, and the cache line (marked as dirty) related to invalidation (invalidate) needs to be made, so that when the CPU reads the data in the cache line next time, the CPU can know that the data is not up to date and can be updated from the memory. In fact, a cache line is not valuable after being invalidized, and is equivalent to being emptied when the cache line is not available, so the cache line can be calculated as a flush.
However, there is no separate invalidate instruction in user state, because the invalidate instruction belongs to a privileged instruction, and there are only invalidate and Flush operations in user state, but this causes that when data in the invalidate related cache is needed, flush operations must be carried along, i.e. the data in the cache is flushed to the corresponding storage, thus contaminating the new data transferred from the DMA to the memory. Therefore, after the data transmitted from the peripheral (such as a network card) is directly transmitted to the memory, the data in the memory is newer than the data in the corresponding cache, and because the cache cannot be marked invalid in the user mode, the data read by the CPU from the cache corresponding to the memory is not the new data stored in the memory, resulting in data verification failure.
In view of this, how to provide a method, apparatus, system and computer readable storage medium for DMA data cache coherency in user mode is a problem to be solved by those skilled in the art.
Disclosure of Invention
The embodiment of the invention aims to provide a method, a device, a system and a computer readable storage medium for DMA data cache consistency in a user mode, which can improve the consistency of data in a cache and a memory in the use process, and are beneficial to improving the system performance and the user experience.
In order to solve the above technical problems, an embodiment of the present invention provides a method for DMA data cache consistency in a user state, including:
determining a target memory according to the data storage completion notification sent by the DMA in the user mode;
judging whether each cache has a target cache corresponding to the target memory, if so, acquiring data information in the target cache, and checking the data information; if not, directly acquiring the data information stored in the target memory, and ending the operation;
when the verification is successful, the data information in the target cache is consistent with the data information stored in the target memory, and the operation is ended;
and when the verification fails, after delaying the preset time, returning to execute the step of judging whether the target cache corresponding to the target memory exists in each cache or not until the target cache corresponding to the target memory does not exist or the verification is successful.
Optionally, after the verification fails, the method further includes:
and when no link layer error reporting and physical layer error reporting exist currently, executing the delay preset time, and then returning to execute the step of judging whether the target cache corresponding to the target memory exists in each cache.
Optionally, before returning to the step of determining whether the target cache corresponding to the target memory exists in each cache after the delay preset time length, the method further includes:
judging whether the number of times of the current continuous check failure reaches the preset number of times, if so, performing restarting operation by the control system, if not, executing the delay preset time, and then returning to execute the step of judging whether the target cache corresponding to the target memory exists in each cache.
Optionally, before the determining the target memory according to the data storage completion notification sent by the DMA in the user mode, the method further includes:
receiving original data information sent by a sending end through DMA (direct memory access) in a user mode; the sending end obtains the effective data with the target preset length from the beginning end of the effective data of the original data information, calculates a standard CRC value, and adds the CRC value to the end of the effective data to form the original data information; the original data information sent by two adjacent times is respectively corresponding to different target preset lengths;
sending the original data information to a memory for storage through the DMA, and generating a data storage completion notification;
the data information includes valid data and a standard CRC check value; the process for verifying the data information comprises the following steps:
starting from the effective data starting end of the data information, acquiring effective data of the target preset length, and calculating a current CRC value according to the effective data of the target preset length;
and comparing the current CRC check value with a standard CRC check value in the data information, if the current CRC check value is consistent with the standard CRC check value, checking successfully, and if the current CRC check value is inconsistent with the standard CRC check value, checking failure.
Optionally, the process of obtaining the valid data with the target preset length from the original data information by the sending end to calculate the standard CRC check value is:
the transmitting end selects a preset length different from the history target preset length from the first preset length and the second preset length as a target preset length corresponding to the original data information transmitted at present according to the history target preset length corresponding to the original data information transmitted at last; wherein, each time data information is sent, one preset length which is different from the last time is alternately selected from the first preset length and the second preset length to be used as a target preset length;
and acquiring the effective data of the target preset length from the effective data initial end of the original data information, and calculating a standard CRC value according to the effective data of the target preset length.
The embodiment of the invention also provides a DMA data cache consistency device in the user mode, which comprises:
the determining module is used for determining a target memory according to the data storage completion notification sent by the DMA under the user state;
the judging module is used for judging whether the target cache corresponding to the target memory exists in each cache or not, and if so, the verification module is triggered; if not, triggering an acquisition module;
the verification module is used for acquiring the data information in the target cache and verifying the data information;
the acquisition module is used for directly acquiring the data information stored in the target memory and ending the operation;
the ending module is used for ending the operation when the verification is successful, wherein the data information in the target cache is consistent with the data information stored in the target memory;
and the return module is used for triggering the judging module after delaying the preset time when the verification fails.
Optionally, the return module is specifically configured to trigger the judging module after delaying for a preset duration when there is no link layer error reporting and no physical layer error reporting currently.
Optionally, the method further comprises:
the receiving module is used for receiving the original data information sent by the sending end through the DMA under the user mode; the sending end obtains the effective data with the target preset length from the beginning end of the effective data of the original data information, calculates a standard CRC value, and adds the CRC value to the end of the effective data to form the original data information; the original data information sent by two adjacent times is respectively corresponding to different target preset lengths;
the sending module is used for sending the original data information to a memory for storage through the DMA and generating a data storage completion notification;
the data information includes valid data and a standard CRC check value; the verification module comprises:
the acquisition unit is used for acquiring the effective data of the target preset length from the effective data starting end of the data information, and calculating a current CRC value according to the effective data of the target preset length;
and the comparison unit is used for comparing the current CRC check value with a standard CRC check value in the data information, triggering the ending module if the current CRC check value is consistent with the standard CRC check value, and triggering the returning module if the current CRC check value is inconsistent with the standard CRC check value.
The embodiment of the invention also provides a DMA data cache consistency system under the user mode, which comprises the following steps:
a memory for storing a computer program;
and the processor is used for realizing the steps of the DMA data cache consistency method in the user mode when executing the computer program.
The embodiment of the invention also provides a computer readable storage medium, wherein the computer readable storage medium is stored with a computer program, and the computer program realizes the steps of the DMA data cache consistency method under the user state when being executed by a processor.
The embodiment of the invention provides a method, a device, a system and a computer-readable storage medium for DMA data cache consistency in a user state, wherein the method comprises the following steps: determining a target memory according to the data storage completion notification sent by the DMA in the user mode; judging whether each cache has a target cache corresponding to the target memory, if so, acquiring data information in the target cache, and checking the data information; if the data information stored in the target memory does not exist, directly acquiring the data information stored in the target memory, and ending the operation; when the verification is successful, the data information in the target cache is consistent with the data information stored in the target memory, and the operation is ended; and when the verification fails, the step of judging whether the target cache corresponding to the target memory exists in each cache is executed after the delay of the preset time period until the target cache corresponding to the target memory does not exist or the verification is successful.
It can be seen that, in the embodiment of the present invention, a target memory is determined according to a data storage completion notification sent by a DMA in a user state, then it is determined whether a cache corresponding to the target memory exists in each cache, if no corresponding target cache exists, it is indicated that the CPU has not yet brushed the data information stored in the target memory into the cache, then the stored data information is directly obtained from the target memory, if the corresponding target cache exists, the data information in the target cache is obtained from the corresponding target cache, and the data information is checked, if the check is successful, it is indicated that the data information cached in the target cache is consistent with the data information stored in the target memory, and if the check is unsuccessful, the data acquisition is finished, and if the check is unsuccessful, then it is continued to determine whether the target cache consistent with the target memory exists in each cache until the target cache corresponding to the target memory does not exist or the check is successful, and the operation is finished; the delay preset time is favorable for the CPU to utilize the time to brush the data information in the target memory into the cache so as to keep the cache consistent with the data in the memory; the invention can improve the consistency of the data in the cache and the memory, and is beneficial to improving the system performance and improving the user experience.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the prior art and the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for DMA data cache consistency in user mode according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a DMA data cache consistency device in a user mode according to an embodiment of the present invention.
Detailed Description
The embodiment of the invention provides a method, a device, a system and a computer readable storage medium for DMA data cache consistency in a user mode, which can improve the consistency of data in a cache and a memory in the use process, and is beneficial to improving the system performance and the user experience.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, fig. 1 is a flowchart of a method for DMA data cache consistency in a user mode according to an embodiment of the present invention. The method comprises the following steps:
s110: determining a target memory according to the data storage completion notification sent by the DMA in the user mode;
it should be noted that, in the embodiment of the present invention, when the DMA is used in a user mode and the DMA is used to implement DMA data transfer between devices through the network card, the DMA directly stores the transferred data into the memory, and after the DMA sends the data information to the memory to complete the storage, a data storage completion notification is generated, and after the data storage completion notification sent by the DMA is received, the target memory is determined according to the data storage completion notification, and in particular, the corresponding target memory may be determined according to the memory identifier code carried in the data storage completion notification.
S120: judging whether target caches corresponding to the target memory exist in each cache, and if so, entering S130; if not, then enter S160;
s130: acquiring data information in a target cache, and checking the data information;
specifically, when a target cache corresponding to a target memory exists in the cache, data information is acquired from the target cache, and is checked, so that whether the data information is successfully checked is judged.
S140: when the verification is successful, the data information in the target cache is consistent with the data information stored in the target memory, and the operation is ended;
specifically, when the verification is successful, it is indicated that the data information stored in the target cache is consistent with the data information stored in the target memory, and the acquired data confidence is correct data information at this time, so that the operation is finished.
S150: when the verification fails, the step of judging whether the target cache corresponding to the target memory exists in each cache is executed after the preset time is delayed until the target cache corresponding to the target memory does not exist or the verification is successful;
specifically, if the verification of the data information obtained from the target cache fails, it indicates that the data information is inconsistent with the data information stored in the target memory, at this time, the step of judging whether the target cache corresponding to the target memory exists in each cache may be executed after a preset period of time, and when the target cache corresponding to the target memory exists, the data information of the target cache is read again, and the data information is verified until the target cache consistent with the target memory does not exist in each cache or the data verification fails. Specifically, when there is no link layer error reporting and no physical layer error reporting, the step of executing the target buffer memory corresponding to the target memory in each buffer memory is returned to be executed after the delay preset time is executed. That is, when there is no link layer error reporting and physical layer error reporting at present and verification fails, it is indicated that the data information obtained from the target cache is not the data information newly stored in the target memory, and the problem of inconsistent cache data occurs.
It should be noted that, because the mechanism of the CPU itself is to continuously refresh the data information in the memory into the cache corresponding to the memory, when there is new data stored in the memory and the CPU has not refreshed the new data from the memory into the corresponding cache, the data information obtained from the cache is old data information, and since the data information in the memory is inconsistent with the data information in the cache, the verification of the data information fails, but since the CPU continuously refreshes the data in the memory into the corresponding cache, the invention sets a mechanism of delaying reading, that is, after the verification fails, the step of delaying the preset time to trigger again to determine whether there is a target cache corresponding to the target memory in each cache, and reading the data information in the target cache when there is a target cache, if there is always storing the target cache corresponding to the target memory, after the CPU refreshes the data information in the target memory into the target cache, the data information read from the target cache in a certain round will succeed in verification, that is correct data information obtained. In addition, according to the mechanism of the CPU itself, since the overall size of the cache is far smaller than the overall size of the memory, after data is stored in a certain memory, the CPU finds the cache corresponding to the memory from the cache and then refreshes the data into the cache, but when the cache does not exist in the cache corresponding to the memory, the CPU can directly obtain the corresponding data information from the memory, and the CPU also finds an idle cache from each cache or when there is no idle cache, needs to establish a mapping relationship between the first used cache and the memory from the first cache, and refreshes the data in the memory into the cache to cover the old data originally stored in the cache.
S160: and directly acquiring the data information stored in the target memory, and ending the operation.
It should be noted that, in the embodiment of the present invention, when it is determined that the target cache corresponding to the target memory does not exist in each cache, the stored data information may be directly obtained from the target memory.
Further, when the IOPS requirement on the data is higher, before the step of determining whether the target cache corresponding to the target memory exists in each cache may be performed after the delay preset time period, the method may further include:
judging whether the current continuous check failure times reach the preset times, if so, performing restarting operation by the control system, if not, executing the step of delaying the preset time and then returning to execute the step of judging whether the target cache corresponding to the target memory exists in each cache. Further, before determining the target memory according to the data storage completion notification sent by the DMA in the user mode, the method may further include:
receiving original data information sent by a sending end through DMA (direct memory access) in a user mode; the method comprises the steps that a sending end obtains valid data with target preset length from a starting end of valid data of original data information to calculate a standard CRC check value, and the CRC check value is added to the tail end of the valid data to form the original data information, wherein the target preset lengths corresponding to the original data information sent twice adjacently are different;
sending the original data information to a memory for storage through DMA, and generating a data storage completion notification;
it should be noted that, in the user state, the transmitting end sends the transmitted original data information to the memory for storage through the DMA, where the original data information includes valid data and a standard CRC check value, where the transmitting end obtains valid data with a target preset length from the starting end of the valid data to calculate the standard CRC check value, and then adds the standard CRC check value to the end of the valid data to form the original data information. The target preset length corresponding to the original data information sent at the sending end at the next time is different from the target preset length corresponding to the original data information sent at the current time, and the target preset length corresponding to the original data information sent at the current time is also different from the target preset length corresponding to the original data information sent at the next time.
Correspondingly, the data information comprises valid data and a standard CRC check value; the process of verifying the data information may specifically be:
starting from the effective data starting end of the data information, acquiring effective data with a target preset length, and calculating a current CRC value according to the effective data with the target preset length;
and comparing the current CRC check value with a standard CRC check value in the data information, if the current CRC check value is consistent with the standard CRC check value, checking successfully, and if the current CRC check value is inconsistent with the standard CRC check value, checking failed.
Specifically, data information is obtained from a target cache, valid data with the target preset length is obtained from a valid data starting end in the data information, a current CRC check value is calculated according to the valid data with the target preset length, then the current CRC check value is compared with a standard CRC check value in the obtained data information, if the current CRC check value and the standard CRC check value are consistent, the data information in the target cache is consistent with the data information stored in a target memory, and if the data information in the target cache and the data information stored in the target memory are inconsistent, the data information in the target cache and the data information stored in the target memory are inconsistent.
It should be noted that, when the transmitting end transmits the original data information, the target preset lengths corresponding to the original data information transmitted by two adjacent times are different, so after the original data information transmitted currently is transmitted to the target memory through the DMA for storage, if the CPU has not yet reached the refreshing of the data information stored in the target memory, the data information stored in the target memory still is the data information transmitted to the target memory last time, for example, the target preset length adopted last time is different from the target preset length adopted last time, for example, 30 is adopted last time, and 60 is adopted this time, namely, the standard CRC check value in the data information cached in the target cache is calculated by using the effective data of the target preset length 30, so after the data information is acquired from the target cache, the current CRC check value calculated by using the target preset length of this time is inconsistent with the standard CRC check value in the data information, thereby proving that the data information in the target cache is inconsistent with the data information in the target memory, and if the CPU delays the target preset time period and the data information in the target cache segment is read again, for example, the standard CRC check value is calculated from the target cache information after the target information is acquired from the target cache information, and the target information is read again, and the standard CRC value is found to be consistent with the target information.
Furthermore, the process of obtaining the valid data with the target preset length from the original data information by the transmitting end to calculate the standard CRC check value may specifically be:
the transmitting end selects a preset length different from the history target preset length from the first preset length and the second preset length as a target preset length corresponding to the original data information transmitted at present according to the history target preset length corresponding to the original data information transmitted at last; wherein, each time data information is sent, one preset length which is different from the last time is alternately selected from the first preset length and the second preset length to be used as a target preset length;
and acquiring the effective data with the target preset length from the effective data initial end of the original data information, and calculating a standard CRC value according to the effective data with the target preset length.
It should be noted that, in the embodiment of the present invention, the first preset length and the second preset length may be preset, and when the transmitting end is controlled to transmit the data information each time, the first preset length and the second preset length are alternately used as the target preset length, so that it may be ensured that the target preset lengths corresponding to the data information transmitted in two adjacent times are different. Correspondingly, after the data information is obtained from the target cache, the first preset length and the second preset length are alternately used as target preset lengths, wherein the target preset length adopted in the process is the same as the target preset length of the data information sent by the sending end, the current corresponding target preset length (for example, the first preset length and the current second preset length) can be automatically determined according to the rule that the first preset length and the second preset length are alternately performed when the data storage completion notification is received each time, and the current corresponding target preset length (for example, the first preset length and the current second preset length) is switched to another preset length (for example, the next first preset length) until the data storage completion notification is received next time.
It can be seen that, in the embodiment of the present invention, a target memory is determined according to a data storage completion notification sent by a DMA in a user state, then it is determined whether a cache corresponding to the target memory exists in each cache, if no corresponding target cache exists, it is indicated that the CPU has not yet brushed the data information stored in the target memory into the cache, then the stored data information is directly obtained from the target memory, if the corresponding target cache exists, the data information in the target cache is obtained from the corresponding target cache, and the data information is checked, if the check is successful, it is indicated that the data information cached in the target cache is consistent with the data information stored in the target memory, and if the check is unsuccessful, the data acquisition is finished, and if the check is unsuccessful, then it is continued to determine whether the target cache consistent with the target memory exists in each cache until the target cache corresponding to the target memory does not exist or the check is successful, and the operation is finished; the delay preset time is favorable for the CPU to utilize the time to brush the data information in the target memory into the cache so as to keep the cache consistent with the data in the memory; the invention can improve the consistency of the data in the cache and the memory, and is beneficial to improving the system performance and improving the user experience.
Based on the above embodiments, the embodiment of the present invention further provides a DMA data cache consistency device in a user state, and refer to fig. 2 specifically. The device comprises:
a determining module 21, configured to determine a target memory according to the data storage completion notification sent by the DMA in the user state;
the judging module 22 is configured to judge whether a target cache corresponding to the target memory exists in each cache, and if so, trigger the verifying module 23; if not, triggering the acquisition module 24;
the verification module 23 is configured to obtain data information in the target cache, and verify the data information;
the obtaining module 24 is configured to directly obtain the data information stored in the target memory, and end the operation;
an ending module 25, configured to, when the verification is successful, make the data information in the target cache consistent with the data information stored in the target memory, and end the operation;
and a return module 26, configured to trigger the judging module 22 after delaying for a preset period of time when the verification fails.
Optionally, the return module 26 is specifically configured to trigger the judging module after delaying for a preset period of time when there is no link layer error reporting and no physical layer error reporting currently.
Optionally, the apparatus further comprises:
the receiving module is used for receiving the original data information sent by the sending end through the DMA under the user mode; the method comprises the steps that a sending end obtains valid data with a preset target length from a starting end of valid data of original data information to calculate a standard CRC check value, and the CRC check value is added to the end of the valid data to form the original data information; the original data information sent by two adjacent times is respectively corresponding to different target preset lengths;
the sending module is used for sending the original data information to the memory for storage through DMA and generating a data storage completion notification;
then the data information includes valid data and a standard CRC check value; the verification module 23 includes:
the acquisition unit is used for acquiring the effective data of the target preset length from the effective data starting end of the data information, and calculating the current CRC value according to the effective data of the target preset length;
and the comparison unit is used for comparing the current CRC check value with the standard CRC check value in the data information, triggering the ending module if the current CRC check value is consistent with the standard CRC check value, and triggering the returning module if the current CRC check value is inconsistent with the standard CRC check value.
It should be noted that, the user-state DMA data cache coherency apparatus provided in the embodiment of the present invention has the same advantages as the user-state DMA data cache coherency method provided in the above embodiment, and reference is made to the above embodiment for specific description of the user-state DMA data cache coherency method related to the embodiment of the present invention, which is not repeated herein.
On the basis of the above embodiment, the embodiment of the present invention further provides a DMA data cache coherence system in a user mode, where the system includes:
a memory for storing a computer program;
and the processor is used for realizing the steps of the DMA data cache consistency method under the user mode when executing the computer program.
For example, the processor in the embodiment of the present invention may be specifically configured to determine the target memory according to the data storage completion notification sent by the DMA in the user state; judging whether each cache has a target cache corresponding to the target memory, if so, acquiring data information in the target cache, and checking the data information; if the data information stored in the target memory does not exist, directly acquiring the data information stored in the target memory, and ending the operation; when the verification is successful, the data information in the target cache is consistent with the data information stored in the target memory, and the operation is ended; and when the verification fails, the step of judging whether the target cache corresponding to the target memory exists in each cache is executed after the delay of the preset time period until the target cache corresponding to the target memory does not exist or the verification is successful.
On the basis of the above embodiment, the embodiment of the present invention further provides a computer readable storage medium, where a computer program is stored, where the computer program, when executed by a processor, implements the steps of the DMA data cache consistency method in the user mode described above.
The computer readable storage medium may include: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (7)
1. The DMA data cache consistency method in the user mode is characterized by comprising the following steps:
determining a target memory according to the data storage completion notification sent by the DMA in the user mode;
judging whether each cache has a target cache corresponding to the target memory, if so, acquiring data information in the target cache, and checking the data information; if not, directly acquiring the data information stored in the target memory, and ending the operation;
when the verification is successful, the data information in the target cache is consistent with the data information stored in the target memory, and the operation is ended;
when the verification fails, the step of judging whether the target cache corresponding to the target memory exists in each cache is executed after delaying the preset time until the target cache corresponding to the target memory does not exist or the verification is successful; wherein:
before the target memory is determined according to the data storage completion notification sent by the DMA in the user mode, the method further comprises the following steps:
receiving original data information sent by a sending end through DMA (direct memory access) in a user mode; the sending end obtains the effective data with the target preset length from the beginning end of the effective data of the original data information, calculates a standard CRC value, and adds the CRC value to the end of the effective data to form the original data information; wherein the target preset lengths respectively corresponding to the original data information sent by two adjacent times are different
Sending the original data information to a memory for storage through the DMA, and generating a data storage completion notification;
the data information includes valid data and a standard CRC check value; the process for verifying the data information comprises the following steps:
starting from the effective data starting end of the data information, acquiring effective data of the target preset length, and calculating a current CRC value according to the effective data of the target preset length;
comparing the current CRC value with a standard CRC value in the data information, if the current CRC value is consistent with the standard CRC value, checking successfully, and if the current CRC value is inconsistent with the standard CRC value, checking failed; wherein:
the process of the sending end obtaining the effective data with the target preset length from the original data information to calculate the standard CRC value is as follows:
the transmitting end selects a preset length different from the history target preset length from the first preset length and the second preset length as a target preset length corresponding to the original data information transmitted at present according to the history target preset length corresponding to the original data information transmitted at last; wherein, each time data information is sent, one preset length which is different from the last time is alternately selected from the first preset length and the second preset length to be used as a target preset length;
and acquiring the effective data of the target preset length from the effective data initial end of the original data information, and calculating a standard CRC value according to the effective data of the target preset length.
2. The method for DMA data cache coherence in a user mode according to claim 1, further comprising, after a verification failure:
and when no link layer error reporting and physical layer error reporting exist currently, executing the delay preset time, and then returning to execute the step of judging whether the target cache corresponding to the target memory exists in each cache.
3. The method for DMA data cache coherence in a user mode according to claim 1 or 2, wherein before returning to the step of determining whether a target cache corresponding to the target memory exists in each cache after the delay preset time period, the method further comprises:
judging whether the number of times of the current continuous check failure reaches the preset number of times, if so, performing restarting operation by the control system, if not, executing the delay preset time, and then returning to execute the step of judging whether the target cache corresponding to the target memory exists in each cache.
4. A DMA data cache coherence apparatus in a user mode, comprising:
the determining module is used for determining a target memory according to the data storage completion notification sent by the DMA under the user state;
the judging module is used for judging whether the target cache corresponding to the target memory exists in each cache or not, and if so, the verification module is triggered; if not, triggering an acquisition module;
the verification module is used for acquiring the data information in the target cache and verifying the data information;
the acquisition module is used for directly acquiring the data information stored in the target memory and ending the operation;
the ending module is used for ending the operation when the data information in the target cache is consistent with the data information stored in the target memory when the verification is successful;
the return module is used for triggering the judging module after delaying the preset time length when the verification fails; wherein:
further comprises:
the receiving module is used for receiving the original data information sent by the sending end through the DMA under the user mode; the sending end obtains the effective data with the target preset length from the beginning end of the effective data of the original data information, calculates a standard CRC value, and adds the CRC value to the end of the effective data to form the original data information; the original data information sent by two adjacent times is respectively corresponding to different target preset lengths;
the sending module is used for sending the original data information to a memory for storage through the DMA and generating a data storage completion notification;
the data information includes valid data and a standard CRC check value; the verification module comprises:
the acquisition unit is used for acquiring the effective data of the target preset length from the effective data starting end of the data information, and calculating a current CRC value according to the effective data of the target preset length;
the comparison unit is used for comparing the current CRC check value with a standard CRC check value in the data information, triggering the ending module if the current CRC check value is consistent with the standard CRC check value, and triggering the returning module if the current CRC check value is inconsistent with the standard CRC check value; wherein:
the process of the sending end obtaining the effective data with the target preset length from the original data information to calculate the standard CRC value is as follows:
the transmitting end selects a preset length different from the history target preset length from the first preset length and the second preset length as a target preset length corresponding to the original data information transmitted at present according to the history target preset length corresponding to the original data information transmitted at last; wherein, each time data information is sent, one preset length which is different from the last time is alternately selected from the first preset length and the second preset length to be used as a target preset length;
and acquiring the effective data of the target preset length from the effective data initial end of the original data information, and calculating a standard CRC value according to the effective data of the target preset length.
5. The apparatus for DMA data cache coherence in a user mode according to claim 4, wherein the return module is specifically configured to trigger the determining module after a delay for a preset period of time when there is no link layer error reporting and no physical layer error reporting currently.
6. A DMA data cache coherence system in a user mode, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the DMA data cache coherence method in a user state according to any of claims 1 to 3 when executing said computer program.
7. A computer readable storage medium, characterized in that it has stored thereon a computer program which, when executed by a processor, implements the steps of the DMA data cache coherence method in a user mode according to any of claims 1 to 3.
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| CN103186492A (en) * | 2011-12-28 | 2013-07-03 | 联芯科技有限公司 | AXI (Advanced Extensible Interface) bus-based data consistency protection method and system |
| CN111176885A (en) * | 2019-12-31 | 2020-05-19 | 浪潮电子信息产业股份有限公司 | Data verification method and related device for distributed storage system |
| CN112256604A (en) * | 2020-10-19 | 2021-01-22 | 海光信息技术股份有限公司 | Direct memory access system and method |
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| CN103186492A (en) * | 2011-12-28 | 2013-07-03 | 联芯科技有限公司 | AXI (Advanced Extensible Interface) bus-based data consistency protection method and system |
| CN111176885A (en) * | 2019-12-31 | 2020-05-19 | 浪潮电子信息产业股份有限公司 | Data verification method and related device for distributed storage system |
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