CN113702676A - Broadband arbitrary waveform generation device and method based on CML interface - Google Patents
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Abstract
The invention discloses a CML interface-based broadband arbitrary waveform generation device and method, and belongs to the field of arbitrary waveform generation. According to the invention, a mode of combining a CML interface with a detection pseudo-random sequence error rate is adopted to replace a JESD204B interface, the data bandwidth with the same channel number is improved by 20%, the channel number is expandable, and the data bandwidth is further improved; the negative feedback loop is formed by adopting the modes of common mode level acquisition, median filtering, accumulation and subtraction operation, so that the common mode level output by the DAC is effectively eliminated, and the device is simple in structure and easy to realize; the data bandwidth is effectively improved, any waveform signal with a higher sampling rate can be generated, the common mode level is eliminated, and the fidelity of any waveform signal is improved.
Description
Technical Field
The invention belongs to the field of arbitrary waveform generation, and particularly relates to a broadband arbitrary waveform generation device and method based on a CML interface.
Background
The broadband arbitrary waveform generation technology is a signal generation technology based on digital, analog and computer technologies, and is widely applied to the fields of radar, satellite communication, electronic countermeasure, radio frequency test, integrated circuit test and the like. The broadband arbitrary waveform generating device taking the technology as the core has the advantages of high output frequency stability and resolution, high frequency switching speed, continuous output waveform phase during switching and the like, and the rich signal excitation capability of the broadband arbitrary waveform generating device comprises a high-speed waveform generator, a function generator, a pulse/sequence generator, a sweep generator, a trigger generator, a broadband white noise signal generator, an amplitude modulation source and the like. Meanwhile, the device has a sequence address control function, and can generate digital modulation signals, simulate various complex signals, even defects in the signals, transient signals and the like. With the development of electronic technology, the broadband arbitrary waveform generating device can play an important role in a variety of applications such as broadband communication, radar systems, high-speed pulse simulation, high-speed digital design, field environment simulation and playback, and the like.
At present, an FPGA and a DAC chip are adopted in a mainstream broadband arbitrary waveform generation scheme, N paths of waveform data in the FPGA are interconnected with the DAC chip through a JESD204B interface, the JESD204B interface is in a general interface mode, 8B/10B coding is adopted, 20% of data bandwidth can be lost, and the JESD204B interface is specified to adopt 8 channels for data transmission, so that channel expansion cannot be carried out at will, and the data bandwidth is limited. In order to increase the output speed of the broadband DAC, an output interface can have a common-mode level, the simplest conventional solution is to adopt a capacitor for blocking direct current and losing a direct current level, or adopt an external instrument for detecting the common-mode level, then design a complex bias control circuit, and move a positive power rail and a negative power rail by using a direct current DAC chip, so that the circuit design difficulty is high, and the reliability is reduced.
The JESD204B interface adopts 8B/10B coding, which can lose 20% of data bandwidth, and the technology adopts a CML interface pseudorandom sequence scrambling mode, which has no loss of data bandwidth. The JESD204B interface adopts 8 channel data transmission, cannot randomly expand channels and limit data bandwidth, the number of channels of the technology can be randomly expanded, the number of the channels is far more than 8, each channel can carry out error code test, the transmission reliability is ensured, and the data bandwidth is effectively improved. The broadband output interface can have a common-mode level, the conventional solution adopts a capacitor to isolate direct current and can lose direct current level, or a complex bias control circuit is adopted to move positive and negative power rails, the circuit design difficulty is high, the cost is high, and the reliability is reduced. The technology can firstly obtain the common mode level without depending on an external instrument, integrates the bias detection circuit, adjusts the waveform data in the FPGA according to the common mode level, adopts the FPGA software method to eliminate the common mode level, and has simple circuit structure and good effect.
Disclosure of Invention
Aiming at the technical problems in the prior art, the invention provides a device and a method for generating any broadband waveform based on a CML (Current Mode Logic) interface, which have reasonable design, overcome the defects of the prior art and have good effect.
In order to achieve the purpose, the invention adopts the following technical scheme:
a broadband arbitrary waveform generating device based on a CML interface comprises an extraction module, a subtraction module, a CML interface module, a DAC chip, a median filtering module, a direct current ADC module and an analog channel;
the extraction module is configured to be used for sequentially extracting the waveform data into N branches;
a subtractor module configured for subtraction of the bias factor and the waveform data;
the CML interface module is configured to be used for transmitting the N paths of waveform data of the FPGA to the DAC chip;
the median filtering module is configured to sort the N numerical values of the bias information in an ascending order every time, take median data, accumulate the data and generate a bias factor;
a DC ADC module integrated with a low pass filter and a DC acquisition circuit configured to acquire a common mode level of the circuit;
an analog channel configured to implement analog signal conditioning functions of filtering, attenuation, and amplification.
Preferably, the decimation module comprises an FPGA.
Preferably, the CML interface module includes an exclusive or module, an N-way pseudo random sequence generation module, and a timer;
an exclusive-or module configured for exclusive-or operation of the pseudo-random sequence and the waveform data;
the N-path pseudo-random sequence generation module is configured to be used for generating N-path pseudo-random sequences according to the bit error rate detected by the N-path DAC chips;
and the DAC chip is configured to be used for integrating the CML interface and the N-way error code detection module.
Preferably, the N-path pseudo-random sequence generation module comprises a pseudo-random sequence generation module, a 1-divided-into-N-path module and an N-path FIFO module;
a pseudo-random sequence generation module configured to generate a pseudo-accompanying source sequence, the module being generated by using N stages of shift registers and comprising 2N1 states, the initial sequence order being set to the median of all states
And the 1-N-path module is configured to copy the output sequence of the pseudo-random sequence generation module into N paths of data.
An N-way FIFO module configured to set a sequence order of the pseudo-random sequence, the set length range being 0-2N-1。
Preferably, in the stage of establishing reliable transmission, the N-way FIFO module moves the sequence order of the corresponding channel according to the bit error rate obtained by reading the DAC chip until the bit error rate is 0; sequentially setting the sequence order of the N paths of pseudo-random sequences until the error rates of all channels are 0; in the waveform generation stage, under the drive of a timer, when a DAC chip detects that the error rate of a certain channel is not 0, the module can adjust the sequence of a corresponding path until the error rate is 0;
in addition, the present invention also provides a method for generating a wideband arbitrary waveform based on a CML interface, which uses the above-mentioned wideband arbitrary waveform generating apparatus based on a CML interface, and specifically includes the following steps:
step 1: a reliable transmission establishing stage; the method specifically comprises the following steps:
step 1.1: powering on, entering a CML interface to establish reliable transmission;
step 1.2: waveform data and bias factor are set to 0;
step 1.3: setting an initial sequence by the N paths of pseudo-random sequences, wherein the N paths of pseudo-random sequences generate the same pseudo-random sequence;
step 1.4: the N paths of pseudo-random sequences and the waveform data are subjected to exclusive OR and then transmitted to a DAC chip through a CML interface;
step 1.5: the DAC chip tests the bit error rate of N paths of data by using the same pseudo-random sequence and feeds the bit error rate back to a pseudo-random sequence generation module of the FPGA;
step 1.6: the pseudo-random sequence generation module moves the data sequence of the pseudo-random sequence according to the error rate and judges whether a channel M with the error rate not being 0 exists or not;
if: if the judgment result is that the channel M with the bit error rate not being 0 exists, executing the step 1.7;
or if the judgment result shows that the channel M with the error rate not being 0 does not exist, namely the error rate is 0 when the DAC chip tests, and the error rates of the N paths of data are all 0, the CML interface establishes reliable transmission; entering the step 2;
step 1.7: adjusting the order of the M channel pseudo-random sequences;
step 2: an offset calibration stage; the method specifically comprises the following steps:
step 2.1: the direct current ADC module acquires a common mode level output by the DAC chip and sends an acquired value to the FPGA;
step 2.2: the FPGA carries out median filtering on the acquired value, filters an interference signal, the value enters an accumulator to obtain a bias factor, and the bias factor is subtracted from the waveform data to form a negative feedback loop;
step 2.3: judging whether the common mode level acquired by the direct current ADC module is 0 or not;
if: if the judgment result is that the common mode level collected by the direct current ADC module is not 0, executing the step 2.1;
or if the judgment result is that the common mode level acquired by the direct current ADC module is 0, the bias calibration stage is finished, and the step 3 is entered;
and step 3: a normal waveform output stage; the method specifically comprises the following steps:
step 3.1: the waveform data is user waveform data, the waveform data is subtracted from the offset factor obtained in the offset calibration stage, and then the subtracted waveform data is subjected to exclusive or with the N-path pseudo-random sequence obtained in the reliable transmission establishment stage;
step 3.2: the data after the exclusive or in the step 3.1 is transmitted to a DAC chip through a CML interface for digital-to-analog conversion, and the converted data is output after low-pass filtering, attenuation and amplification through an analog channel;
and 4, step 4: detecting N paths of data error rates at fixed time, and judging whether a channel M with the error rate not being 0 exists or not;
if: if the judgment result is that the channel M with the bit error rate not being 0 exists, executing the step 1.7;
or judging that the channel M with the bit error rate not being 0 does not exist, and ending.
Preferably, the bias factor generation method is as follows: the data collected by the direct current ADC module is sorted from small to large according to a bubble sorting method, then, a median value is taken as a value of a common mode level, the value enters an accumulator to be added, an initial value of the accumulator is set as a theoretical calculation value P, and a calculation formula is as follows:
P＝K×I；
k is the load impedance of the broadband DAC chip, I is the common-mode current of the broadband DAC chip and is provided by a DAC chip manual; the output of the accumulator is an offset factor used for subtracting the waveform data, the circuit structure forms a convergent negative feedback structure, when the offset is increased, the offset factor is increased, the offset of the waveform data output is reduced, when the offset is reduced, the offset factor is reduced, the offset change rate of the waveform data output is reduced, and finally the output offset is automatically adjusted to 0.
Preferably, K takes 50 ohms.
The invention has the following beneficial technical effects:
1. the method adopts a CML interface combined with a mode of detecting the error rate of the pseudorandom sequence to replace a JESD204B interface, improves the data bandwidth by 20% with the same channel number, can expand the channel number, and further improves the data bandwidth.
2. The negative feedback loop is formed by adopting the modes of common mode level acquisition, median filtering, accumulation and subtraction operation, the common mode level output by the DAC is effectively eliminated, and the device is simple in structure and easy to realize.
3. The data bandwidth is effectively improved, any waveform signal with a higher sampling rate can be generated, the common mode level is eliminated, and the fidelity of any waveform signal is improved.
Drawings
Fig. 1 is a schematic block diagram of a broadband arbitrary waveform generating device based on a CML interface.
Fig. 2 is an overall work flow diagram.
FIG. 3 is a block diagram of the generation of N pseudo-random sequences.
Fig. 4 is a block diagram of bias factor generation.
Detailed Description
The invention is described in further detail below with reference to the following figures and detailed description:
the CML interface-based broadband arbitrary waveform generating device mainly comprises an extraction module, a subtraction module, a CML interface module, a DAC chip, a median filtering module, a direct current ADC module and an analog channel, wherein the CML interface module comprises an exclusive OR module, an N-path pseudo-random sequence generating module and a timer. The principle is shown in fig. 1. The extraction module is used for sequentially extracting the waveform data into N branches. The subtractor module is used for subtracting the bias factor and the waveform data. And the CML interface module is used for transmitting the N paths of waveform data of the FPGA to the DAC chip. And the exclusive OR module is used for exclusive OR operation of the pseudo-random sequence and the waveform data. And the N-path pseudo-random sequence generation module generates N-path pseudo-random sequences according to the error rate detected by the N-path DAC chips. And the DAC chip integrates a CML interface and an N-path error code detection module. The median filtering module sorts N values of the bias information in ascending order every time, takes median data and accumulates the data for generating the bias factors. The direct current ADC module integrates a low-pass filtering circuit and a direct current acquisition circuit and is used for acquiring the common mode level of the circuit. The analog channel is used for realizing the analog signal conditioning functions of filtering, attenuation and amplification.
The overall workflow is shown in fig. 2. After the power-on starts, firstly, a CML interface is entered to establish a reliable transmission stage, waveform data and a bias factor are set to be 0, N paths of pseudo-random sequences generate the same pseudo-random sequence, such as a PRBS9 sequence, the pseudo-random sequence and the waveform data are transmitted to a DAC chip through the CML interface after being subjected to exclusive OR, and the DAC chip uses the same pseudo-random sequence to test the error rate of N paths of data and feeds the error rate back to a pseudo-random sequence generation module of the FPGA. And the pseudo-random sequence generation module moves the data sequence of the pseudo-random sequence according to the error rate until the DAC chip tests that the error rate is 0. And when the error rates of the N paths of data are all 0, the CML interface establishes reliable transmission. And then, carrying out an offset calibration stage, wherein the DC ADC acquires the common mode level output by the DAC, the acquired value is sent to the FPGA, the FPGA carries out median filtering on the acquired value, interference signals are filtered, the value enters an accumulator to obtain an offset factor, the offset factor is subtracted from the waveform data to form a negative feedback loop, and when the common mode level acquired by the DC ADC and the value of 0 are smaller than the minimum offset error, the offset calibration stage is completed. And finally, normal waveform generation is carried out, the waveform data is user waveform data, the waveform data is subtracted from the offset factor obtained in the offset calibration stage, then the exclusive OR is carried out on the waveform data and the N-path pseudo-random sequence obtained in the reliable transmission establishment stage, the result is transmitted to a DAC chip through a CML interface to carry out digital-to-analog conversion, and the converted data is output after low-pass filtering, attenuation and amplification are carried out through an analog channel. The device regularly detects N paths of data error rates after a normal waveform generation stage, when the error rate of one path is higher, the device enters a CML interface to establish a reliable transmission stage, and adjusts the data sequence of a pseudo-random sequence of the path with the higher error rate until the error rate of the path is 0. Then, normal waveform generation is resumed.
The internal structure of the N-way pseudo-random sequence generation module is shown in fig. 3. The N-path pseudo-random sequence generation module mainly comprises a pseudo-random sequence generation module, a 1-path N-path module and an N-path FIFO module, wherein the N-path pseudo-random sequences are homologous sequences and are generated by the pseudo-random sequence generation module which adopts an N-level shift register to generate and totally comprises 2N1 states, the initial sequence order being set to the median of all states
The sequence order of the pseudo-random sequence of each path can be set through the FIFO module, and the setting length range is 0-2N-1. In the stage of establishing reliable transmission, N paths of pseudo-random sequences are generatedAnd the module moves the sequence of the corresponding channel according to the bit error rate obtained by reading the DAC chip until the bit error rate is 0. And sequentially setting the sequence order of the N paths of pseudo-random sequences until the error rates of all the channels are 0. In the waveform generation stage, under the drive of the timer, when the DAC chip detects that the bit error rate of a certain channel is not 0, the module can adjust the sequence of the corresponding channel until the bit error rate is 0.
The bias factor generation is shown in fig. 4. The data collected by the direct current ADC are sorted from small to large for N values each time, the sorting method is a bubble sorting method, then, a median value is taken as a value of a common mode level, the value enters an accumulator to be added, an initial value of the accumulator is set as a theoretical calculation value P, and a calculation formula is as follows:
P＝K×I
wherein K is the load impedance of the wideband DAC and is 50 ohms, and I is the common-mode current of the wideband DAC and is provided by a DAC manual. The output of the accumulator is an offset factor used for subtracting the waveform data, the circuit structure forms a convergent negative feedback structure, when the offset is increased, the offset factor is increased, the offset of the waveform data output is reduced, when the offset is reduced, the offset factor is reduced, the offset change rate of the waveform data output is reduced, and finally the output offset is automatically adjusted to 0.
The invention relates to a broadband arbitrary waveform generating device based on a CML interface; the device sequentially extracts waveform data into N paths of parallel branches in an FPGA, the N paths of parallel branches are respectively subjected to XOR operation with a pseudorandom sequence and transmitted to a broadband DAC chip through a CML level interface, and the DAC chip is subjected to XOR operation with the same pseudorandom sequence to obtain the waveform data and perform analog-to-digital conversion. The type and data sequence of the N paths of pseudo-random sequences are adjusted in the FPGA by the bit error rate tested by the DAC chip. The method adopts the CML interface to realize the high-speed data interconnection between the FPGA and the broadband DAC, and effectively improves the transmission rate of waveform data by means of the pseudorandom sequence, so that the waveform has higher data bandwidth. The broadband DAC chip generates a common-mode bias level when outputting, the device adopts a direct-current ADC to collect the common-mode level to form a feedback loop, the FPGA filters and accumulates the collected value at intermediate frequency, waveform data bias factors are set according to the accumulation result, N paths of waveform data and the bias factors are subjected to subtraction operation, the broadband DAC output signals are enabled to eliminate the influence of the common-mode level and are completely analog signals of waveform data conversion. The analog signal is output after filtering, attenuation and amplification. The device effectively improves the transmission bandwidth between the FPGA and the DAC chip, eliminates the influence of the broadband DAC common mode level, and has the advantages of simple circuit structure and large bandwidth for outputting any waveform.
It is to be understood that the above description is not intended to limit the present invention, and the present invention is not limited to the above examples, and those skilled in the art may make modifications, alterations, additions or substitutions within the spirit and scope of the present invention.
Claims (8)
1. A broadband arbitrary waveform generating device based on a CML interface is characterized in that: the device comprises an extraction module, a subtraction module, a CML interface module, a DAC chip, a median filtering module, a direct current ADC module and an analog channel;
the extraction module is configured to be used for sequentially extracting the waveform data into N branches;
a subtractor module configured for subtraction of the bias factor and the waveform data;
the CML interface module is configured to be used for transmitting the N paths of waveform data of the FPGA to the DAC chip;
the median filtering module is configured to sort the N numerical values of the bias information in an ascending order every time, take median data, accumulate the data and generate a bias factor;
a DC ADC module integrated with a low pass filter and a DC acquisition circuit configured to acquire a common mode level of the circuit;
an analog channel configured to implement analog signal conditioning functions of filtering, attenuation, and amplification.
2. The CML interface based wideband arbitrary waveform generation apparatus of claim 1, wherein: the extraction module comprises an FPGA.
3. The CML interface based wideband arbitrary waveform generation apparatus of claim 1, wherein: the CML interface module comprises an exclusive OR module, an N-path pseudo-random sequence generation module and a timer;
an exclusive-or module configured for exclusive-or operation of the pseudo-random sequence and the waveform data;
the N-path pseudo-random sequence generation module is configured to be used for generating N-path pseudo-random sequences according to the bit error rate detected by the N-path DAC chips;
and the DAC chip is configured to be used for integrating the CML interface and the N-way error code detection module.
4. The CML interface based wideband arbitrary waveform generation apparatus of claim 3, wherein: the N-path pseudo-random sequence generation module comprises a pseudo-random sequence generation module, a 1-path N-path module and an N-path FIFO module;
a pseudo-random sequence generation module configured to generate a pseudo-accompanying source sequence, the module being generated by using N stages of shift registers and comprising 2N1 states, the initial sequence order being set to the median of all states
The 1-N path module is configured to copy the output sequence of the pseudo-random sequence generation module into N paths of data;
an N-way FIFO module configured to set a sequence order of the pseudo-random sequence, the set length range being 0-2N-1。
5. The CML interface based wideband arbitrary waveform generation apparatus of claim 4, wherein: in the stage of establishing reliable transmission, the N-path FIFO module moves the sequence of the corresponding channels according to the error rate obtained by reading the DAC chip until the error rate is 0; sequentially setting the sequence order of the N paths of pseudo-random sequences until the error rates of all channels are 0; in the waveform generation stage, under the drive of the timer, when the DAC chip detects that the bit error rate of a certain channel is not 0, the module can adjust the sequence of the corresponding channel until the bit error rate is 0.
6. A broadband arbitrary waveform generation method based on a CML interface is characterized in that: the CML interface-based broadband arbitrary waveform generation apparatus according to claim 5, comprising:
step 1: a reliable transmission establishing stage; the method specifically comprises the following steps:
step 1.1: powering on, entering a CML interface to establish reliable transmission;
step 1.2: waveform data and bias factor are set to 0;
step 1.3: setting an initial sequence by the N paths of pseudo-random sequences, wherein the N paths of pseudo-random sequences generate the same pseudo-random sequence;
step 1.4: the N paths of pseudo-random sequences and the waveform data are subjected to exclusive OR and then transmitted to a DAC chip through a CML interface;
step 1.5: the DAC chip tests the bit error rate of N paths of data by using the same pseudo-random sequence and feeds the bit error rate back to a pseudo-random sequence generation module of the FPGA;
step 1.6: the pseudo-random sequence generation module moves the data sequence of the pseudo-random sequence according to the error rate and judges whether a channel M with the error rate not being 0 exists or not;
if: if the judgment result is that the channel M with the bit error rate not being 0 exists, executing the step 1.7;
or if the judgment result shows that the channel M with the error rate not being 0 does not exist, namely the error rate is 0 when the DAC chip tests, and the error rates of the N paths of data are all 0, the CML interface establishes reliable transmission; entering the step 2;
step 1.7: adjusting the order of the M channel pseudo-random sequences;
step 2: an offset calibration stage; the method specifically comprises the following steps:
step 2.1: the direct current ADC module acquires a common mode level output by the DAC chip and sends an acquired value to the FPGA;
step 2.2: the FPGA carries out median filtering on the acquired value, filters an interference signal, the value enters an accumulator to obtain a bias factor, and the bias factor is subtracted from the waveform data to form a negative feedback loop;
step 2.3: judging whether the common mode level acquired by the direct current ADC module is 0 or not;
if: if the judgment result is that the common mode level collected by the direct current ADC module is not 0, executing the step 2.1;
or if the judgment result is that the common mode level acquired by the direct current ADC module is 0, the bias calibration stage is finished, and the step 3 is entered;
and step 3: a normal waveform output stage; the method specifically comprises the following steps:
step 3.1: the waveform data is user waveform data, the waveform data is subtracted from the offset factor obtained in the offset calibration stage, and then the subtracted waveform data is subjected to exclusive or with the N-path pseudo-random sequence obtained in the reliable transmission establishment stage;
step 3.2: the data after the exclusive or in the step 3.1 is transmitted to a DAC chip through a CML interface for digital-to-analog conversion, and the converted data is output after low-pass filtering, attenuation and amplification through an analog channel;
and 4, step 4: detecting N paths of data error rates at fixed time, and judging whether a channel M with the error rate not being 0 exists or not;
if: if the judgment result is that the channel M with the bit error rate not being 0 exists, executing the step 1.7;
or judging that the channel M with the bit error rate not being 0 does not exist, and ending.
7. The CML interface based wideband arbitrary waveform generation method of claim 6, wherein: the bias factor generation method is as follows: the data collected by the direct current ADC module is sorted from small to large according to a bubble sorting method, then, a median value is taken as a value of a common mode level, the value enters an accumulator to be added, an initial value of the accumulator is set as a theoretical calculation value P, and a calculation formula is as follows:
P＝K×I；
k is the load impedance of the broadband DAC chip, I is the common-mode current of the broadband DAC chip and is provided by a DAC chip manual; the output of the accumulator is an offset factor used for subtracting the waveform data, the circuit structure forms a convergent negative feedback structure, when the offset is increased, the offset factor is increased, the offset of the waveform data output is reduced, when the offset is reduced, the offset factor is reduced, the offset change rate of the waveform data output is reduced, and finally the output offset is automatically adjusted to 0.
8. The CML interface based wideband arbitrary waveform generation method of claim 7, wherein: k was taken to be 50 ohms.
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