CN113691255A

CN113691255A - Configurable oscillator circuit for high-speed analog-to-digital converter

Info

Publication number: CN113691255A
Application number: CN202111017244.7A
Authority: CN
Inventors: 吴旭凡; 董业民
Original assignee: Guangdong Xinchi Integrated Circuit Technology Co ltd
Current assignee: Guangdong Xinchi Integrated Circuit Technology Co ltd
Priority date: 2021-08-31
Filing date: 2021-08-31
Publication date: 2021-11-23

Abstract

The invention discloses a configurable oscillator circuit for a high-speed analog-to-digital converter, which belongs to the field of oscillators and comprises a ring oscillator and an adjustable RC delay circuit; the adjustable RC delay circuit is connected into the ring oscillator by adjusting different numbers of resistors and capacitors, and the oscillation frequency of the ring oscillator is controlled. According to the invention, a plurality of high-precision resistors and capacitors are added in the ring oscillator circuit, so that the loop delay can be accurately controlled, and the oscillation frequency is controlled; a switch is added between a loop and a resistor capacitor, the size or the number of the resistors and the capacitors of an access circuit is selected through the switch, the total resistance-capacitance size is different, the transmission delay of the loop is changed along with the total resistance-capacitance size, and therefore the configuration of the oscillation frequency is achieved.

Description

Configurable oscillator circuit for high-speed analog-to-digital converter

Technical Field

The invention relates to the technical field of oscillators, in particular to a configurable oscillator circuit for a high-speed analog-to-digital converter.

Background

Oscillator circuits are commonly used to generate high frequency signals and have important applications especially in high speed analog to digital converters. As shown in fig. 1, the ring oscillator is a ring circuit composed of n (n is an odd number) not gates. At the output end of the oscillator, the output signal is periodically inverted from high level to low level and then to high level, so as to generate an oscillating signal with a fixed frequency.

If the delay time from when the input of a single inverter becomes 1/2VDD to when the output becomes 1/2VDD is considered as the delay time Δ t of a single inverter, the expression can be described as:

wherein t is_PLH、t_PHLThe propagation delay of the output of a single inverter from low to high and from high to low, respectively, represents the delay experienced by a signal passing gate, defined as the time between the 50% flip point of the input and output waveforms.

If Δ t represents the delay time of a single inverter, n represents the number of inverters, and f represents the frequency of the oscillator output signal, the frequency of the ring oscillator output can be written as:

wherein T is the total transmission delay (hereinafter referred to as total transmission delay) of a signal flowing through the loop for two cycles, and the inverter has a short delay time and is suitable for generating a high-frequency signal, the delay time is ns, and the frequency of an output signal is GHz. If the oscillation frequency is reduced to 1/n, n times of inverters are required to be connected in series in a ring circuit, redesign, simulation and debugging are required each time, and the workload is large and tedious. Therefore, a frequency configurable ring oscillator design is necessary.

The ring oscillator has the advantages of simple circuit and easy oscillation starting, but has the problems that the frequency of a delay network is not convenient to flexibly select, and the number of NOT gates is greatly multiplied to generate a lower frequency signal. Since there is a certain error in the delay time of the gate circuit, which also causes a large error in the actual oscillation frequency and the estimated value, the direct use of the series arrangement of the not gates does not allow a high-quality frequency output, and also limits the frequency range.

Disclosure of Invention

It is an object of the present invention to provide a configurable oscillator circuit for a high speed analog to digital converter that solves the problems of the background art.

In order to solve the above technical problem, the present invention provides a configurable oscillator circuit for a high-speed analog-to-digital converter, which comprises a ring oscillator and an adjustable RC delay circuit,

the adjustable RC delay circuit is connected into the ring oscillator by adjusting different numbers of resistors and capacitors, and the oscillation frequency of the ring oscillator is controlled.

Optionally, the RC delay circuit includes a plurality of capacitors and a plurality of resistors, the plurality of capacitors are connected in parallel, and a single end of the RC delay circuit is connected to the loop of the ring oscillator; several resistors are connected in series in the loop of the ring oscillator, creating a time delay.

Optionally, the first end of each capacitor is connected to the loop of the ring oscillator, and the second end of each capacitor is grounded through a switch.

Optionally, the second end of each resistor is connected to a switch and connected to the ring oscillator, and the first end is directly connected to the loop of the ring oscillator in series.

The configurable oscillator circuit for the high-speed analog-to-digital converter comprises a ring oscillator and an adjustable RC delay circuit; the adjustable RC delay circuit is connected into the ring oscillator by adjusting different numbers of resistors and capacitors, and the oscillation frequency of the ring oscillator is controlled.

(1) An annular structure formed by connecting three stages of NOT gates in series is adopted for generating a high-frequency signal and realizing the function of an oscillator;

(2) a plurality of high-precision resistors and capacitors are added in the ring oscillator circuit, so that the loop delay can be accurately controlled, and the oscillation frequency is controlled;

(3) a switch is added between a loop and a resistor capacitor, the size or the number of the resistors and the capacitors of an access circuit is selected through the switch, the total resistance-capacitance size is different, the transmission delay of the loop is changed along with the total resistance-capacitance size, and therefore the configuration of the oscillation frequency is achieved.

Drawings

FIG. 1 is a schematic diagram of a ring oscillator constructed with three inverters connected in series;

FIG. 2 is a schematic diagram of a configurable oscillator according to the present invention;

fig. 3 is another schematic diagram of a configurable oscillator according to the present invention.

Detailed Description

The configurable oscillator circuit for a high-speed analog-to-digital converter according to the present invention is further described in detail with reference to the accompanying drawings and the specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Example one

The invention provides a configurable oscillator circuit for a high-speed analog-to-digital converter.A ring oscillator assisted with an RC delay circuit structure can realize oscillator outputs with different frequencies, namely, the frequency configurable oscillator structure. As shown in fig. 2, the specific implementation method is: on the basis of a ring oscillator, a resistor, a capacitor and a switch with certain sizes are added to form an RC delay circuit.

With reference to fig. 2, the RC delay circuit includes a plurality of capacitors and a plurality of resistors, the plurality of capacitors are connected in parallel, and a single terminal is connected to the loop of the ring oscillator; several resistors are connected in series in the loop of the ring oscillator, creating a time delay. The first end of each capacitor is connected with the loop of the ring oscillator, and the second end of each capacitor is grounded through a switch. The second end of each resistor is connected with a switch and connected into the ring oscillator, and the first end of each resistor is directly connected into a loop of the ring oscillator in series. Through the control of the switch, the resistors and the capacitors with corresponding numbers or sizes are connected into the ring oscillator, and due to the introduction of the resistors and the capacitors, different RC circuit delay time can be obtained, so that the oscillation frequency of the whole oscillator can be controlled.

In the invention, the resistance values of the resistors can be the same, can be different or can be partially the same; the capacitance values of the capacitors can be all the same, can be completely different, and can be partially the same. For convenience of calculation and understanding, in the first embodiment, the resistance values of all the resistors are the same, and the capacitance values of all the capacitors are the same, for example, the description is made; other conditions of the resistor and the capacitor are similar to those of the first embodiment and are within the protection scope of the present invention.

Firstly, the transmission delay of a basic RC delay circuit is simply analyzed, and the time domain transmission function of the RC delay circuit is as follows:

where t is the delay time of the RC delay circuit, V_outIs the output voltage, V_inIs an input voltage, τ is a time constant, and the expression τ is R · C, R is a resistance value, and C is a capacitance value;

with input as V_DDOutput changed to 1/2V_DDThe delay time t of the RC delay circuit is expressed as:

t＝ln2·RC＝0.69RC

now, referring to fig. 2, if the switches S1 and S4 are closed, the resistance of the incoming loop is R, the capacitance is C, and the total delay time T is then₁The expression is as follows:

T₁＝2（n·Δt+0.69×RC）＝2nΔt+1.38RC

n is the number of inverters in the ring oscillator, delta t is the delay time of a single inverter, and the oscillation frequency f of the stable output₁Comprises the following steps:

if the switches S1, S2 and S5 are closed, the resistance of the introduced loop is 2R, the capacitance is 2C, and the total delay time T is₂Expression and oscillation frequency f₂Respectively as follows:

T₂＝2nΔt+1.38×4RC

if the switches S1, S2, S3 and S6 are closed, the resistance of the introduced loop is 3R, the capacitance is 3C, and the total delay time T is₃Expression and oscillation frequency f₃Respectively as follows:

T₃＝2nΔt+1.38×9RC

in summary, the configuration of the oscillator frequency can be realized by controlling the number of the resistors and the capacitors introduced through the switches, and the oscillator frequency after the output is stabilized can be summarized as:

wherein f is the oscillation frequency of the oscillator, T is the total transmission delay of the loop, n is the number of inverters, Δ T is the transmission delay of a single inverter, and m₁Number of resistors connected in series into the loop, m₂The number of capacitors incorporated into the loop.

If the number of the introduced resistors and capacitors is the same in each configuration, namely m₁＝m₂＝m(m>0) Then we can get from the above analysis that when m is 1, the delay is the smallest and has the largest oscillation frequency f_{m Yao x}：

When m takes the maximum value, the delay is maximum, and the oscillation frequency f is minimum_min：

From the formula, observe the total delay of different configurationsAt time T, it can be found that: the total delay T is in a square relation with the number m of the introduced resistors and capacitors, a unitary quadratic equation with the coefficient of 1.38RC and the increment of 2n delta T is formed, and the oscillation frequency and m²In inverse proportion.

If the number of resistors in the loop is fixed, i.e. m₁Invariable, m₂Variable, as shown in fig. 3, the oscillation frequency f can be summarized as:

at this time, the total delay T and the number m of introduced capacitors₂The frequency change after configuration is relatively slow in a linear relation. When the frequency divider is used, different circuit structures, RC sizes and mounting numbers can be selected according to the frequency configuration requirement.

Note that the RC should be reasonably controlled in the design process, and is not easily too large, otherwise the stability condition of the oscillator may not be satisfied, and the oscillator may not work normally. The circuit structure of the invention is an annular structure formed by three-stage NOT gates and a plurality of resistance capacitors, and has the characteristics of simple circuit and easy starting oscillation. The invention realizes the oscillation frequency adjustable function of the oscillator, and the oscillation frequency can be configured by controlling the number of resistors and capacitors connected into the circuit through a switch; compared with the traditional oscillator with fixed frequency, the oscillator has the characteristic of more convenient adjustment of the oscillation frequency. The invention uses RC circuit to control transmission delay, the resistance and capacitance are the common influence factors of transmission delay, and their values are determined by the process under the existing technology, and no larger value error occurs, so the invention has the characteristic of more accurate oscillation frequency.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims

1. A configurable oscillator circuit for a high-speed analog-to-digital converter, comprising a ring oscillator, characterized by an adjustable RC delay circuit,

2. The configurable oscillator circuit for a high speed analog to digital converter of claim 1, wherein the RC delay circuit comprises a plurality of capacitors and a plurality of resistors, the plurality of capacitors being connected in parallel, a single terminal being connected to a loop of the ring oscillator; several resistors are connected in series in the loop of the ring oscillator, creating a time delay.

3. A configurable oscillator circuit for a high speed analog to digital converter as claimed in claim 2, in which a first terminal of each capacitor is connected to the loop of the ring oscillator and a second terminal of each capacitor is connected to ground via a respective switch.

4. A configurable oscillator circuit for a high speed analog to digital converter as claimed in claim 2, in which the second terminal of each resistor is connected to a respective switch connected to the ring oscillator and the first terminal is connected directly in series to the ring oscillator loop.