CN113690155B - Monolithic microwave integrated circuit isolation ring design and chip screening method - Google Patents
Monolithic microwave integrated circuit isolation ring design and chip screening method Download PDFInfo
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- CN113690155B CN113690155B CN202111251383.6A CN202111251383A CN113690155B CN 113690155 B CN113690155 B CN 113690155B CN 202111251383 A CN202111251383 A CN 202111251383A CN 113690155 B CN113690155 B CN 113690155B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H—ELECTRICITY
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Abstract
The invention discloses a design of a monolithic microwave integrated circuit isolation ring and a chip screening method, aiming at enabling the isolation ring to be suitable for millimeter wave chips and the area of the isolation ring to be more than 5mm2The chip achieves the purpose of not influencing the internal circuit of the chip, a plurality of isolation lines are used for enclosing to form an isolation ring, one end of each isolation line is grounded and used for shielding interference signals outside the chip, and the other end of each isolation line is provided with a PAD (PAD application) and used for carrying out IV test on the isolation ring. The invention not only reserves the conventional function of the isolating ring, but also better adapts to the high-frequency characteristic of the millimeter wave chip. According to the invention, the resistance R of each isolation line is calculated by testing the IV value of the isolation ring, and the hidden crack chips on the wafer are isolated by resistance comparison, so that the hidden crack chips are prevented from flowing into the next procedure, and the larger loss is avoided.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a design of a monolithic microwave integrated circuit isolation ring and a design of a chip screening method.
Background
The production process of a semiconductor circuit is generally: the wafer is cleaned (Cleaning) properly, then oxidized (Oxidation) and deposited, and finally, repeated steps of photolithography, etching and ion implantation are performed. In the process of finishing the processing and manufacturing of circuits on the wafer, mechanical damage to the wafer is difficult to avoid, so that the probability of the wafer having hidden cracks is increased.
The latent cracks initially occur at the wafer stage and cannot be easily detected completely by a high power microscope because the latent cracks are not obvious or are hidden in the intermediate layer. Subsequently, mechanical stress is applied to the wafer during dicing of the wafer. Therefore, on one hand, the originally existing hidden cracks can deepen the crack strength and enlarge the area under the action of mechanical stress, so that the defect rate of the wafer is increased. On the other hand, cracks are easily generated in the cut chips near the hidden crack area, and the chips with the cracks flow into the next process, so that the task of chip screening in the subsequent process is increased, and the packaging yield is possibly influenced. Chip cracking is one of the most serious defects in semiconductor integrated circuit packaging processes and is also the most fatal failure mode of integrated circuit packaging. It is very important to avoid the generation of cracks in chips and to detect cracked chips in time, regardless of any stage of semiconductor manufacturing.
After the wafer fabrication process is completed, each chip must be tested, which is commonly referred to as CP testing (Circuit testing). The isolation Ring (Seal Ring) is a protection Ring between the Chip (Chip) and the scribe Line (scribe Line), and its most essential and main function is to prevent the Chip from being mechanically damaged during dicing. The existing single-ring open isolation ring design method is only suitable for chips with lower working frequency and smaller chip area. Once the working frequency of the chip is increased or the length of the isolation ring is longer, the opening characteristic of the single-ring isolation ring can easily generate a coupling effect, and the coupling effect is similar to that of a shielding cavity interfering with the internal circuit of the chip.
Disclosure of Invention
The invention aims to solve the problem that the existing single-ring isolating ring design method cannot be applied to a chip with a larger chip area, and provides a single-chip microwave integrated circuit isolating ring design and a chip screening method.
The technical scheme of the invention is as follows: a monolithic microwave integrated circuit isolation ring design and chip screening method comprises the following steps:
and S1, designing an isolation ring for each chip in the Layout design stage of the monolithic microwave integrated circuit chip.
And S2, in the CP test stage of the wafer, testing the IV value of each isolation line forming the isolation ring of the chip aiming at each chip in the wafer.
And S3, calculating the resistance value of each isolation line according to the IV value of each isolation line.
S4, judging whether the resistance values of all isolation lines forming the chip isolation ring are in the corresponding preset range or not for each chip in the wafer, if so, judging that the chip is a normal chip, and otherwise, judging that the chip has a hidden crack defect.
And S5, making an isolation mark on the wafer for the chip with the hidden crack defect, and dividing an isolation area of the wafer to complete the screening of the monolithic microwave integrated circuit chip.
Further, the specific method for designing the isolation ring for each chip in step S1 is as follows: an isolation ring is formed by enclosing N isolation lines on the chip, N is larger than or equal to 2, one end of each isolation line is grounded, the other end of each isolation line is provided with a PAD, and the PAD of the Nth isolation line is arranged adjacent to the grounding end of the first isolation line.
Further, step S2 includes the following substeps:
s21, in the CP test stage of the wafer, regarding each chip in the wafer, the PAD of each isolation line forming the chip isolation ring is used as the Port of the chip.
S22, inputting current I at Port of ith isolation lineiAnd measuring the voltage U of the Port of the ith isolation lineiWherein i =1, 2.
Further, the current input at the same Port is equal in magnitude for each chip in the wafer.
Further, step S3 is specifically: according to the IV value I of each isolation lineiAnd UiAnd calculating to obtain the resistance value R of each isolation linei=Ui/Ii。
Further, the corresponding preset range of the resistance value in step S4 is: rlowi≤Ri≤RhighiWherein R islowiRepresents the minimum value of the preset resistance clamping threshold of the ith isolation line, RhighiAnd the maximum value of the preset resistance clamping threshold of the ith isolation line is shown.
Further, the minimum value R of the resistance card control thresholdlowiAnd maximum value R of resistance clamping thresholdhighiAll pass through resistance values R in M chipsiAnd obtaining M as the total number of chips in the wafer.
The invention has the beneficial effects that:
(1) the isolation ring is designed into a ring formed by two or more isolation lines, one end of each isolation line is grounded and used for shielding interference signals outside a chip, and the other end of each isolation line is provided with a PAD (PAD application area) for carrying out IV (input/output) test on the isolation ring, so that the isolation ring is suitable for working at millimeter waves and having an area larger than 5mm2The chip of (1).
(2) The PAD of each isolation line is arranged close to the grounding end of the other isolation line, so that the influence on an internal circuit of a chip caused by a closed loop formed between the isolation lines is avoided.
(3) According to the invention, the resistance R of each isolation line is calculated by testing the IV value of the isolation ring, and the hidden crack chips on the wafer are isolated by resistance comparison, so that the hidden crack chips are prevented from flowing into the next procedure, and the larger loss is avoided.
Drawings
Fig. 1 is a flow chart of a monolithic microwave integrated circuit isolator ring design and a chip screening method according to an embodiment of the present invention.
Fig. 2 is a schematic diagram illustrating a design of a chip isolation ring with N =2 according to an embodiment of the present invention.
Fig. 3 is a schematic diagram illustrating a design of a chip isolation ring with N =3 according to an embodiment of the present invention.
Fig. 4 is a schematic diagram illustrating a port configuration and a test of a chip isolation ring when N =2 according to an embodiment of the present invention.
Fig. 5 is a schematic diagram illustrating a port configuration and a test of a chip isolation ring when N =3 according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It is to be understood that the embodiments shown and described in the drawings are merely exemplary and are intended to illustrate the principles and spirit of the invention, not to limit the scope of the invention.
The embodiment of the invention provides a monolithic microwave integrated circuit isolation ring design and a chip screening method, as shown in FIG. 1, the method comprises the following steps of S1-S5:
and S1, designing an isolation ring for each chip in the Layout design stage of the monolithic microwave integrated circuit chip.
In the embodiment of the invention, N isolation lines are used on the chip to form an isolation ring, N is more than or equal to 2, so that 2 or more opening points are arranged on the whole isolation ring. One end of each isolation line is grounded, the other end of each isolation line is provided with a chip routing Pin (PAD), and the PAD of the Nth isolation line is arranged adjacent to the grounding end of the first isolation line.
As shown in fig. 2, when N =2, PAD of the isolation line 1 is PAD1The ground terminal is GND1(ii) a PAD of the isolation line 2 is PAD2The ground terminal is GND2. Viewed in the clockwise direction, the mode of forming the isolation ring by the two isolation lines is as follows: PAD1→GND1→PAD2→GND2→PAD1。
As shown in fig. 3, when N =3, PAD of the isolation line 1 is PAD1The ground terminal is GND1(ii) a The PAD of the isolation line 2 is PAD2The ground terminal is GND2(ii) a PAD of the isolation line 3 is PAD3The ground terminal is GND3. Viewed in the clockwise direction, the mode that the isolating ring is enclosed by the three isolating lines is as follows: PAD1 → GND2→ PAD3 → GND1→ PAD2 → GND3 → PAD1。
And S2, in the CP test stage of the wafer, testing the IV value of each isolation line forming the isolation ring of the chip aiming at each chip in the wafer.
The step S2 includes the following substeps S21-S22:
s21, in the CP test stage of the wafer, regarding each chip in the wafer, the PAD of each isolation line forming the chip isolation ring is used as the Port of the chip.
As shown in fig. 4, when N =2, let PAD of isolation line 1 be Port1 Port, and PAD of isolation line 2 be Port2 Port.
As shown in fig. 5, when N =3, let PAD of isolation line 1 be Port1 Port, PAD of isolation line 2 be Port2 Port, and PAD of isolation line 3 be Port3 Port.
S22, inputting current I at Port of ith isolation lineiAnd measuring the voltage U of the Port of the ith isolation lineiWherein i =1, 2.
As shown in fig. 4, when N =2, the current I is input to the Port1 Port of the isolation line 11Testing the voltage U of the Port11(ii) a Inputting current I at Port2 Port of isolation line 22Testing the voltage U of the Port22。
As shown in fig. 5, when N =3, the current I is input to the Port1 Port of the isolation line 11Testing the voltage U of the Port11(ii) a Inputting current I at Port2 Port of isolation line 22Testing the voltage U of the Port22(ii) a Inputting current I at Port3 Port of isolation line 33Testing the voltage U of the Port33。
In the embodiment of the invention, the current input at the same Port is equal for each chip in the wafer.
Take two isolation lines as an example: the current input by M chips in the wafer at the Port1 has equal magnitude, and is I1(ii) a The current input by the M chips at the Port2 is equal in magnitude and is I2。
Take three isolation lines as an example: the current input by M chips in the wafer at the Port1 has equal magnitude, and is I1(ii) a M chips are onThe currents input from the ports 2 are equal in magnitude and are I2(ii) a The current input by the M chips at the Port3 is equal in magnitude and is I3。
S3, IV value I according to each isolation lineiAnd UiAnd calculating to obtain the resistance value R of each isolation linei=Ui/Ii。
S4, judging whether the resistance values of all isolation lines forming the chip isolation ring are in the corresponding preset range or not for each chip in the wafer, if so, judging that the chip is a normal chip, and otherwise, judging that the chip has a hidden crack defect.
In the embodiment of the present invention, the corresponding preset range of the resistance value is: rlowi≤Ri≤RhighiWherein R islowiRepresents the minimum value of the preset resistance clamping threshold of the ith isolation line, RhighiAnd the maximum value of the preset resistance clamping threshold of the ith isolation line is shown.
In the embodiment of the invention, the minimum value R of the resistance card control thresholdlowiAnd maximum value R of resistance clamping thresholdhighiAll pass through resistance values R in M chipsiAnd obtaining M as the total number of chips in the wafer. E.g. resistance stuck threshold minimum value Rlow1And maximum value R of resistance clamping thresholdhigh1All pass through the resistance value R of the first isolation line in M chips1And after a large amount of data are tested, determining according to three sigma intervals of data distribution.
And S5, making an isolation mark on the wafer for the chip with the hidden crack defect, and dividing an isolation area of the wafer to complete the screening of the monolithic microwave integrated circuit chip.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (6)
1. A monolithic microwave integrated circuit isolating ring design and chip screening method is characterized by comprising the following steps:
s1, designing an isolation ring for each chip in the Layout design stage of the monolithic microwave integrated circuit chip;
s2, in the CP test stage of the wafer, testing the IV value of each isolation line forming the isolation ring of the chip aiming at each chip in the wafer;
s3, calculating the resistance value of each isolation line according to the IV value of each isolation line;
s4, judging whether the resistance values of all isolation lines forming the chip isolation ring are in the corresponding preset range or not for each chip in the wafer, if so, judging that the chip is a normal chip, and otherwise, judging that the chip has a hidden crack defect;
s5, making an isolation mark on the wafer for the chip with the hidden crack defect, and dividing an isolation area of the wafer to complete screening of the monolithic microwave integrated circuit chip;
the specific method for designing the isolation ring for each chip in step S1 is as follows: an isolation ring is formed by enclosing N isolation lines on the chip, N is larger than or equal to 2, one end of each isolation line is grounded, the other end of each isolation line is provided with a PAD, and the PAD of the Nth isolation line is arranged adjacent to the grounding end of the first isolation line.
2. The method for designing an isolator ring and screening dies for monolithic microwave integrated circuits as claimed in claim 1, wherein said step S2 includes the sub-steps of:
s21, in the CP test stage of the wafer, regarding each chip in the wafer, using the PAD of each isolation line forming the chip isolation ring as the Port;
s22, inputting current I at Port of ith isolation lineiAnd measuring the voltage U of the Port of the ith isolation lineiWherein i =1, 2.
3. The monolithic microwave integrated circuit isolator ring design and die screening method of claim 2, wherein the current input at the same Port is equal in magnitude for each die in the wafer.
4. The method for designing the isolator ring and screening the chip of claim 2, wherein the step S3 is specifically as follows: according to the IV value I of each isolation lineiAnd UiAnd calculating to obtain the resistance value R of each isolation linei=Ui/Ii。
5. The method as claimed in claim 4, wherein the corresponding predetermined range of the resistance values in step S4 is as follows: rlowi≤Ri≤RhighiWherein R islowiRepresents the minimum value of the preset resistance clamping threshold of the ith isolation line, RhighiAnd the maximum value of the preset resistance clamping threshold of the ith isolation line is shown.
6. The monolithic microwave integrated circuit isolator ring design and chip screening method of claim 5, wherein the resistance stuck threshold minimum value RlowiAnd maximum value R of resistance clamping thresholdhighiAll pass through resistance values R in M chipsiAnd obtaining M as the total number of chips in the wafer.
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