CN113687967B - Method for recording startup error information - Google Patents
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- CN113687967B CN113687967B CN202010419690.XA CN202010419690A CN113687967B CN 113687967 B CN113687967 B CN 113687967B CN 202010419690 A CN202010419690 A CN 202010419690A CN 113687967 B CN113687967 B CN 113687967B
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0766—Error or fault reporting or storing
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2284—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by power-on test, e.g. power-on self test [POST]
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Abstract
The invention provides a startup error information recording method. The method for recording the startup error information comprises the following steps: when the BIOS is started to execute the self-detection program each time, the first subprogram judges whether the self-detection program is wrong or not, if so, the writing function of the BIOS memory is not ready, so that the debugging codes existing in the first address space of the CMOS memory are moved to the second address space, the processing unit executes each subprogram containing the debugging codes, the debugging codes of the executed subprograms are written into the first address space, and when the writing function is ready, the power-on error information corresponding to the debugging codes existing in the second address space is written into the BIOS memory.
Description
Technical Field
The present disclosure relates to a method for recording power-on error information.
Background
During the startup of the server, various error causes may occur. After the server is powered on, the system of the server is automatically restarted or stays in the local place according to different servers. If the server is automatically restarted, the user of the server has difficulty in tracking the cause of the server being on-line, and even if the server is not restarted, because the server is on-line, an engineer has difficulty in analyzing the cause of the server being on-line only by the debug code displayed on the LED lamp. Especially when the server is sold to the client, a common computer operator may restart without recording the visible LED lamp debug code when the computer operator runs out of the machine, so that even the simplest error information cannot be provided for the factory to remove the error. Therefore, regardless of whether the server is automatically restarted, the engineer is difficult to analyze and debug the server on-line status, resulting in low debug efficiency and inconvenience.
Furthermore, even if the server can display error information, the current server cannot display enough error information, so that thousands or tens of thousands of culverts can be executed by the server during the power-on process according to the complexity of the system of the current server, and it is difficult for engineers to analyze which time point the server is executed or which culvert is executed, so that the efficiency of debugging is quite low.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a startup error information recording method for improving the debugging efficiency
In order to solve the above-mentioned problems, the present invention provides a method for recording power-on error information for a server device, comprising: a processing unit executing a power-on self-test code to execute a first power-on self-test program and a second power-on self-test program successively, in the second power-on self-test program, the processing unit judging whether the first power-on self-test program executed previously is wrong, when the first power-on self-test program is wrong, the processing unit moving the debug code existing in a first address space of a complementary metal oxide semiconductor memory to a second address space of the complementary metal oxide semiconductor memory when a write function of a basic input output system memory is not ready; after the processing unit moves to the second address space, the processing unit executes a plurality of subroutines contained in the power-on self-detection code, wherein each subroutine contains a debug code, the processing unit writes the debug code of the executed subroutine into the first address space when executing the subroutine, and the processing unit writes the power-on error information corresponding to the debug code which exists in the second address space after the movement into the basic input output system memory when the writing function is ready.
Compared with the prior art, the debugging device of the server device in the startup error information recording method of the invention can know which time point and which subprogram the server device is on the machine according to the startup error information stored in the BIOS memory, and can be used as a reference for tracking and debugging so as to improve the debugging efficiency.
Drawings
FIG. 1 is a functional block diagram of an embodiment of a server device with power-on error information recording according to the present invention.
FIG. 2 is a flowchart of a method for recording power-on error information according to an embodiment of the present invention.
FIG. 3 is a flow chart of an embodiment of the power-on error message recording method illustrated in FIG. 2.
Detailed Description
Referring to fig. 1, fig. 1 is a functional block diagram of an embodiment of a server apparatus 1 with a startup error information recording function according to the present invention. The server device 1 includes a Basic Input Output System (BIOS) memory 11, a Complementary Metal Oxide Semiconductor (CMOS) memory 12, and a processing unit 13. The processing unit 13 is coupled to the BIOS memory 11 and the CMOS memory 12.
The BIOS memory 11 contains a Power-On Self-Test (POST) code, and the processing unit 13 reads the BIOS memory 11 to execute the Power-On Self-Test code to perform the Power-On procedure of the server device 1. Wherein the power-on self-test code comprises a plurality of sub-processes, wherein some of the sub-processes have debug codes and have different debug codes. For example, taking the example that the power-on self-test code includes tens of thousands of sub-programs and three of the sub-programs having debug codes (hereinafter referred to as a first sub-program, a second sub-program, and a third sub-program, respectively), the debug codes of the first sub-program, the second sub-program, and the third sub-program (for example, 16-ary notation) may be "0 x 01", "0 x 02", and "0 x 03", respectively. In one embodiment, the subroutine may be a routine (routine) to be executed in the power-on self-test process.
Based on the debug code, the CMOS memory 12 includes different address spaces (hereinafter referred to as a first address space and a second address space) for storing the debug code, and the processing unit 13 writes the debug code of the executed subroutine into the first address space to record the executed subroutine when executing the power-on self-test code; furthermore, in the case that the power-on self-detection procedure has been in error, the processing unit 13 can write the power-on error information corresponding to the debug code existing in the second address space into the BIOS memory 11 when the writing function of the BIOS memory 11 is ready (ready) so as to record the power-on error information of the server device 1. In one embodiment, the first address space and the second address space may be addresses of "42 h" and "43 h", respectively. Furthermore, the power-on error information can be the debug code, the date and time when the error occurred in the power-on self-test procedure.
Referring to fig. 1 and fig. 2 in combination, fig. 2 is a flowchart illustrating an embodiment of a method for recording boot error information according to the present invention. When executing the power-on self-test code, the processing unit 13 determines whether the power-on self-test program executed the previous time is wrong (step S01), that is, the processing unit 13 determines whether the server device 1 has been powered on, if the processing unit 13 determines that the power-on self-test program executed the previous time is not wrong when executing the power-on self-test code (no result of determination), the processing unit 13 executes the subroutine and writes the debug code of the executed subroutine into the first address space when executing the subroutine (step S03), so as to record the executed subroutine with the debug code in real time; on the other hand, if the processing unit 13 determines that the last power-on self-test program executed when the power-on self-test code is executed (yes in the determination), the processing unit 13 reads the first address space of the CMOS memory 12, the first address space contains the debug code of the executed subroutine written by the processing unit 13 when the last power-on self-test program is executed, and the processing unit 13 moves the debug code already existing in the first address space to the second address space when the write function of the BIOS memory 11 is not ready (step S02).
After the debug code is moved from the first address space to the second address space, the processing unit 13 executes the subroutine, and writes the debug code of the executed subroutine into the first address space when executing the subroutine (step S03), so that the debug code after writing covers the debug code already existing in the first address space, to record the executed subroutine in the power-on self-test program executed at present. When the writing function of the BIOS memory 11 is ready, the processing unit 13 writes the boot error information corresponding to the debug code in the second address space after the movement into the BIOS memory 11 (step S05), so as to record the error information generated when the boot self-test procedure is executed last time in the BIOS memory 11.
For example, taking the processing unit 13 sequentially executing a first power-on self-test program and a second power-on self-test program as an example, in the first power-on self-test program, the processing unit 13 writes the debug code "0 x 01" of the first subprogram into the first address space when executing the first subprogram, and writes the debug code "0 x 02" of the second subprogram into the first address space when executing the second subprogram, the server apparatus 1 then generates an on-machine condition after the debug code "0 x 02" is written into the first address space, the processing unit 13 executes the second power-on self-test program after the server apparatus 1 is restarted, and in the second power-on self-test program, the first power-on self-test program is judged to have an error (judged to have an error in step S01), then, in the second power-on self-test program, the processing unit 13 moves the debug code "0 x 02" stored in the first address space into the second address space, then the processing unit 13 starts to write the debug code "0 x 02" into the second address space after the processing unit 1 is restarted, and the memory error information "11" is written into the memory space "for the memory error" 11 "is ready to have been written into the memory information" 11. The processing unit 13 continues to execute the power-on self-test procedure after executing step S05 (step S12).
Therefore, the processing unit 13 can record the current sub-program executed in real time each time the boot self-test code is executed, and record the current situation in the BIOS memory 11, so that the debugger of the server device 1 can know which time point and which sub-program happens in the server device 1 according to the boot error information stored in the BIOS memory 11, and the current situation can be used as a reference for tracking and debugging, thereby improving the debugging efficiency.
In one embodiment, the processing unit 13 sequentially executes a plurality of sub-programs in step S03, and the processing unit 13 writes the debug code of the sub-program into the first address space to cover the debug code of different sub-programs when executing each sub-program having the debug code. Taking the first subroutine and the second subroutine as examples, the processing unit 13 writes the debug code "0 x 01" into the first address space when executing the first subroutine, and the processing unit 13 writes the debug code "0 x 02" into the first address space when executing the second subroutine, after the processing unit 13 writes the debug code "0 x 02" into the first address space, the debug code "0 x 02" covers the debug code "0 x 01" of the first subroutine existing in the first address space, so that the debug code stored in the first address space is updated from "0 x 01" to "0 x 02", and thus, the first address space can store the debug code of the latest subroutine that has been executed.
In one embodiment, the CMOS memory 12 further has a third address space, which may be an address of "40 h", and the third address space stores two flags (hereinafter referred to as a first flag and a second flag), wherein the first flag indicates whether the power-on self-test procedure is completed, the second flag indicates whether the power-on self-test procedure executed last time is wrong, and whether the power-on error information corresponding to the debug code existing in the second address space needs to be written into the BIOS memory 11, and the processing unit 13 determines whether the power-on self-test procedure executed last time is wrong according to the first flag and sets the second flag according to the first flag. When the writing function of the BIOS memory 11 is ready, the processing unit 13 determines whether to write the boot error information corresponding to the debug code in the second address space into the BIOS memory 11 according to the second flag.
In detail, referring to fig. 3, the first flag at the high level indicates that the power-on self-test procedure is not completed, and the processing unit 13 determines whether the first flag is at the high level (i.e., logic "1") when executing step S01 to determine whether the first power-on self-test procedure executed last time is completed. If the processing unit 13 determines in step S01 that the first flag is not at the high level (no in the determination result), for example, the first flag is at the low level, which indicates that the first power-on self-test procedure is completed without error, at this time, in the second power-on self-test procedure, the processing unit 13 sets the first flag to have the high level (step S07), that is, the processing unit 13 presets that the second power-on self-test procedure executed at present cannot be completed, so that the first flag is changed from the low level to the high level, so as to avoid that the processing unit 13 is in error when executing the second power-on self-test procedure, and cannot set the first flag to have the high level in the second power-on self-test procedure; after that, when the second power-on self-test procedure is completed, the processing unit 13 further resets the first flag (step S08), so that the first flag is changed from the high level to the low level, so as to indicate that the currently executed second power-on self-test procedure is completed without error.
Accordingly, after the processing unit 13 sets the first flag to have the high level (step S07), if the processing unit 13 is on-line during execution of the subroutine in the second power-on self-test procedure, after the server apparatus 1 is restarted, since the second power-on self-test procedure is not completed, the processing unit 13 has not reset the first flag to change the first flag to the low level in step S08, and the processing unit 13 can determine that the error occurred in the second power-on self-test procedure executed last time by virtue of the first flag being at the high level during execution of step S01 in the third power-on self-test procedure after the server apparatus 1 is restarted (yes in the determination result) so as to move the debug code existing in the first address space to the second address space (step S02).
On the other hand, in the second power-on self-test procedure, if the processing unit 13 determines that the first flag is at the high level (yes in step S01), it indicates that the first power-on self-test procedure executed last time is not completed, that is, the first power-on self-test procedure is in error, at this time, the processing unit 13 further sets the second flag according to the first flag having the high level (step S09); thus, taking the example that the second flag with the high level indicates that the error occurred in the last power-on self-test procedure (e.g., the first power-on self-test procedure), the processing unit 13 sets the second flag with the high level in step S09; accordingly, after the writing function of the BIOS memory 11 is ready (yes in step S04), the processing unit 13 determines whether the second flag has a high level (step S10), so as to determine whether the last power-on self-detection procedure executed by the processing unit 13 is wrong and the power-on error information corresponding to the debug code in the second address space needs to be written into the BIOS memory 11 (step S05), if it is determined that the second flag has a high level (yes in step S04), the processing unit 13 starts to execute step S05 and writes the power-on error information into the BIOS memory 11. After the processing unit 13 writes the boot error information into the BIOS memory 11, the processing unit 13 resets the second flag to have a low level (step S12), so that the second flag is changed from a high level to a low level to indicate that the recording of the boot error information is completed.
On the other hand, when the processing unit 13 determines in step S01 that the first power-on self-detection procedure executed last time is not wrong according to the first flag (no in the determination result) and the processing unit 11 determines in step S10 that the second flag is not at the high level (no in the determination result), the processing unit 11 executes step S11 to determine whether the second power-on self-detection procedure executed currently is completed and determine whether the server device 1 needs to perform the warm reset, and when the second power-on self-detection procedure is completed or the server device 1 needs to perform the warm reset, the processing unit 11 resets the first flag (step S08). Therefore, the processing unit 13 determines whether the power-on procedure is completed and whether the server device 1 needs to perform a system reset in the second power-on self-detection procedure executed at present, so as to determine whether to reset the first flag, regardless of whether the first flag and the second flag have high levels.
In one embodiment, the processing unit 13 further determines whether the power-on self-test procedure performed at present is completed before resetting the first flag (step S11), and if the power-on self-test procedure is completed, which indicates that no error occurs in the power-on self-test procedure performed at present, the processing unit 13 starts resetting the first flag to have a low level (step S08), so that the first flag is changed from the high level set in step S07 to the low level. Further, some of the subroutines have a function of causing the server apparatus 1 to perform a warm reset. In step S11, the processing unit 13 further determines whether the server device 1 needs to perform a warm reset, and if the server device 1 needs to perform a warm reset due to the above-mentioned subroutine (yes in step S11), the processing unit 13 also needs to reset the first flag to have a low level (step S08), so as to avoid the problem that the processing unit 13 has a judgment error in step S01 in the power-on self-detection procedure performed subsequently because the first flag is not reset to the low level after the start of the warm reset of the server device 1.
For example, taking the third sub-process having the function of enabling the server apparatus 1 to perform the warm reset as an example, the processing unit 13 sets the first flag to have a high level in step S07 of the second power-on self-test process, then the processing unit 13 performs the third sub-process in step S03 and determines that the server apparatus 1 needs to perform the warm reset in step S11, at this time, the first flag is at a high level, the first flag is changed from a high level to a low level after the processing unit 13 performs step S08, and after the server apparatus 1 is reset, the processing unit 13 performs the third power-on self-test process and determines that the first flag is at a low level instead of a high level in step S01, that is, correctly indicates that the previously performed second power-on self-test process is not in error (because the server apparatus 1 performs the warm reset instead of being in place).
In one embodiment, the processing unit 13 further calculates a checksum according to the data in the third address space in step S07, and stores the checksum in the fourth address space to indicate whether the CMOS memory 12 is damaged. For example, taking the data in the third address space as "0 x 01", the processing unit 13 calculates the checksum generated as "0 xFF", so that the sum of "0 xFF" and "0 x 01" should be generated as the sum of "0 x 00". In one embodiment, the fourth address space may be an address of "41 h".
Therefore, before the processing unit 13 determines whether the power-on self-detection code executed in the power-on self-detection procedure executed last time is wrong (step S01), the processing unit 13 determines whether the CMOS memory 12 is damaged (step S06), the processing unit 13 reads the CMOS memory 12 in step S06, the processing unit 13 sums the data in the third address space and the checksum stored in the fourth address space to generate a sum value, the processing unit 13 determines whether the sum value is zero, and if the sum value is not zero, it indicates that the sum value is not zero due to the change of the value of any one of the first flag, the second flag and the checksum stored in the CMOS memory 12 due to the damage of the CMOS memory 12. Accordingly, if the CMOS memory 12 is defective, the information representing the first flag and the second flag stored in the CMOS memory 12 is not worth referencing. Therefore, when the processing unit 13 determines that the CMOS memory 12 is damaged in step S06 (no result of the determination), the processing unit 13 does not execute steps S01, S02, S09, and the processing unit 13 starts executing from step S07, that is, in the case that the CMOS memory 12 is damaged, the processing unit 13 does not set the second flag to have a high level, and does not execute step S05 to write the boot error data into the BIOS memory 11.
In one embodiment, when the processing unit 12 writes the boot-up error information into the BIOS memory 11 in step S05, the processing unit 12 does not cover the boot-up error information written at different time points, that is, the boot-up error information generated at different time points can be stored in the BIOS memory 11, so that the maintainer of the server device 1 can perform debug analysis on the server device 1 according to more boot-up error information. Furthermore, the debug code of the above-mentioned subroutine may comprise two bytes (bytes), that is, the power-on self-test code may comprise 65536 subroutines having different debug codes at most. In this way, the debugger can increase the number of debug codes in the subroutine according to the actual requirement, and can more accurately know the executed subroutine with error when the server device 1 is in the on-machine condition according to the huge number of different debug codes.
In one embodiment, the writing function of the BIOS memory 11 is ready during a driver execution environment (DXE) boot phase included in the boot self-test program, that is, the processing unit 13 may update the boot error information in the BIOS memory 11 during the DXE boot phase by executing step S05. Furthermore, the server device 1 includes a south bridge chip, the CMOS memory 12 is located in the south bridge chip, and the write function of the south bridge chip is ready in the Security (SEC) stage included in the power-on self-test program, that is, the processing unit 13 can use the CMOS memory 12 to store the debug code of the executed subroutine when starting to execute the power-on self-test code.
In summary, according to an embodiment of the present invention, the debugger of the server device can know which time point and which subroutine is on-line according to the boot error information stored in the BIOS memory, and use the time point and the subroutine as the reference for tracking and debugging to improve the debugging efficiency.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather by the scope of the appended claims.
Claims (10)
1. A method for recording power-on error information is suitable for a server device, and is characterized by comprising the following steps:
In a second power-on self-detection program executed at present, a processing unit judges whether a first power-on self-detection program executed at the previous time is wrong or not;
When the first power-on self-test program has no error, the processing unit executes a plurality of sub-programs of power-on self-test codes contained in a basic input/output system memory and writes the debug codes of the executed sub-programs into a first address space of a complementary metal oxide semiconductor memory;
When the first power-on self-detection program generates errors, the processing unit moves the debug code existing in the first address space to a second address space of the CMOS memory when a write function of the BIOS memory is not ready;
after moving to the second address space, the processing unit executes the subroutines and writes the debug code of the executed subroutines into the first address space; and
When the writing function is ready, the processing unit writes a boot error message corresponding to the debug code in the second address space after being moved into the basic input/output system memory.
2. The method of claim 1, wherein a third address space of the CMOS memory stores a first flag indicating whether the first power-on self-test procedure is completed, and the processing unit determines whether the first flag has a predetermined level to determine whether the first power-on self-test procedure is wrong by the first flag in the step of determining whether the first power-on self-test procedure executed last time is wrong by the processing unit.
3. The method of claim 2, wherein the first flag is further used to indicate whether the second power-on self-test procedure is completed, and the method further comprises:
the processing unit sets the first flag to have the preset level after judging whether the first power-on self-detection program executed at the previous time is in error or not according to the first flag and before executing the subroutines, and the preset level is high; and
The processing unit resets the first flag to a low level when the second power-on self-test procedure is completed, so that the first flag indicates that the second power-on self-test procedure is completed.
4. The power-on error message recording method as claimed in claim 3, wherein in the second power-on self-test procedure, the power-on error message recording method further comprises: after setting the predetermined level at which the first flag has a high level, the processing unit further resets the first flag to a low level when the server device needs to perform a warm reset.
5. The method of claim 2, wherein the second power-on self-test procedure further comprises:
When the processing unit judges that the first power-on self-detection program is in error according to the first flag, the processing unit sets a second flag stored in the third address space to have a high level so as to indicate that the first power-on self-detection program executed last time is in error;
the processing unit judges whether the second flag has a high level when the writing function is ready;
When the second flag is at high level, the processing unit writes the power-on error information into the basic input/output system memory; and
The processing unit resets the second flag to a low level after the power-on error message is written into the bios memory.
6. The method of claim 5, wherein the second power-on self-test procedure further comprises: when the processing unit judges that the first power-on self-detection program is not wrong according to the first flag and the processing unit judges that the second flag is not at a high level, the processing unit judges whether the second power-on self-detection program executed at the moment is finished or not and judges whether the server device needs to be subjected to warm reset or not so as to determine whether to reset the first flag.
7. The method of claim 2, wherein the second power-on self-test procedure further comprises:
After judging whether the first power-on self-detection program executed at the previous time is wrong or not and before executing the subroutines, the processing unit calculates and generates a checksum according to the data in the third address space;
the processing unit determines whether the CMOS memory is damaged according to the checksum before determining whether the first power-on self-test procedure executed last time is wrong; and
If the CMOS memory is not damaged, the processing unit determines whether the first power-on self-test procedure executed last time is wrong.
8. The method of claim 7, wherein in the step of calculating the checksum by the processing unit, the processing unit stores the checksum in a fourth address space of the CMOS memory.
9. The method for recording power-on error information according to claim 1, wherein, some of the subroutines include different debug codes.
10. The method of claim 8, wherein the step of the processing unit writing the debug code of the executed subroutine into the first address space comprises:
The processing unit executes each subprogram in sequence; and
The processing unit writes the debug code of the executed one of the subroutines into the first address space each time the one of the subroutines is executed, so as to cover the different debug codes in the first address space.
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