CN113686261A - Silicon wafer suede testing method and device, electronic equipment and readable storage medium - Google Patents
Silicon wafer suede testing method and device, electronic equipment and readable storage medium Download PDFInfo
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Abstract
The embodiment of the invention discloses a method and a device for testing the texture surface of a silicon wafer, electronic equipment and a readable storage medium, wherein the testing method comprises the following steps: acquiring a texturing surface microscopic image of a textured silicon wafer, and performing image processing on the texturing surface microscopic image to obtain a texturing surface gray level image; extracting suede shape parameters of a single suede from the gray level image of the suede surface; and (4) counting the texture surface shape parameters of the texture surface, and determining the texture surface quality parameters of the textured silicon wafer. According to the embodiment of the invention, the texture information of the silicon wafer can be accurately counted, and the texture condition of the silicon wafer can be quantitatively counted, so that the texture quality of the silicon wafer can be effectively analyzed.
Description
Technical Field
The embodiment of the invention relates to a solar cell technology, in particular to a method and a device for testing a silicon wafer texture surface, electronic equipment and a readable storage medium.
Background
Conventional fossil fuels are increasingly consumed and cause environmental pollution, and solar energy is rapidly developed as a sustainable green energy source to replace the fossil fuels. At present, the main utilization mode of solar energy is photovoltaic power generation, such as solar cells, and among all solar cells, silicon solar cells are the mainstream of the current solar energy field, because silicon materials have extremely abundant reserves in the earth crust and excellent electrical and mechanical properties. Obviously, in the development direction of photovoltaic power generation technology, improving the photoelectric performance of a silicon solar cell will become a focus of research direction of the silicon solar cell.
In the process of preparing the silicon solar cell, the silicon wafer must be textured, and the uniformity and the size of the texture directly influence the efficiency of the solar cell. Different suede sizes have different influences on the efficiency of the solar cell, the reflectivity of a silicon wafer can be effectively reduced by the smaller suede, so that the short-circuit current of the solar cell is improved, and the larger suede is beneficial to the passivation of the suede by a subsequent process. Therefore, accurate statistics of the texture surface condition plays a crucial role in improving the texture surface process and the efficiency of the solar cell.
However, the existing silicon wafer texture surface statistical process is subjective, and has little effect on improving the texture surface making process.
Disclosure of Invention
The embodiment of the invention provides a method and a device for testing the texture surface of a silicon wafer, electronic equipment and a readable storage medium, which are used for quantitatively counting the texture surface condition of the silicon wafer.
The embodiment of the invention provides a method for testing the texture surface of a silicon wafer, which comprises the following steps:
acquiring a texturing surface microscopic image of a textured silicon wafer, and performing image processing on the texturing surface microscopic image to obtain a texturing surface gray level image;
extracting suede shape parameters of a single suede from the grey-scale image of the suede surface;
and (4) counting and processing the texture surface shape parameters of all texture surfaces, and determining and obtaining texture surface quality parameters of the textured silicon wafer.
Further, image processing the texturing surface microscopic image to obtain a texturing surface grayscale image includes:
calculating to obtain an average gray value according to the initial gray value of each pixel in the texturing surface microscopic image;
and adjusting each pixel of the texturing surface microscopic image with the initial gray value higher than the average gray value to be a first gray value and adjusting each other pixel to be a second gray value so as to obtain the texturing surface gray image, wherein the difference value between the first gray value and the second gray value is more than 200.
Further, before determining the initial gray value of each pixel in the micro-image of the texturing surface, the method further includes:
and sequentially carrying out scale setting, phase inversion, contrast adjustment and smooth image processing on the acquired texturing surface microscopic image.
Further, extracting the suede shape parameters of a single suede from the suede surface gray level image comprises: extracting each connected region from the gray level image of the texturing surface and calculating the texture surface shape parameters of the connected regions, wherein the pixels in the connected regions are the first gray level values.
Further, the statistical treatment of the texture surface shape parameters of all texture surfaces and the determination of the texture surface quality parameters of the textured silicon wafer comprise:
and counting the total area S1 of the first gray scale value and the total area S2 of the second gray scale value, and calculating the effective texturing density B according to the B which is S1/(S1+ S2).
Further, the suede shape parameters include: at least one of a pile area, pile size, squareness, circularity, ovality, Ferrett diameter, Ferrett angle, and centroid coordinates.
Further, the suede size X of a single suede of the monocrystalline silicon wafer is as follows:
s is the suede area of the single suede;
the suede size X of a single suede of the polycrystalline silicon wafer is as follows:
and S is the suede area of the single suede.
Further, after statistical treatment of the suede shape parameters of all the suede surfaces, the method further comprises the following steps: and classifying and counting all the suede surfaces according to the suede surface shape parameters to obtain the suede surface occupation ratio under the condition of fixing the suede surface shape parameters.
Further, the statistical treatment of the texture surface shape parameters of all texture surfaces and the determination of the texture surface quality parameters of the textured silicon wafer comprise:
arranging all the suede surfaces from small to large according to the suede surface area to obtain S1-Sy, wherein y is a positive integer;
calculating the cumulative area Kn of the textured area Sn,
wherein Ci is the number Ci of the texture surfaces with the texture surface area of Si, and n is less than or equal to y;
fitting a suede dimension X-cumulative area K curve,
wherein, X0 is the maximum suede size of the area ratio, dx is the suede size conversion range of X0 as Xn, and A1 and A2 are curve constants.
The embodiment of the invention also provides a testing device for the texture surface of the silicon wafer, which comprises:
the image processing module is used for acquiring a texturing surface microscopic image of a textured silicon wafer and carrying out image processing on the texturing surface microscopic image to obtain a texturing surface gray level image;
the parameter extraction module is used for extracting the suede shape parameters of a single suede from the suede surface gray level image;
and the texture quantization module is used for counting texture shape parameters of all textures and determining to obtain texture quality parameters of the textured silicon wafer.
An embodiment of the present invention further provides an electronic device, including:
one or more processors;
a storage device for storing one or more programs,
when the one or more programs are executed by the one or more processors, the one or more processors are enabled to realize the method for testing the texture of the silicon wafer.
The embodiment of the invention also provides a computer readable storage medium, wherein a computer program is stored on the computer readable storage medium, and when the program is executed by a processor, the method for testing the texture surface of the silicon wafer is realized.
In the embodiment of the invention, a texturing surface microscopic image of a textured silicon wafer is obtained, and the texturing surface microscopic image is subjected to image processing to obtain a texturing surface gray level image; extracting suede shape parameters of a single suede from the gray level image of the suede surface; and (4) counting the texture surface shape parameters of the texture surface, and determining the texture surface quality parameters of the textured silicon wafer. According to the embodiment of the invention, the texture information of the silicon wafer can be accurately counted, and the texture condition of the silicon wafer can be quantitatively counted, so that the quality of the texture is evaluated, and the quality of the texture of the silicon wafer is effectively analyzed. Obviously, according to the testing method provided by the invention, the parameters of each texture surface in the silicon wafer are used for carrying out statistics, the testing result is more comprehensive, rigorous and accurate, artificial subjective influence is eliminated, and the texturing process is favorably improved, so that the battery efficiency is improved.
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To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief description will be given below of the drawings required for the embodiments or the technical solutions in the prior art, and it is obvious that the drawings in the following description, although being some specific embodiments of the present invention, can be extended and extended to other structures and drawings by those skilled in the art according to the basic concepts of the device structure, the driving method and the manufacturing method disclosed and suggested by the various embodiments of the present invention, without making sure that these should be within the scope of the claims of the present invention.
FIG. 1 is a schematic diagram of a method for testing a textured surface of a silicon wafer according to an embodiment of the present invention;
FIG. 2 is a schematic view of a testing apparatus for a silicon wafer texture surface according to an embodiment of the present invention;
FIG. 3 is a micro-image of a texturized surface of a polysilicon silicon wafer after texturization;
FIG. 4 is a microscope image of the textured surface after image processing;
FIG. 5 is a grayscale image of a textured surface after image processing;
FIG. 6 is a grayscale image of a textured surface after image processing;
FIG. 7 is a schematic representation of a pile profile ratio waveform;
FIG. 8 is a pile size-cumulative area curve;
FIG. 9 is a fitted pile face size-cumulative area curve;
FIG. 10 is a textured surface microscopic image of a monocrystalline silicon wafer after texturing;
FIG. 11 is a grayscale image of a textured surface after image processing;
FIG. 12 is a pile size-cumulative area curve;
FIG. 13 is a fitted pile face size-cumulative area curve;
FIG. 14 is a schematic view of a textured surface of a polysilicon wafer according to the prior art;
fig. 15 is a schematic diagram of an electronic device provided in an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described through embodiments with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the basic idea disclosed and suggested by the embodiments of the present invention, are within the scope of the present invention.
Referring to fig. 1, a schematic diagram of a method for testing a textured surface of a silicon wafer according to an embodiment of the present invention is shown. The silicon wafer suede testing method provided by the embodiment can be executed through a testing device of the silicon wafer suede, and the testing device can be realized in a software and/or hardware mode and is configured in testing equipment.
The method for testing the texture of the silicon wafer provided by the embodiment comprises the following steps:
and step S1, acquiring a texturing surface microscopic image of the textured silicon wafer, and performing image processing on the texturing surface microscopic image to obtain a texturing surface gray level image.
As described above, in the process of manufacturing a silicon solar cell, texturing must be performed on a silicon wafer, wherein the silicon solar cell using single crystal silicon as a material mainly adopts an alkali texturing method, and the silicon solar cell using polycrystalline silicon as a material mainly adopts a metal-assisted catalytic acid texturing method. After the texturing is finished, the testing device calls a scanning electron microscope to shoot the texturing surface of the textured silicon wafer, and the testing device obtains a texturing surface microscopic image of the silicon wafer.
Then, the testing device performs image processing on the micro-image of the texturing surface through the image processing module to obtain a grayscale image of the texturing surface, and the image processing module integrated in the testing device can be selected for java-based image processing application. The gray level image of the texturing surface obtained after the image processing is an image formed by two gray level values, the difference value of the two gray level values is larger than or equal to 200, and the gray level value can also be called as a gray level value; for example, if the two gray scale values are 0 and 255, the texture surface microscopic image is subjected to image processing, and the texture surface gray scale image includes a plurality of pixels having a gray scale value of 0 and the remaining pixels have a gray scale value of 255. The relevant practitioner can set the two gray scale values reasonably as required by the test, and is not limited to the above examples.
And step S2, extracting the suede shape parameters of a single suede from the grey-scale image of the suede surface.
As described above, the gray level images of the texturing surfaces of the textured silicon wafers are obtained according to step S1, and then all the single textures can be extracted from the gray level images of the texturing surfaces, so as to obtain the texture shape parameters of the single texture. The selectable matte shape parameters include at least one of matte area, matte size, squareness, circularity, ovality, Ferrett diameter, Ferrett angle, and centroid coordinates. The texture surface shape parameters include, but are not limited to, the above examples, and relevant practitioners can reasonably select the texture surface shape parameters according to product requirements and then obtain the relevant shape parameters of a single texture surface in the gray level image of the texture surface.
And step S3, counting the suede shape parameters of all the suede surfaces, and determining the suede quality parameters of the silicon wafer after the suede is obtained.
As described above, the texture surface shape parameters of all the single texture surfaces in the texture surface gray level image are obtained, and then the texture surface shape parameters of all the texture surfaces can be statistically classified, so as to obtain texture surface quality parameters of the textured silicon wafer. For example, the suede area and the suede size of all single suede in the obtained suede surface gray level image are obtained, the suede size uniformity can be obtained through calculation, and the suede size uniformity can represent the size uniformity of each suede of the silicon wafer suede surface; the larger the numerical value of the size uniformity of the texture surface is, the poorer the size uniformity of each texture surface on the texture surface of the silicon wafer is, the larger the size difference between the texture surfaces is, and correspondingly, the quality difference of the texture surface of the silicon wafer is represented; the smaller the numerical value of the size uniformity of the texture surface is, the better the size uniformity of each texture surface on the texture surface of the silicon wafer is, the smaller the size difference between the texture surfaces is, and correspondingly, the good quality of the texture surface of the silicon wafer is represented. It can be understood that the texture surface quality parameters obtained through statistics are different when the texture surface shape parameters of the extracted single texture surface are different, and are not limited to the uniformity of the texture surface size. The texture surface quality parameters include, but are not limited to, the above examples, and relevant practitioners can reasonably select texture surface shape parameters according to product requirements, and then perform statistics to obtain relevant quality parameters of texture surface gray level images.
In the embodiment of the invention, a texturing surface microscopic image of a textured silicon wafer is obtained, and the texturing surface microscopic image is subjected to image processing to obtain a texturing surface gray level image; extracting suede shape parameters of a single suede from the gray level image of the suede surface; and (4) counting the texture surface shape parameters of the texture surface, and determining the texture surface quality parameters of the textured silicon wafer. According to the embodiment of the invention, the texture information of the silicon wafer can be accurately counted, the texture condition of the silicon wafer can be quantitatively counted, and the texture information is used as a standard for evaluating the texture quality, so that the effective analysis of the texture quality of the silicon wafer is realized. Obviously, by adopting the testing method, the statistical quantization is carried out according to the parameters of each texture surface in the silicon chip, the testing result is more comprehensive, rigorous and accurate, the artificial subjective influence is eliminated, the texturing process is favorably improved, and the battery efficiency is improved.
Optionally, the image processing the micro-image of the texturing surface to obtain a grayscale image of the texturing surface includes: calculating to obtain an average gray value according to the initial gray value of each pixel in the texturing surface microscopic image;
and adjusting each pixel with the initial gray value higher than the average gray value in the micro-image of the texturing surface to be a first gray value and adjusting each other pixel to be a second gray value so as to obtain a gray image of the texturing surface, wherein the difference value between the first gray value and the second gray value is more than 200.
The method specifically comprises the following steps: 1) acquiring a gray value of each pixel in the texturing surface microscopic image, wherein the gray value can be regarded as an initial gray value of the corresponding pixel; 2) summing the initial gray values of all pixels in the image, and averaging to obtain an average value, wherein the average value obtained by calculation is the average gray value; 3) and adjusting the gray value of each pixel of which the initial gray value is higher than the average gray value in the image from the initial gray value to a first gray value, and adjusting the gray value of each remaining pixel in the image from the initial gray value to a second gray value, so as to obtain the gray image of the texturing surface.
The difference between the first gray value and the second gray value is optionally greater than 200. For example, if the first gray value is 255 and the second gray value is 0, the processed gray image of the texturing surface is a black-and-white image. Taking 5 pixels in the micro-image of the textured surface as an example, the initial gray scale value of pixel 1 is 12, the initial gray scale value of pixel 2 is 217, the initial gray scale value of pixel 3 is 184, the initial gray scale value of pixel 4 is 93, and the initial gray scale value of pixel 5 is 56. If the average gray value calculated after counting the initial gray values of all the pixels is 166, the gray values of the adjusted pixels 1, 4 and 5 are all 0, and the gray values of the pixels 2 and 3 are all 255.
It is understood that the difference between the first gray scale value and the second gray scale value is merely an example, and the relevant practitioner may reasonably set the first gray scale value and the second gray scale value according to the needs of the product, and is not limited thereto; for example, the first gray scale value is 1 and the second gray scale value is 250. The algorithm used for the optional image gamma adjustment is the watershed algorithm.
Before adjusting the gray scale, the micro-image of the texturing surface can be subjected to image preprocessing. Specifically, before determining the initial gray value of each pixel in the micro-image of the texturing surface, the method further includes: and sequentially carrying out scale setting, phase inversion, contrast adjustment and smooth image processing on the acquired texturing surface microscopic image. It can be understood that the scale, the inverse phase, the contrast and the smoothing processing are all operations of image processing, specific setting parameters of the operations are not limited, but a microscopic image with high contrast is obtained after the final image processing, so that analysis can be conveniently carried out on a single suede. In other embodiments, the scaling, inverting, contrast adjusting and image smoothing processing may not be performed, or the scaling, contrast adjusting and image smoothing processing may be performed sequentially, and the manner of image processing is not limited thereto. And then carrying out gray level adjustment on the microscopic image after the first processing to obtain a gray level image.
The method for extracting the suede shape parameters of a single suede from the gray level image of the suede surface comprises the following steps: extracting each connected region from the gray level image of the texturing surface and calculating the texture shape parameters of the connected regions, wherein the pixels in the connected regions are all first gray level values. The gray image of the texturing surface obtained in step S1 is a black-and-white image, where a single texture is a connected region, the gray values of the pixels in one connected region are both the first gray values, and the gray value of the pixel between the two connected regions is the second gray value. The connected regions and the edges of the connected regions can be effectively divided, the connected regions are effective regions of a single suede, and parameters such as the area, the size and the like of each connected region can be obtained according to the plurality of connected regions in the image.
For example, the first gray scale value is 255 (white), the second gray scale value is 0 (black), the gray scale image of the texturing surface includes a plurality of white areas, two white areas are divided by a black line, the white areas are effective texturing areas in the gray scale image of the texturing surface, and the other black areas are ineffective texturing areas. The testing device can acquire the suede shape parameters of each effective suede area in the image.
Optionally statistically processing the suede shape parameters of all suede surfaces, and determining to obtain the suede quality parameters of the silicon wafer after the suede, wherein the method comprises the following steps: and counting the total area S1 of the first gray value region and the total area S2 of the second gray value region, and calculating the effective texturing density B according to the B which is S1/(S1+ S2). And knowing all the effective texturing areas and the ineffective texturing areas in the image, wherein the gray value of the pixel in the effective texturing area is a first gray value, and the gray value of the pixel in the ineffective texturing area is a second gray value, so that the effective texturing density can be calculated. The effective texturing density can be used as another standard for evaluating the texture quality of the silicon wafer, and obviously, the higher the effective texturing density is, the better the texture quality of the silicon wafer is.
The suede size X of a single suede of the selectable monocrystalline silicon piece is as follows:
s is the suede area of the single suede; the suede size X of a single suede of the polycrystalline silicon wafer is as follows:
and S is the suede area of the single suede. The suede size of a single suede is related to the suede area, the calculation formula of the suede size of the monocrystalline silicon wafer is different from the calculation formula of the suede size of the polycrystalline silicon wafer, the suede size of each suede in the silicon wafer can be calculated according to the formulas, and the description is omitted.
After optionally statistically processing the suede shape parameters of all the suede surfaces, the method further comprises the following steps: and (4) classifying and counting all the suede surfaces according to the suede surface shape parameters to obtain the suede surface occupation ratio under the condition of fixing the suede surface shape parameters. Knowing the pile face shape parameters of each pile face in the gray level image of the pile face surface, the pile face occupation ratio under the condition of fixing the pile face shape parameters can be determined.
Classifying the acquired suede shape parameters of all suedes according to the range of the required size X and the suede area, accumulating Sn of each group of data after classification to acquire the suede proportion under a fixed condition: a ∑ Sn/(S1+ S2). Of course, there are other suede-based evaluations of different parameters, not limited to these. For example, the suede area of each suede is acquired, and the suede size of each suede is calculated; and classifying the counted sizes of the suede according to a plurality of preset suede size intervals to obtain the area of each suede contained in each suede size interval, so as to obtain the suede area ratio of one suede size interval. Assuming that the sum of the areas of all the suede surfaces of the single suede surface in the suede surface size interval [200nm, 400nm ] is Ka, and the areas of all the suede surfaces in the suede surface gray level image are Kb, the suede surface occupation ratio of [200nm, 400nm ] is Ka/Kb. Here, the size interval [200nm, 400nm ] of the suede is the shape parameter of the fixed suede. It is understood that the fixed matte surface shape parameter may include at least one matte surface shape parameter, and if the matte surface size interval [200nm, 400nm ] and the circularity is greater than 0.8, the matte surface proportion of the matte surface with the circularity greater than 0.8 in the matte surface size interval [200nm, 400nm ] may be obtained.
Optionally statistically processing the suede shape parameters of all suede surfaces, and determining to obtain the suede quality parameters of the silicon wafer after the suede, wherein the method comprises the following steps: arranging all the suede surfaces from small to large according to the suede surface area to obtain S1-Sy, wherein y is a positive integer; calculating the cumulative area Kn of the textured area Sn,
wherein Ci is the number Ci of the texture surfaces with the texture surface area of Si, and n is less than or equal to y; fitting a suede dimension X-cumulative area K curve,
wherein, X0 is the matte size of the maximum ratio matte area, dx is the matte size transformation range of X0, and A1 and A2 are curve constants.
As described above, knowing the pile areas of the single piles in the gray images of the pile surface, the pile areas of all the single piles are sorted from small to large, the accumulated areas are calculated, and the sorted piles are sequentially marked as S1-Sy, S1 is the pile area with the smallest area, i.e., the 1 st pile area, i.e., the pile area with the smallest area, Si is the pile area with the ith pile area, and Sn is the pile area with the nth pile area.
The cumulative area Ki of the textured area Si is the sum of all textured areas of the single textured surface which is less than or equal to Si, i.e., the cumulative area K2 of S2 is the sum of all textured areas which is S1 plus the sum of all textured areas which is S2. For example, when the number of pile faces C1 of the pile face area S1 is 2 and the number of pile faces C2 of the pile face area S2 is 5, K2 is 2S1+5S 2. In practical situations, the suede areas of the single suede are rarely equal, the number Ci of the suede of the large possible suede area Si is 1, and the number Ci of the suede area Si is not 1 in rare situations; if the number of the suede surfaces of each suede surface area S in the image is 1, then
Knowing the cumulative area Kn of Sn, Kn corresponds to a knap size Xn. For the monocrystalline silicon wafer, the suede size Xn of a single suede corresponding to Sn is as follows:
for the polycrystalline silicon wafer, the suede size Xn of a single suede corresponding to Sn is as follows:
and drawing the size of the suede surface and the accumulated area by taking the accumulated area K as a vertical coordinate and the size X of the suede surface as a horizontal coordinate to obtain an X-K curve. Fitting the obtained X-K curve by using a sigmoidal-boltzmann equation,
wherein X0 is the maximum suede size of area ratio, dx is the suede size conversion range of X0 as Xn, A1 and A2 are curvesThe line constant. X0 is the point of maximum probability distribution of the pile size and represents the size of the pile with the largest area ratio. After fitting, at least the average size of all the suede surfaces, the uniformity dx of the suede surface size and the area-to-maximum suede surface size X0 can be obtained, and the quality of the silicon wafer suede surface can be evaluated by the quantized silicon wafer suede surface data.
In the embodiment, the image processing program is adopted to count the whole suede image, so that the artificial subjective influence is eliminated, and the suede image is more comprehensive and accurate; and a rigorous mathematical model (a symbolic-boltzmann equation) is also adopted to analyze the suede data, and the suede size, the suede size uniformity and the effective suede density with the largest quantifiable area ratio are obtained and are used as standards for evaluating the quality of the suede. In addition, the area, the size and the shape parameters of the single suede (including the squareness, the circularity, the ellipticity, the Feret diameter, the Feret angle, the centroid coordinate and the like) of all the single suede in the image can be counted.
Based on the same inventive concept, the embodiment of the invention also provides a testing device for the texture surface of the silicon wafer, and the testing device shown in fig. 2 is used for executing the testing method in any embodiment.
The test device of the embodiment comprises: the image processing module 110 is configured to obtain a texturing surface microscopic image of the textured silicon wafer, and perform image processing on the texturing surface microscopic image to obtain a texturing surface grayscale image; the parameter extraction module 120 is used for extracting the suede shape parameters of a single suede from the grey level image of the suede surface; and the suede quantization module 130 is used for counting and processing suede shape parameters of all suedes and determining suede quality parameters of the silicon wafer after suede processing is obtained.
In the embodiment of the invention, the information of the texture surface of the silicon wafer can be accurately counted, the texture surface condition of the silicon wafer can be quantitatively counted, for example, the size of each texture surface can be calculated to further calculate the uniformity of the size of the texture surface, the uniformity is used as a standard for evaluating the quality of the texture surface, the quality of the texture surface of the silicon wafer can be effectively analyzed, in other embodiments, other texture surface quality parameters can be determined according to other texture surface shape parameters, and the evaluation of the texture surface of the silicon wafer can be realized. Obviously, by adopting the testing device, the statistical quantification is carried out according to the parameters of each texture surface in the silicon wafer, the testing result is more comprehensive, rigorous and accurate, the artificial subjective influence is eliminated, the texturing process is favorably improved, and the battery efficiency is improved. The following is further described in connection with two specific examples.
The testing process of the testing device for the texture surface of the silicon wafer on the texture surface of the polycrystalline silicon wafer is as follows:
1. and (3) calling a Scanning Electron Microscope (SEM) to shoot the surface of the textured polycrystalline silicon wafer, wherein the obtained silicon wafer textured electron microscope image is shown in figure 3.
2. Invoking ImageJ software may optionally perform the following image processing on fig. 3: scale-inverse-contrast adjustment-smooth image, whereby fig. 4 is obtained; then, setting a gray threshold, namely the average gray value, and adjusting the image according to the gray threshold to classify the area in the image according to the first gray value and the second gray value into a white area and a black area, so as to obtain fig. 5, where the white area is an effective texturing area and the black area is an ineffective texturing area in fig. 5.
3. Dividing the graph 5 by using a watershed algorithm to obtain a graph 6, wherein each white connected region in the graph 6 is a suede; the ImageJ software was then used to count the area S of each white area in fig. 6 along with other shape parameters, and to calculate the pile size X,
4. and (4) classifying the data obtained in the step (3) to obtain a suede distribution map. For example: dividing every 200nm of the size interval of the suede size X from 0nm to 1000nm into a group, and dividing the group with the size larger than 1000nm into a group with the size larger than 1000nm being [0, 200], (200, 400], (400, 600], (600, 800], (800, 1000], (1000, + ∞), and classifying all suede according to the suede size interval; then, the user can use the device to perform the operation, dividing all the suedes in the same suede size interval into three groups according to the circularities of 0-0.4, 0.6-0.8 and 0.8-1, and accumulating the suede areas in the same suede size interval and positioned in the same circularity group to obtain the area ratio under the condition, wherein the area ratio is shown in figure 7; as can be seen from the figure 7 of the drawings, the proportion of the suede in the size range of 800-1000 nm is 22.63 percent, the proportion of the suede with the circularity higher than 0.6 in the group is 19.34%; the proportion of the suede in the size range of 1000-1200 nm is 19.87%, and the proportion of the suede with the circularity higher than 0.6 in the group is 15.61%.
5. The data obtained in step 3 are processed as follows: and arranging all the suede surfaces from small to large according to the area S, and accumulating the areas of all the sequenced suede surfaces according to different sizes to obtain an accumulated area K. Kn ═ Σ S (S ≦ Sn), where Ci is 1, and Kn is the sum of the areas of all the textured surfaces having an area smaller than or equal to Sn. The dimensions and the cumulative area were plotted with Xn as the abscissa and Kn as the ordinate to obtain fig. 8.
6. Fitting the resulting curve using the sigmoidal-boltzmann equation to obtain the equation for Kn and fig. 9:
as can be seen from the calculation, in fig. 9, X0 is 1012.3nm, dx is 182.8nm, and the maximum value of Kn is 69.59%, so the area of the pile accounts for 1012.3nm relative to the maximum pile size X0, the pile size uniformity dx is 182.8nm, and the effective pile density is 69.59%.
The testing process of the testing device of the silicon wafer texture surface on the texture surface of the monocrystalline silicon wafer is as follows:
1. scanning Electron Microscope (SEM) is called to shoot the surface of the textured monocrystalline silicon wafer, and the obtained textured surface electron microscope image of the silicon wafer is shown in FIG. 10.
2. The following processing was performed on fig. 10 using ImageJ software therein: setting a scale, inverting, adjusting contrast, smoothing the image, and then setting a gray threshold (i.e., an average gray value) to segment the region in the image according to the gray level, thereby obtaining fig. 11; then, the ImageJ software is used for counting the area and the shape parameters of each white area in the figure 11, and calculating the dimension X of the suede,
3. the data obtained in step 2 are processed as follows: and arranging all the suede surfaces from small to large according to the area S, and accumulating the areas of all the sequenced suede surfaces according to different sizes to obtain an accumulated area K. And Kn is ∑ S (S is less than or equal to Sn), and Kn is the sum of the areas of all the textured surfaces with the area less than or equal to Sn. Plotting the dimensions and the cumulative area with Xn as the abscissa and Kn as the ordinate yields fig. 12.
4. The resulting curves were fitted using the sigmoidal-boltzmann equation, whereby fig. 13 was obtained:
it can be found by calculation that X0 is 1768.2nm and dx is 213.4nm in fig. 13. So that the area of the suede accounts for 1768.2nm than the maximum suede size X0; the texture size uniformity dx was 213.4 nm.
Referring to fig. 14, a prior art texture measuring method for a silicon wafer is shown, wherein the silicon wafer is identical to the silicon wafer shown in fig. 3. In the prior art, the area-to-area ratio maximum pile face size is obtained by subjectively measuring individual maximum size points, wherein 3 visually-measured maximum pile face sizes are respectively 1.24 μm, 1.26 μm and 1.31 μm, and then X0 is 1.27 μm; x0 in FIG. 3 was 1.0123 μm as measured by the above measurement method; obviously, the invention has more accurate conclusion according to the statistical result. In the prior art, the uniformity dx of the size of the suede and the effective density Kn of the suede can be subjectively judged only by SEM images, quantification cannot be carried out, and the obtained result is inaccurate.
In this embodiment, the image processing software ImageJ is applied to processing and analysis of a texture scanning electron microscope, and the sigmoidal-boltzmann equation is applied to texture data fitting and data processing, so that the texture processing method is suitable for processing textures of single-crystal and polycrystalline silicon wafers, and can obtain the texture size, the texture uniformity and the effective texture density with the largest quantifiable area ratio as standards for evaluating the quality of the texture, and can also count the area, the size and the texture shape parameters (including the squareness, the circularity, the ellipticity, the fisher diameter (parameter), the fisher angle (angle), and the centroid coordinate) of all single textures.
Based on the same inventive concept, an embodiment of the present invention further provides an electronic device, including:
one or more processors;
a storage device for storing one or more programs,
when the one or more programs are executed by the one or more processors, the one or more processors implement the method for testing the texture of the silicon wafer as in any one of the above embodiments.
The embodiment of the invention also provides a computer readable storage medium, on which a computer program is stored, and when the program is executed by a processor, the method for testing the texture of the silicon wafer is implemented as in any one of the above embodiments.
Fig. 15 is a schematic structural diagram of an electronic device according to an embodiment of the present invention, as shown in fig. 15, the electronic device includes a processor 410, a memory 420, an input device 430, and an output device 440; the number of the processors 410 in the electronic device may be one or more, and one processor 410 is taken as an example in fig. 15; the processor 410, the memory 420, the input device 430 and the output device 440 in the electronic apparatus may be connected by a bus or other means, and the connection by the bus is exemplified in fig. 15.
The memory 420 is a computer-readable storage medium, and can be used for storing software programs, computer-executable programs, and modules, such as program instructions/modules corresponding to the method for testing the texture of the silicon wafer in the embodiment of the present invention. The processor 410 executes various functional applications and data processing of the electronic device by running the software programs, instructions and modules stored in the memory 420, that is, the method for testing the texture of the silicon wafer provided by the embodiment of the present invention is implemented.
The memory 420 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal, and the like. Further, the memory 420 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, memory 420 may further include memory located remotely from processor 410, which may be connected to an electronic device over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 430 may be used to receive input numeric or character information and generate key signal inputs related to user settings and function control of the electronic apparatus, and may include a keyboard, a mouse, and the like. The output device 440 may include a display device such as a display screen.
The embodiment also provides a storage medium containing computer executable instructions, and the computer executable instructions are used for realizing the method for testing the texture of the silicon wafer provided by the embodiment of the invention when being executed by a computer processor.
Of course, the storage medium provided in the embodiments of the present invention contains computer-executable instructions, and the computer-executable instructions are not limited to the above-described method operations, and may also perform related operations in the method for testing the texture of the silicon wafer provided in any embodiment of the present invention.
From the above description of the embodiments, it is obvious for those skilled in the art that the present invention can be implemented by software and necessary general hardware, and certainly, can also be implemented by hardware, but the former is a better embodiment in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute the methods according to the embodiments of the present invention.
It should be noted that, in the embodiment of the above search apparatus, each included unit and module are merely divided according to functional logic, but are not limited to the above division as long as the corresponding functions can be implemented; in addition, specific names of the functional units are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (12)
1. A method for testing the texture of a silicon wafer is characterized by comprising the following steps:
acquiring a texturing surface microscopic image of a textured silicon wafer, and performing image processing on the texturing surface microscopic image to obtain a texturing surface gray level image;
extracting suede shape parameters of a single suede from the grey-scale image of the suede surface;
and (4) counting and processing the texture surface shape parameters of all texture surfaces, and determining and obtaining texture surface quality parameters of the textured silicon wafer.
2. The testing method of claim 1, wherein image processing the textured surface microscopic image to obtain a textured surface grayscale image comprises:
calculating to obtain an average gray value according to the initial gray value of each pixel in the texturing surface microscopic image;
and adjusting each pixel of the texturing surface microscopic image with the initial gray value higher than the average gray value to be a first gray value and adjusting each other pixel to be a second gray value so as to obtain the texturing surface gray image, wherein the difference value between the first gray value and the second gray value is more than 200.
3. The method of claim 2, wherein prior to determining an initial gray value for each pixel in the microscope image of the textured surface, further comprising:
and sequentially carrying out scale setting, phase inversion, contrast adjustment and smooth image processing on the acquired texturing surface microscopic image.
4. The method of claim 2, wherein extracting the pile face shape parameters of a single pile face from the gray scale image of the pile face comprises: extracting each connected region from the gray level image of the texturing surface and calculating the texture surface shape parameters of the connected regions, wherein the pixels in the connected regions are the first gray level values.
5. The test method of claim 2, wherein the statistical treatment of the texture surface shape parameters of all texture surfaces to determine and obtain texture surface quality parameters of the textured silicon wafer comprises:
and counting the total area S1 of the first gray scale value and the total area S2 of the second gray scale value, and calculating the effective texturing density B according to the B which is S1/(S1+ S2).
6. The testing method of claim 1, wherein the textured shape parameters comprise: at least one of a pile area, pile size, squareness, circularity, ovality, Ferrett diameter, Ferrett angle, and centroid coordinates.
7. The test method according to claim 6, wherein the suede size X of a single suede of the single crystal silicon wafer is:
s is the suede area of the single suede;
the suede size X of a single suede of the polycrystalline silicon wafer is as follows:
and S is the suede area of the single suede.
8. The testing method of claim 1, wherein after statistically processing the suede shape parameters of all the suede surfaces, the method further comprises: and classifying and counting all the suede surfaces according to the suede surface shape parameters to obtain the suede surface occupation ratio under the condition of fixing the suede surface shape parameters.
9. The test method of claim 1, wherein the statistical treatment of the texture surface shape parameters of all texture surfaces to determine and obtain texture surface quality parameters of the textured silicon wafer comprises:
arranging all the suede surfaces from small to large according to the suede surface area to obtain S1-Sy, wherein y is a positive integer;
calculating the cumulative area Kn of the textured area Sn,
wherein Ci is the number Ci of the texture surfaces with the texture surface area of Si, and n is less than or equal to y;
fitting a suede dimension X-cumulative area K curve,
wherein, X0 is the maximum suede size of the area ratio, dx is the suede size conversion range of X0 as Xn, and A1 and A2 are curve constants.
10. A silicon chip suede testing device is characterized by comprising:
the image processing module is used for acquiring a texturing surface microscopic image of a textured silicon wafer and carrying out image processing on the texturing surface microscopic image to obtain a texturing surface gray level image;
the parameter extraction module is used for extracting the suede shape parameters of a single suede from the suede surface gray level image;
and the texture quantization module is used for counting texture shape parameters of all textures and determining to obtain texture quality parameters of the textured silicon wafer.
11. An electronic device, comprising:
one or more processors;
a storage device for storing one or more programs,
when executed by the one or more processors, cause the one or more processors to implement the method of testing the silicon wafer texture as recited in any one of claims 1-9.
12. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out a method of testing a silicon wafer texture as claimed in any one of claims 1 to 9.
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