CN113676992B

CN113676992B - Clock signal synchronization method and device

Info

Publication number: CN113676992B
Application number: CN202010404055.4A
Authority: CN
Inventors: 杨永超; 杨博; 莫道春; 臧大军
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-05-13
Filing date: 2020-05-13
Publication date: 2022-11-25
Anticipated expiration: 2040-05-13
Also published as: CN113676992A

Abstract

The embodiment of the application provides a clock synchronization method and a device, wherein the method comprises the following steps: receiving N groups of combined signals sent by data sending equipment, wherein each group of combined signals in the N groups of combined signals comprises X-path combined signals; each path of combined signal in the X paths of combined signals comprises a data signal, a noise signal and a clock signal; the data signals of the X-path combined signals in each group of combined signals are differential signals, and the noise signals in the X-path combined signals in each group of combined signals are common-mode signals; in the N groups of combined signals, the clock signal of the M groups of combined signals is a first clock signal, the clock signal of the N-M groups of combined signals is a second clock signal, and the first clock signal and the second clock signal are differential signals; and carrying out common mode processing and differential processing on the N groups of combined signals, and separating out clock signals, wherein the frequency of the clock signals is the same as that of the first clock signal and that of the second clock signal. The method and the device can realize frequency synchronization among multiple APs.

Description

Clock signal synchronization method and device

Technical Field

The embodiment of the application relates to the field of communication, in particular to a clock signal synchronization method and device.

Background

In a wireless fidelity (WiFi) network in a traditional enterprise scenario, interference between co-frequency APs is a main factor limiting throughput of the entire network, and a next generation IEEE802.11 standard considers that interference between co-frequency APs is eliminated by using an Access Point (AP) coordination (convergence) mode. In the prior art, a distributed Multi-input Multi-output (DMIMO) technique is usually adopted to eliminate interference between APs with the same frequency and bring a mode of maximum system gain.

The DMIMO technique relies on frequency synchronization between APs, but since the signal transmission process is affected by phase noise of independent crystal oscillators, jitter is easily generated in cooperation with clocks between APs, and thus the frequency synchronization effect between APs is affected.

Disclosure of Invention

The application provides a clock signal synchronization method and device, which can realize clock signal synchronization among multiple APs.

In order to achieve the purpose, the technical scheme is as follows:

in a first aspect, an embodiment of the present application provides a clock signal synchronization method, where the method is applied to a data receiving device, and the method includes: the data receiving equipment receives N groups of combined signals sent by the data sending equipment, wherein each group of combined signals in the N groups of combined signals comprises X paths of combined signals; each of the X combined signals includes a data signal, a noise signal, and a clock signal. The data signals of the X-path combined signals in each group of combined signals are differential signals, and the noise signals in the X-path combined signals in each group of combined signals are common-mode signals; in the N groups of combined signals, the clock signal of the M groups of combined signals is a first clock signal, the clock signal of the N-M groups of combined signals is a second clock signal, and the first clock signal and the second clock signal are differential signals. Then, the data receiving device performs common mode processing and differential processing on the N groups of combined signals to separate out clock signals, wherein the frequency of the clock signals is the same as that of the first clock signal and that of the second clock signal.

Based on the above manner, the data receiving device separates out a pure clock signal through common mode and differential processing by multiplexing the ethernet data lines to transmit the clock signal while transmitting the data signal, and the phases of the clock signals in the multiple combined signals are the same or opposite, so that high-precision frequency synchronization of the clock signals among the cooperative APs is realized in a manner similar to clock direct transmission.

In a possible implementation manner, the data receiving device performs common-mode processing and differential processing on the N groups of combined signals to separate out the clock signal, and includes: the data receiving device performs common mode processing on the X signals in each group of combined signals to obtain M first signals and (N-M) second signals, wherein the first signals comprise first clock signals with amplitude increased by X times and noise signals with amplitude increased by X times, and the second signals comprise second clock signals with amplitude increased by X times and noise signals with amplitude increased by X times. And the data receiving equipment carries out multiple iterative difference processing on the M paths of first signals and the (N-M) paths of second signals to obtain clock signals, wherein the amplitude of the clock signals is K times of that of the first clock signals or the second clock signals.

Based on the mode, the common-mode processing and the differential processing of the combined signal are realized, and the clock signal with the amplitude expanded by K times can be obtained so as to obtain a larger signal-to-noise ratio.

In one possible implementation, N =4,m =2, the data receiving device performs multiple iterative difference processing on the M first signals and the (N-M) second signals, including: the data receiving equipment subtracts the two combinations of the 2 paths of first signals and the 2 paths of second signals to obtain a third clock signal and a fourth clock signal, wherein the amplitude of the third clock signal is 2 times of that of the first clock signal, the amplitude of the fourth clock signal is 2 times of that of the second clock signal, and the third clock signal and the fourth clock signal are differential signals; the data receiving apparatus subtracts the third clock signal from the fourth clock signal to obtain a clock signal, the clock signal has the same frequency as the third clock signal and the fourth clock signal, the clock signal has the same phase as the third clock signal or the fourth clock signal, and the amplitude of the clock signal is 2 times the amplitude of the third clock signal or the fourth clock signal.

In one possible implementation, the method further includes: the data receiving equipment responds to the acquired P groups of data signals and clock signals to generate P groups of combined signals, wherein each group of combined signals in the P groups of combined signals comprises Q paths of combined signals; each path of combined signal in the Q paths of combined signals comprises a data signal and a clock signal; the data signals of the Q paths of combined signals in each group of combined signals are differential signals; in the P groups of combined signals, the clock signal of the L groups of combined signals is a third clock signal, the clock signal of the (P-L) groups of combined signals is a fourth clock signal, and the frequencies of the third clock signal and the fourth clock signal are the same as the frequency of the clock signal; and transmitting the P groups of combined signals to the second data receiving equipment.

Based on the above manner, it is realized that the data receiving device can also serve as a data sending device, that is, based on the separated clock signal, a combined signal is generated and transmitted to other data receiving devices, thereby realizing clock signal synchronization among multiple APs.

In one possible implementation, the method further includes: the data receiving device performs extremely narrow band filtering processing on the clock signal.

Based on the mode, the separated clock signals are subjected to extremely narrow band filtering, and therefore purer clock signals can be obtained.

In one possible implementation, the method further comprises: and the data receiving equipment subtracts the X-path combined signals in each group of combined signals to separate the data signals in each group of combined signals.

Based on the above manner, the data receiving device may subtract the combined signal to obtain the data signal, that is, in this application, the clock signal is transmitted by multiplexing the data line, and the data signal is not affected.

In one possible implementation, the clock signal is a single-tone clock signal.

Based on above-mentioned mode, this application is through adopting single tone clock signal, has the clock signal of single frequency promptly, and the frequency spectrum occupies for when carrying out the narrow band filtering to the clock signal who separates, can obtain better filtering effect.

In a second aspect, an embodiment of the present application provides a clock signal synchronization method, where the method is applied to a data transmission device, and the method includes: the data sending equipment responds to the acquired N groups of data signals and the original clock signal to generate N groups of combined signals, wherein each group of combined signals in the N groups of combined signals comprises X-path combined signals; each of the X combined signals includes a data signal and a clock signal. The data signals of the X-path combined signals in each group of combined signals are differential signals; in the N groups of combined signals, the clock signal of the M groups of combined signals is a first clock signal, the clock signal of the (N-M) groups of combined signals is a second clock signal, and the frequencies of the first clock signal and the second clock signal are the same as the frequency of the original clock signal. The data transmitting apparatus transmits the N sets of combined signals to the data receiving apparatus.

In one possible implementation, generating N sets of combined signals includes: the data sending equipment responds to the acquired original clock signal and generates M paths of first clock signals and (N-M) paths of second clock signals; the data transmission equipment synthesizes the M paths of first clock signals with M groups of data signals in the N groups of data signals to generate M groups of combined signals; and, the (N-M) second clock signals are combined with the (N-M) group data signals in the N group data signals to generate (N-M) group combined signals.

In a third aspect, an embodiment of the present application provides a data receiving device, where the data receiving device is connected to a data sending device through N groups of data lines, and the data receiving device includes a transceiver module and a clock data processing module. The receiving and transmitting module is used for receiving N groups of combined signals sent by the data sending equipment through N groups of data lines, and each group of combined signals in the N groups of combined signals comprises X-path combined signals; each path of combined signal in the X paths of combined signals comprises a data signal, a noise signal and a clock signal; the data signals of the X-path combined signals in each group of combined signals are differential signals, and the noise signals in the X-path combined signals in each group of combined signals are common-mode signals; in the N groups of combined signals, the clock signal of the M groups of combined signals is a first clock signal, the clock signal of the N-M groups of combined signals is a second clock signal, and the first clock signal and the second clock signal are differential signals; and the clock data processing module is used for carrying out common mode processing and differential processing on the N groups of combined signals and separating out clock signals, wherein the frequency of the clock signals is the same as that of the first clock signals and that of the second clock signals.

In one possible implementation, the clock data processing module includes at least one common mode processing unit and at least one differential processing unit; the common mode processing unit is used for carrying out common mode processing on the X-path signals in each group of combined signals to obtain M-path first signals and (N-M) -path second signals, wherein the first signals comprise first clock signals with amplitude increased by X times and noise signals with amplitude increased by X times, and the second signals comprise second clock signals with amplitude increased by X times and noise signals with amplitude increased by X times; and the differential processing unit is used for carrying out multiple iterative differential processing on the M paths of first signals and the (N-M) paths of second signals to obtain clock signals, and the amplitude of the clock signals is K times of that of the first clock signals or the second clock signals.

In one possible implementation, the common mode processing unit includes: at least one of a transformer, a power divider, a combiner and an inductor.

In a possible implementation manner, N =4,m =2, the difference processing unit is specifically configured to: the 2 paths of first signals and the 2 paths of second signals are combined and subtracted in pairs to obtain a third clock signal and a fourth clock signal, the amplitude of the third clock signal is 2 times that of the first clock signal, the amplitude of the fourth clock signal is 2 times that of the second clock signal, and the third clock signal and the fourth clock signal are differential signals; and subtracting the third clock signal from the fourth clock signal to obtain a clock signal, wherein the frequency of the clock signal is the same as that of the third clock signal and that of the fourth clock signal, the phase of the clock signal is the same as that of the third clock signal or that of the fourth clock signal, and the amplitude of the clock signal is 2 times that of the third clock signal or that of the fourth clock signal.

In a possible implementation manner, the data receiving device is connected to the second data receiving device through a P-group data line, and the data receiving device further includes a clock combination transmission module; the clock combination transmission module is used for responding to the acquired P groups of data signals and clock signals and generating P groups of combination signals, wherein each group of combination signals in the P groups of combination signals comprises Q paths of combination signals; each path of combined signal in the Q paths of combined signals comprises a data signal and a clock signal; the data signals of the Q paths of combined signals in each group of combined signals are differential signals; in the P groups of combined signals, the clock signal of the L groups of combined signals is a third clock signal, the clock signal of the (P-L) groups of combined signals is a fourth clock signal, and the frequency of the third clock signal and the frequency of the fourth clock signal are the same as the frequency of the clock signal; and the transceiving module is used for sending the P groups of combined signals to the second data receiving equipment through the P groups of data lines.

In a possible implementation manner, the data receiving device further includes a filtering module, configured to perform a very narrow-band filtering process on the clock signal.

In a possible implementation manner, the data receiving device further includes a physical layer PHY module, configured to subtract the X-path combined signals in each group of combined signals, and separate the data signals in each group of combined signals.

In one possible implementation, the clock signal is a single-tone clock signal.

In a fourth aspect, an embodiment of the present application provides a data sending device, where the data sending device is connected to a data receiving device through N groups of data lines, and the data sending device includes a transceiver module and a clock combined transmission module; the clock combination transmission module is used for responding to the acquired N groups of data signals and the original clock signal and generating N groups of combination signals, wherein each group of combination signals in the N groups of combination signals comprises X-path combination signals; each path of combined signal in the X paths of combined signals comprises a data signal and a clock signal; the data signals of the X-path combined signals in each group of combined signals are differential signals; in the N groups of combined signals, the clock signal of the M groups of combined signals is a first clock signal, the clock signal of the (N-M) groups of combined signals is a second clock signal, and the frequencies of the first clock signal and the second clock signal are the same as the frequency of the original clock signal; and the transceiving module is used for sending the N groups of combined signals to the data receiving equipment through the N groups of data lines.

In one possible implementation, the clock combination transmission module includes at least one common-mode processing unit and at least one differential processing unit; the differential processing unit is also used for responding to the acquired original clock signals and generating M paths of first clock signals and (N-M) paths of second clock signals; the common mode processing unit is used for synthesizing M groups of data signals in the M paths of first clock signals and the N groups of data signals to generate M groups of combined signals; and, the (N-M) second clock signals are combined with the (N-M) group data signals in the N group data signals to generate (N-M) group combined signals.

In a fifth aspect, an embodiment of the present application provides a chip, where the chip includes at least one processor and an interface; the interface is used for inputting N groups of combined signals sent by the data sending equipment to the processor, and each group of combined signals in the N groups of combined signals comprises X-path combined signals; each path of combined signal in the X paths of combined signals comprises a data signal, a noise signal and a clock signal; the data signals of the X-path combined signals in each group of combined signals are differential signals, and the noise signals in the X-path combined signals in each group of combined signals are common-mode signals; in the N groups of combined signals, the clock signal of the M groups of combined signals is a first clock signal, the clock signal of the N-M groups of combined signals is a second clock signal, and the first clock signal and the second clock signal are differential signals; and the processor is used for carrying out common mode processing and differential processing on the N groups of combined signals and separating out a clock signal, wherein the frequency of the clock signal is the same as that of the first clock signal and that of the second clock signal.

In a sixth aspect, an embodiment of the present application provides a chip, where the chip includes at least one processor and an interface; the processor is used for responding to the acquired N groups of data signals and the original clock signal and generating N groups of combined signals, wherein each group of combined signals in the N groups of combined signals comprises X paths of combined signals; each path of combined signal in the X paths of combined signals comprises a data signal and a clock signal; the data signals of the X-path combined signals in each group of combined signals are differential signals; in the N groups of combined signals, the clock signal of the M groups of combined signals is a first clock signal, the clock signal of the (N-M) groups of combined signals is a second clock signal, and the frequencies of the first clock signal and the second clock signal are the same as the frequency of the original clock signal; and the interface is used for sending the N groups of combined signals to the data receiving equipment.

In a seventh aspect, an embodiment of the present application provides an apparatus, including a transceiver module and a processing module, where the transceiver module is configured to receive N groups of combined signals sent by a data sending device, where each group of combined signals in the N groups of combined signals includes an X-path combined signal; each of the X combined signals includes a data signal, a noise signal, and a clock signal. The data signals of the X-path combined signals in each group of combined signals are differential signals, and the noise signals in the X-path combined signals in each group of combined signals are common-mode signals; in the N groups of combined signals, the clock signal of the M groups of combined signals is a first clock signal, the clock signal of the N-M groups of combined signals is a second clock signal, and the first clock signal and the second clock signal are differential signals. And the processing module is used for carrying out common mode processing and differential processing on the N groups of combined signals and separating out a clock signal, wherein the frequency of the clock signal is the same as that of the first clock signal and that of the second clock signal.

In an eighth aspect, an embodiment of the present application provides an apparatus, including a processing module, a transceiver module, and a processing module, where the processing module is configured to generate N groups of combined signals in response to N groups of acquired data signals and an original clock signal, where each group of combined signals in the N groups of combined signals includes X paths of combined signals; each of the X combined signals includes a data signal and a clock signal. The data signals of the X-path combined signals in each group of combined signals are differential signals; in the N groups of combined signals, the clock signal of the M groups of combined signals is a first clock signal, the clock signal of the (N-M) groups of combined signals is a second clock signal, and the frequencies of the first clock signal and the second clock signal are the same as the frequency of the original clock signal. And the transceiver module is used for transmitting the N groups of combined signals.

In a ninth aspect, embodiments of the present application provide a computer-readable medium for storing a computer program comprising instructions for executing the method of the first aspect or any possible implementation manner of the first aspect.

In a tenth aspect, embodiments of the present application provide a computer-readable medium for storing a computer program including instructions for executing the second aspect or the method in any possible implementation manner of the second aspect.

In an eleventh aspect, the present application provides a computer program including instructions for executing the method of the first aspect or any possible implementation manner of the first aspect.

In a twelfth aspect, the present application provides a computer program including instructions for executing the method of the second aspect or any possible implementation manner of the second aspect.

In a thirteenth aspect, an embodiment of the present application provides a chip, which includes a processing circuit and a transceiver pin. Wherein the transceiver pin and the processing circuit are in communication with each other via an internal connection path, and the processing circuit is configured to perform the method of the first aspect or any one of the possible implementations of the first aspect to control the receiving pin to receive signals and to control the sending pin to send signals.

In a fourteenth aspect, an embodiment of the present application provides a chip, where the chip includes a processing circuit and a transceiver pin. Wherein the transceiver pin and the processing circuit are in communication with each other via an internal connection path, and the processing circuit performs the method of the second aspect or any possible implementation manner of the second aspect to control the receiving pin to receive signals and to control the sending pin to send signals.

In a fifteenth aspect, an embodiment of the present application provides a communication system, which includes the data transmitting apparatus and the data receiving apparatus related to the first aspect and the second aspect.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments of the present application will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive exercise.

FIG. 1 is a diagram illustrating standard deviation jitter;

FIG. 2 is a schematic diagram of exemplary non-reciprocal dithering;

FIG. 3 is a schematic comparison of an exemplary non-DMIMO and DMIMO;

fig. 4 is a schematic diagram of an exemplary illustrative channel model of DMIMO;

FIG. 5 is a schematic diagram of an exemplary illustrative DMIMO frequency unsynchronized model;

FIG. 6 is an exemplary illustrative clock synchronization scheme;

FIG. 7 is an exemplary illustrative clock synchronization scheme;

FIG. 8 is an exemplary illustrative data level change diagram;

fig. 9 is a schematic view of an application scenario provided in an embodiment of the present application;

fig. 10 is a schematic view of an application scenario provided in an embodiment of the present application;

fig. 11 is a schematic interaction diagram of a data sending device and a data receiving device according to an embodiment of the present application;

fig. 12 is a schematic diagram of the connection of an exemplary illustrated differential processing unit;

fig. 13 is a schematic structural view of an exemplary data transmitting apparatus and data receiving apparatus;

fig. 14 is a schematic structural view of an exemplary data transmitting apparatus and data receiving apparatus;

fig. 15 is a schematic structural view of an exemplary data transmitting apparatus and data receiving apparatus;

FIG. 16 is an exemplary illustrative internal connection diagram;

fig. 17 is an interaction diagram of an exemplary data transmitting apparatus and a data receiving apparatus;

FIG. 18 is a schematic diagram illustrating interaction of a data transmission device with a data reception device;

fig. 19 is a schematic structural diagram of a data transmission device according to an embodiment of the present application;

fig. 20 is a schematic structural diagram of a data receiving device according to an embodiment of the present application;

fig. 21 is a schematic structural diagram of a network device according to an embodiment of the present application;

fig. 22 is a schematic structural diagram of a communication device according to an embodiment of the present application;

fig. 23 is a schematic structural diagram of a chip system according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone.

The terms "first" and "second," and the like in the description and in the claims of the embodiments of the present application, are used for distinguishing between different objects and not for describing a particular order of the objects. For example, the first target object and the second target object, etc. are specific sequences for distinguishing different target objects, rather than describing target objects.

In the embodiments of the present application, the words "exemplary" or "such as" are used herein to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "such as" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present relevant concepts in a concrete fashion.

In the description of the embodiments of the present application, the meaning of "a plurality" means two or more unless otherwise specified. For example, a plurality of processing units refers to two or more processing units; a plurality of systems refers to two or more systems.

For those skilled in the art to better understand the technical solutions of the present application, a brief description will first be made of the background art that may be involved:

(1) Phase noise (phase noise)

The phase noise is the ratio of the noise power per hertz (Hz) in the clock spectrum to the total power of the signal, is expressed as the random drift of the carrier phase, and is an important index for evaluating the frequency spectrum purity of the clock source.

(2) Clock jitter

The clock jitter is the appearance of phase noise in the time domain, which reflects the difference between the actual clock period and the ideal clock period, and usually the standard difference of the multiple period differences is taken as the measurement standard of the clock jitter, i.e. the standard deviation jitter. Referring to fig. 1, a diagram of standard deviation jitter is shown, and referring to fig. 1, the standard deviation jitter rms jitter can be expressed as:

wherein, P _n Is a real clock cycle, T ₀ Is the ideal clock period.

(3) Non-reciprocal dithering

The nonreciprocal jitter is relative jitter between two groups of clocks, reflects a difference value of corresponding periods between the two groups of clocks, and is used for representing consistency of the two groups of clocks. If the two groups of clocks are from the same clock source and have no interference in the middle, the nonreciprocal jitter of the two groups of clocks is considered to be zero. Referring to fig. 2, the non-reciprocal jitter is shown in fig. 2, and the non-reciprocal jitter threshold can be expressed as:

wherein, P _n Is the period of the first set of clocks, F _n The second set of clock periods.

The DMIMO technology can eliminate interference (i.e., interference between data fields) between APs with the same frequency, as shown in fig. 3, it is a conventional Wi-Fi, that is, a principle comparison diagram of the DMIMO technology and the DMIMO is not adopted, wherein two adjacent APs in the conventional Wi-Fi adopt an inter-frequency networking to eliminate interference to each other as much as possible, but interference between users in a cell overlapping area is difficult to avoid, for example, referring to fig. 3, a signal sent by AP1 to Station (STA) 1 also reaches STA2 to cause interference to STA2, and correspondingly, a channel sent by AP2 to STA2 also reaches STA1 to cause interference to STA 1. In contrast, the DMIMO neighboring APs use co-frequency networking, and multiple APs perform cooperative transmission, so that interference reaching a specific user is cancelled.

The principles of DMIMO are described in detail below: FIG. 4 is a schematic diagram of a channel model of DMIMO, where x ₁ And x ₂ Information indicating that AP1 and AP2 need to transmit to STA1 and STA2, respectively, y ₁ And y ₂ Information received by STA1 and STA2, respectively, h ₁₁ 、h ₁₂ 、h ₂₁ And h ₂₂ Respectively, the corresponding channels are expressed as follows:

y ₁ ＝h ₁₁ *x ₁ +h ₁₂ *x ₂

y ₂ ＝h ₂₁ *x ₁ +h ₂₂ *x ₂ (3)

the above two sets of equations can be expressed in matrix form, where matrix H represents the channel matrix:

therefore, if the channel matrix H is obtained before the AP transmits the information, the information to be transmitted may be precoded to eliminate interference to each other, which is specifically as follows:

for matrix H, there is the following relationship, where H ^-1 The inverse matrix representing H:

therefore, if the information to be sent by the distributed AP is multiplied by H first ^-1 This process is called precoding, and is specifically as follows:

in the above formula S ₁ And S ₂ Respectively representing the information actually transmitted by the AP1 and the AP2 after precoding, wherein both groups of information are x ₁ And x ₂ The mixed signal of (2).

S above ₁ And S ₂ After the channel transmission, the process of arriving at STA1 and STA2 can be expressed as the following relation:

the above equation indicates that STA1 only receives the information x ₁ STA2 only receives information x ₂ The interference between the two users is zeroed out so DMIMO can gain additional than traditional Wi-Fi.

The above-mentioned principle derivation about DMIMO is based on that the frequency between each AP and each STA is completely synchronized, wherein the frequency synchronization between the STA and the AP can perform real-time frequency offset compensation and phase tracking through a data frame, but no real-time information interaction is possible between the APs, so that it is difficult to perform real-time frequency offset compensation and phase tracking, and therefore, the frequency synchronization index between the APs is a key to influence the overall performance of DMIMO.

Specifically, as shown in fig. 5, a schematic diagram of a DMIMO frequency asynchronous model is shown, and referring to fig. 5, assuming that a relative frequency offset between AP1 and AP2 is Δ f, a non-reciprocal jitter is Δ θ (t), and STA1, STA2 and AP1 have performed frequency offset compensation and phase tracking, as shown in fig. 5, a DMIMO channel H measured by the system is transformed into:

the above equation shows that if the frequencies are not synchronized between APs, the actually measured channel H' will contain e ^j*Δf*t And e ^j*Δθ(t) Two time-varying components that cause the measured channel to vary widely from the actual channel, and ultimately cause the DMIMO to become dryThe interference nulling algorithm cannot achieve the desired interference cancellation effect.

To solve the above problem, as shown in fig. 6, a technical solution in the prior art is shown, and referring to fig. 6, in the prior art, a master-slave synchronization method based on an air interface selects one AP from a plurality of APs which are independently distributed as a master AP, and the other APs are slave APs. After the system receives the frequency synchronization command, the master AP sends a synchronization frame to each slave AP, each slave AP receives the synchronization frame and calculates the frequency offset value of each slave AP and the master AP by using the synchronization frame, then each slave AP reports the measured frequency offset value to the central baseband, and finally the central baseband compensates the frequency offset of each slave AP on the baseband data of each slave AP, so that the frequency offset influence of each slave AP and the master AP can be counteracted.

Calculating a frequency deviation value delta f by using repeated information in a traditional-Short Training Field (L-STF) Field and a traditional-Long Training Field (L-LTF) Field in a synchronous frame, and assuming that the repeated information is x ₁ If the sending time interval of the repeated information is T, then the following frequency offset calculation results are obtained:

the master-slave synchronization method based on the air interface relies on the synchronization frame interaction between the APs, frequency offset calculation errors inevitably exist due to the limitation of the length of the synchronization frame, and the frequency offset calculation and compensation cannot be carried out in real time. In addition, the method does not consider the influence of the phase noise of the clock source in each AP, the phase noise can cause two or more same-frequency clock sources to have random instantaneous frequency offset, and the instantaneous frequency offset is difficult to measure and compensate.

The method specifically comprises the following steps: phase noise results in each data sample being multiplied by e ^j*Δθ(t) Correspondingly, the result of the frequency offset calculation becomes:

therefore, when the influence of phase noise is considered, the prior art air interface frequency synchronization method cannot accurately calculate and compensate the frequency offset.

Referring to fig. 7, the method uses a wired Ethernet system between a central baseband and distributed APs, includes a data clock recovery module on each AP side, and can recover a data clock from Ethernet data through a clock data recovery technique, and specifically, extracts a Synchronous Ethernet (sync) clock of a Physical layer (PHY) chip on each AP side. The key of the method for realizing frequency synchronization comprises the following steps:

key point 1) each AP is connected to the same switch or the same central baseband unit through ethernet lines, with the emphasis on the data clock of each ethernet port being homogeneous.

Key point 2) the hop edge of the ethernet data is sufficiently rich. Since the clock recovery method needs to determine the phase information of the clock by using the transition edges in the ethernet data, if the continuous level in the ethernet data is too high, the recovered clock will lose the phase reference, resulting in deterioration of the clock phase noise.

In the two key points where the clock recovery method ensures frequency synchronization, for the key point 1), it can be implemented by connecting the ethernet lines of the APs to the same switch or the central baseband.

For key point 2), theoretically if the level of the ethernet data is changing all the time, the recovered clock will have a phase reference all the time, and the recovered clock will not have a loss in phase noise performance. However, ethernet data is to carry information, and the data level may not always change, as shown in fig. 8, which is an exemplary schematic diagram of data level change, referring to fig. 8, the data level always appears in the case of two or more consecutive same levels, so that the phase reference of the clock may be lost, the phase noise performance may inevitably deteriorate, and the non-reciprocal jitter of the multi-path synchronous clock may inevitably occur, and therefore, the prior art also has an inevitable frequency synchronization error.

In view of the above problems, the present application provides a clock synchronization method to solve the above drawbacks in the prior art. In the embodiment of the present application, the network device may be an access point where a terminal device (e.g., a mobile phone) enters a wired (or wireless) network, and is mainly deployed in a home, a building, and a garden, and a typical coverage radius is several tens of meters to hundreds of meters, and certainly, may also be deployed outdoors. The access point is equivalent to a bridge connected with a network and a wireless network, and is mainly used for connecting various wireless network clients together and then connecting the wireless network to the Ethernet.

Specifically, the access point may be a terminal device (e.g., a mobile phone) or a network device (e.g., a router) with a wireless-fidelity (WiFi) chip. The access point may be a device supporting 802.11be system. The access point may also be a device supporting multiple Wireless Local Area Network (WLAN) systems of 802.11 families, such as 802.11be, 802.11ax, 802.11ac, 802.11n, 802.11g, 802.11b, and 802.11 a. The access point in the application can be an HE-AP or an EHT-AP, and can also be an access point suitable for a future WiFi standard.

The terminal device may be a wireless communication chip, a wireless sensor, a wireless communication terminal, or the like, and may also be referred to as a user, a station, or a terminal. For example, the website may be a mobile phone supporting a WiFi communication function, a tablet computer supporting a WiFi communication function, a set top box supporting a WiFi communication function, a smart television supporting a WiFi communication function, a smart wearable device supporting a WiFi communication function, a vehicle-mounted communication device supporting a WiFi communication function, a computer supporting a WiFi communication function, and the like. Alternatively, a station may support the 802.11be system. The station can also support multiple WLAN formats of 802.11 families such as 802.11be, 802.11ax, 802.11ac, 802.11n, 802.11g, 802.11b and 802.11 a.

The terminal in the embodiment of the application can be an HE-STA or an EHT-STA, and can also be an STA suitable for WiFi standards of some future generation.

For example, the access point and the station may be devices applied to an internet of vehicles (IoT), internet of things (IoT) nodes, sensors, etc., smart cameras in smart homes, smart remote controllers, smart water meters, and sensors in smart cities.

It should be noted that the AP station and the non-AP station in this application may also be a wireless communication device supporting multiple links for parallel transmission, for example, referred to as a multi-link device (multi-link device) or a multi-band device (multi-band device). The multi-link device has higher transmission efficiency and higher throughput than a device supporting only single link transmission.

The multilink device includes one or more subordinate stations STA (afternamed STA), which is a logical station and can work on a link.

Although the embodiments of the present application are described primarily with reference to a network that deploys IEEE802.11, those skilled in the art will readily appreciate that the various aspects of the present application may be extended to other networks that employ various standards or protocols, such as BLUETOOTH, high performance wireless LAN (HIPERLAN), a wireless standard similar to the IEEE802.1 standard, used primarily in europe, and Wide Area Networks (WAN), wireless Local Area Networks (WLAN), personal Area Networks (PAN), or other now known or later developed networks. Thus, the various aspects provided herein may be applicable to any suitable wireless network, regardless of the coverage and wireless access protocol used.

Fig. 9 is a schematic diagram of an application scenario provided in an embodiment of the present application, and referring to fig. 9, the application scenario may include multiple Access Point (AP) class stations. For ease of description, an access point type station is referred to herein as an Access Point (AP) for purposes of illustration.

An application scenario including a plurality of APs (AP 1, AP2, AP3, and AP 4) in fig. 9 will be described as an example. The application scenario also includes a center baseband. Optionally, a switch (not shown in the figure) may be further included in the application scenario, and the central baseband may connect to multiple APs through the switch. Optionally, the central baseband is connected with each AP or the central baseband, the switch and each AP through a data line. Alternatively, the central baseband may be disposed in the AP, or may be in other network devices that can generate clock signals.

Fig. 10 is a schematic view of another application scenario provided in the embodiment of the present application, and referring to fig. 10, in the application scenario, a plurality of APs (AP 1, AP2, AP3, and AP 4) are connected in series. Alternatively, the APs may be connected to each other by a data line.

In one possible implementation, the data line may be an ethernet data line, in this application, the ethernet data line may be used to transmit a data signal and a clock signal, that is, the ethernet data line is multiplexed to transmit a clock signal in this application, and a specific transmission manner will be described in detail below. Optionally, the data lines include N groups of data lines, each group of data lines includes X data lines, and each data line is configured to transmit one path of combined signal in this application.

For example, the data line may be an ethernet differential twisted pair, which includes 4 sets (pairs) of twisted pairs, i.e., N =4,x =2, where each twisted pair is used to transmit a combined signal, and the specific transmission manner will be described in detail in the following embodiments.

Specifically, the present application mainly includes two types of devices, one is a data transmitting device, and the other is a data receiving device. For example, the data transmitting device may be the central baseband in fig. 8, and the data receiving device is an AP (AP 1, AP2, AP 3) in fig. 8, and an application of the present application in this scenario will be described in scenario one. For example, the data transmitting device may be AP1, AP2, and AP3 in fig. 9, and the data receiving device may be AP2 and AP3 in fig. 9, that is, in an application scenario of fig. 9, AP2 and AP3 may serve as both the data transmitting device and the data receiving device, and an application of the present application in this scenario will be described in a scenario two.

The following describes in detail an implementation principle of the clock synchronization method in the present application with reference to the above application scenarios. Fig. 11 is a schematic interaction diagram of a data sending device and a data receiving device in the present application, and refer to fig. 11:

1) Realization principle of data sending equipment end

Specifically, the data transmission device is configured to generate and transmit the combined signal. Referring to fig. 11, the data transmission apparatus 100 includes a clock combining transmission module 110, a PHY module 120, and a clock source module 130.

The specific use of each module is described in detail below:

the Clock source module 130 is connected to the Clock combination transmission module 110 for generating a Clock signal (Clock + or Clock-).

The PHY module 120 is connected to the clock combination transmission module 110, and is configured to generate N sets of differential Data signals based on the received Data signals (Data), for example, data1, data2 \8230 \ 8230;, data N, where each set of differential Data signals includes X paths of differential Data signals, and the differential Data signals in the X paths of differential Data signals are differential signals, that is, signals having the same amplitude and opposite phases, and may also be understood as signals having opposite phases and symmetric waveforms.

For example, PHY module 120 receives Data1, data2, data3, and Data4, and may generate 4 sets of differential Data signals based on Data1, data2, data3, and Data4, respectively: data1+ and Data1-, data2+ and Data2-, data3+ and Data3-, data4+ and Data4-.

It should be noted that the data signal received by the PHY module 120 is sent by a network side, and for example, the number N of the data signals received by the PHY module 120 may be greater than N or smaller than N, which is not limited in the present application. However, the number of groups of differential data signals generated by the PHY module 120 needs to be equal to N, i.e., N groups of differential data signals are generated, and each group of differential data signals includes X paths of differential data signals for combining with a subsequently generated clock signal to generate a combined signal.

The Clock combining transmission module 110 may receive the Clock signal (Clock + or Clock-) from the Clock source module 130 and the N sets of differential data signals from the PHY module 120, and the Clock combining transmission module 110 may generate the N sets of combined signals based on the Clock signal and the N sets of differential data signals. Wherein, each group of combined signals comprises X paths of combined signals, and each path of combined signals comprises data signals and clock signals.

Illustratively, the Data signals Data in the combined signals are the differential Data signals in the above, that is, the Data signals in the N groups of combined signals have the characteristics corresponding to the N groups of differential Data signals, that is, the Data signals in the X-way combined signals in each group of combined signals are differential signals.

For example, the clock signals of the X-path signals in the N groups of combined signals are common-mode signals, i.e., the amplitudes and polarities of the clock signals are the same, and it should be noted that in this application, the clock signals are single-tone clock signals, and the single-tone clock signals have a single frequency, so the clock signals that are common-mode signals can be regarded as having the same amplitude and frequency and the same polarity, and the clock signals that are differential signals can be regarded as having the same amplitude and frequency and the opposite polarities. Illustratively, the Clock signal of the M of the N sets of combined signals may be Clock +, and the Clock signal of the other (N-M) set of combined signals may be Clock-. Illustratively, the Clock signal of the M of the N sets of combined signals may be Clock-, and the Clock signal of the other (N-M) sets of combined signals may be Clock +. It is also understood that the Clock signals in the M sets of combined signals and the (N-M) combined signals are at the same frequency as the Clock signal (e.g., clock +) generated by the Clock source module 130, wherein the Clock signals in the M sets of combined signals or the (N-M) combined signals are opposite in polarity to the Clock signal (e.g., clock +) generated by the Clock source module 130.

The generation process of the N sets of combined signals is explained in detail below. Specifically, the clock combinational transmission module 110 includes a plurality of differential processing units 111 (e.g., a differential processing unit 111a, a differential processing unit 111b \8230; a differential processing unit 111 n) and a plurality of common mode processing units 112 (e.g., a common mode processing unit 112a, a common mode processing unit 112b \8230; a common mode processing unit 112 n). It should be noted that the number of the differential processing unit and the common mode processing unit may be the same or different, and the present application is not limited thereto.

The differential processing unit 111 is connected to the clock source module 130, and configured to generate N/2 groups or ceil (N/2) groups of differential clock signals based on the clock signal generated by the clock source module 130, where the X-path differential clock signals in each group of differential clock signals are differential signals, that is, the frequencies are the same and the polarities are opposite. Wherein, when N is even, it is N/2 groups of differential clock signals, and if N is odd, it is ceil (N/2) groups of differential clock signals, ceil () represents rounding up.

Alternatively, referring to fig. 11, the difference processing unit 111 is connected in a stepwise manner. It should be noted that, in the present application, the differential processing unit 111 is taken as an example of a balun, which is limited by a device structure of the balun, and the balun can only receive or generate two paths of signals. In other embodiments, the differential processing unit 111 may also be other devices capable of converting a single-ended signal into a differential signal or converting a differential signal into a single-ended signal, for example, may receive or generate more than two signals, which is not limited in this application.

Still referring to fig. 11, the differential processing unit 111 includes n layers, which are respectively the 1 st layer to the nth layer from left to right. The layer 1, for example, the differential processing unit 111a is connected to the clock source module 130, the last layer, that is, the multiple differential processing units in the nth layer, are connected to the common mode processing unit 112, specifically, each differential processing unit in the nth layer may be connected to multiple common mode processing units, the number of the connected common mode processing units depends on the processing capability of the differential processing units, taking balun as an example, the balun can only output two signals, and therefore, each differential processing unit in the nth layer can only be connected to two common mode processing units.

Specifically, the function of the differential processing unit is mainly divided into two functions of converting single-ended signals into differential signals or converting differential signals into single-ended signals, and in the data transmission device 100, the differential processing unit 111 is used for converting single-ended signals into differential signals, that is, each differential processing unit can convert one input signal into multiple signals with the same amplitude and opposite polarity. Still taking balun as an example, the differential processing unit (e.g., the differential processing unit 111 a) takes the Clock signal Clock + from the Clock source module 130 as an input signal and outputs two differential Clock signals, clock + and Clock-.

As described above, the plurality of differential processing units in the differential processing unit 111 are connected in a stepwise manner, and the multiple paths of differential clock signals output by each differential processing unit are transmitted to the differential processing unit connected thereto in the next layer for further processing, and the process is repeated until the differential processing unit in the nth layer generates N/2 groups or ceil (N/2) groups of differential clock signals.

For example, as shown in fig. 12, which is a schematic connection diagram of the differential processing unit 111, the clock combination transmission module includes 3 differential processing units, which are a differential processing unit 111a, a differential processing unit 111b, and a differential processing unit 111c, respectively, where the differential processing unit 111a is a differential processing unit of a first layer, and is connected to the differential processing unit 111b and the differential processing unit 111c of a second layer, respectively. Alternatively, the difference processing unit 111a may also be referred to as an upstream difference processing unit of the difference processing unit 111b and the difference processing unit 111c, and the difference processing unit 111b and the difference processing unit 111c are downstream difference processing units of the difference processing unit 111a. The differential processing unit 111a receives the Clock signal generated by the Clock source module 130, such as Clock +, and the differential unit 111a generates a set of differential Clock signals based on the received Clock +, including: clock + and Clock-, the frequency of two differential Clock signals is the same, and the polarity is opposite. The differential processing unit 111a transmits two differential Clock signals Clock + and Clock-to the downstream differential processing units, illustratively, clock + to differential processing unit 111b and Clock-to differential processing unit 111c. The differential processing unit 111b generates Clock + and Clock-based on the received Clock +, and the differential processing unit 111c is similar, which is not described herein, i.e., the differential processing unit 111 generates two sets of differential Clock signals, one set being Clock + and Clock-and the other set being Clock + and Clock-based on the Clock + from the Clock source module 130.

Still referring to fig. 11, the common mode processing unit 112 is connected to the differential processing unit 111 and the PHY module 120, and configured to perform common mode processing, which may also be referred to as synthesis processing, on the differential data signal transmitted from the PHY module 120 and the differential clock signal from the differential processing unit 111 to generate N sets of combined signals as described above, where each set of combined signals includes X combined signals, each set of combined signals in the X combined signals includes a data signal (i.e., a differential clock signal) and a clock signal (i.e., a differential clock signal), and the data signals in the X combined signals are differential signals, i.e., have the same amplitude and opposite polarities. In one example, the Clock signals received by the M common mode processing units are Clock +, (N-M) common mode processing units are Clock-, accordingly, the Clock signal in M of the N combined signals generated by the common mode processing unit 112 is Clock +, and the Clock signal in (N-M) of the N combined signals generated by the common mode processing unit 112 is Clock-. In another example, the Clock signals received by the M common mode processing units are Clock-, the Clock signals received by the (N-M) common mode processing units are Clock +, accordingly, the Clock signal of M combined signals generated by the common mode processing unit 112 is Clock-, and the Clock signal of (N-M) combined signals of N combined signals generated by the common mode processing unit 112 is Clock +.

Specifically, the clock combining and transmitting module 110 includes n common-mode processing units, for example: the common mode processing unit 112a, the common mode processing unit 112b \8230 \ 8230, and the common mode processing unit 112n. Illustratively, N may be equal to N, i.e. comprising N common-mode processing units, a single common-mode processing unit being used to generate a set of combined signals, and N common-mode processing units generating N sets of combined signals.

Specifically, each common mode processing unit may be connected to one or more differential processing units, and it should be noted that, if a single common mode processing unit is connected to a plurality of differential processing units, polarities of differential clock signals input to the common mode processing unit by the plurality of differential processing units need to be the same.

For example, the common mode processing unit (e.g., the common mode processing unit 112 a) receives Clock + transmitted by the differential processing unit 111b and Data1+ and Data 1-transmitted by the PHY module 120. The common mode processing unit 112a synthesizes Data1+ and Clock + to generate a combined signal ((Data 1 +) + (Clock +)), and the common mode processing unit 112a synthesizes Data 1-and Clock + to generate a combined signal ((Data 1-) + (Clock +)). The other common mode processing units are similar, and are not illustrated here.

It should be noted that, for better explanation in this application, only a single common mode processing unit is taken as an example to describe the generation of a group of combined signals, in other embodiments, the combined signals generated by two or more common mode processing units may be considered as a group of combined signals, that is, for the division of the "group" of combined signals, the multiple combined signals generated by the single common mode processing unit may be considered as a group of combined signals, or the multiple combined signals generated by multiple common mode processing units may be considered as a group of combined signals, which is not limited in this application.

Still referring to fig. 11, after the common mode processing unit 112 (the common mode processing unit 112a, the common mode processing unit 112b \8230; the common mode processing unit 112N) generates N sets of combined signals, the N sets of combined signals may be transmitted through the data lines. For example, in the present application, a single common mode processing unit is connected to one data line of N groups of data lines, and the common mode processing unit 112 transmits the generated X combined signals through X data lines of the group of data lines connected thereto, where each data line is used for transmitting one combined signal.

It should be noted that, in the present application, only the correspondence between N groups of data lines and N groups of combined signals is taken as an example for description, actually, in other embodiments, N groups of combined signals may correspond to 2N groups of data lines, and each group of data lines is connected to a common mode processing unit, that is, the combined signals transmitted on each two groups of data lines may be regarded as a group of combined signals. The present application is not limited.

2) Implementation principle of data receiving equipment end

Specifically, still referring to fig. 11, the data receiving apparatus 200 is configured to receive N sets of combined signals transmitted through the data line, where the N sets of combined signals are subjected to external interference, such as noise interference, during transmission, and therefore, for the data receiving apparatus, each of the N sets of combined signals received by the data receiving apparatus includes an interference signal in addition to the data signal and the clock signal. Specifically, the data receiving device 200 may perform common mode processing and differential processing on the N groups of combined signals to separate out a clock signal, where the frequency of the separated clock signal is the same as that of the clock signal in the N groups of combined signals, and it may also be understood that the frequency of the separated clock signal is the same as that of the clock signal generated by the clock source module 130 in the data sending device 100, and the polarity may be the same or different.

Referring to fig. 11, the data receiving apparatus 200 includes a clock data processing module 210, a PHY module 220, and a filtering module 230. Optionally, the data receiving device 200 may include a transceiver module (not shown), such as an interface chip, for connecting the N groups of data lines and receiving the N groups of combined signals carried on the N groups of data lines. The interface chip may transmit the received N sets of combined signals to the clock data processing module 210.

The clock data processing module 210 includes a plurality of differential processing units 210 (e.g., a differential processing unit 211a, a differential processing unit 211b \8230; a differential processing unit 211 n) and a plurality of common mode processing units 211 (e.g., a common mode processing unit 212a, a common mode processing unit 212b \8230; a common mode processing unit 212 n). It should be noted that the number of the differential processing unit and the common mode processing unit may be the same or different, and the present application is not limited thereto.

Specifically, the common mode processing unit 211 (e.g., the common mode processing unit 212a, the common mode processing unit 212b \8230; the common mode processing unit 212N) is configured to receive N groups of combined signals, perform common mode processing on the X-channel signals in each group of combined signals, and specifically add the X-channel signals, wherein the data signals in the X-channel signals are differential signals, that is, have the same amplitude and opposite polarity, and therefore, after the addition of the X-channel signals, the data signals are cancelled out, and a clock signal and an interference signal with an amplitude increased by X times can be obtained.

For example, the following steps are carried out: the 4 groups of combined signals are respectively: (ii) a combined signal ((Data 1 +) + (Clock +) + interfering (Interference) signal) and a combined signal ((Data 1-) + (Clock +) + (Interference)); the combined signal ((Data 2 +) + (Clock-) + (Interference)) and the combined signal ((Data 2-) + (Clock-) + (Interference)), the combined signal ((Data 3 +) + (Clock-) + (Interference)) and the combined signal ((Data 3-) + (Clock-) + (Interference)), the combined signal ((Data 4 +) + (Clock +) (Interference)) and the combined signal ((Data 4-) + (Clock +) (Interference)) are examples.

Illustratively, the common mode processing unit 212a receives the combined signal ((Data 1 +) (Clock +) + Interference (Interference) signal) and the combined signal ((Data 1-) + (Clock +) (Interference)), and performs common mode processing on the set of combined signals, which may be expressed as:

(2*Clock+)+2*(Interference)＝[(Data1+)+(Clock+)+(Interference)]+[(Data1-)+(Clock+)+(Interference)]

that is, the common mode processing unit 212a performs the common mode processing to obtain a signal ((2 × clock +) +2 × Interference), that is, a clock signal with an amplitude increased by 2 times and an Interference signal with an amplitude increased by 2 times.

The processing procedure of other common mode processing units (such as common mode processing unit 112b, common mode processing unit 112c, and common mode processing unit 112 d) is similar, and can be expressed as:

(2*Clock-)+2*(Interference)＝[(Data2+)+(Clock-)+(Interference)]+[(Data2-)+(Clock-)+(Interference)]

(2*Clock-)+2*(Interference)＝[(Data3+)+(Clock-)+(Interference)]+[(Data3-)+(Clock-)+(nterference)]

(2*Clock+)+2*(Interference)＝[(Data4+)+(Clock+)+(Interference)]+[(Data4-)+(Clock+)+(Interference)]

still referring to fig. 11, the common mode processing unit 212 is connected to the differential processing unit 211, and at the data receiving device 200, the differential processing unit 211 has a different function from the differential processing unit 111 in the data transmitting device 100, the function of the differential processing unit 111 is single-ended to differential, that is, converting a single input signal into multiple differential signals, and the function of the differential processing unit 211 in the data receiving device 200 is differential to single-ended, that is, combining the multiple differential signals into one signal.

Specifically, the differential processing unit 211 includes a plurality of differential processing units, for example, a differential processing unit 211a, a differential processing unit 211b \8230, and a differential processing unit 211N, which is configured to perform multiple iterative differential processing on the N-channel signals output by the common mode processing unit 212 to separate the clock signals. The single differential processing unit may be configured to perform differential processing on the input multiple signals, or may be understood as subtracting the multiple signals to generate and output one signal. In the present application, the plurality of signals input to the differential processing unit are differential signals, i.e., signals having the same amplitude and opposite polarities.

Specifically, referring to fig. 11, the differential processing units 211 connected in a ladder manner include n layers, which are respectively the 1 st layer to the nth layer from left to right, and unlike the data transmission device 100, the ladder manner of the differential processing units in the data reception device 200 is gradually decreased from layer to layer, and the differential processing units in the 1 st layer are used to connect the common mode processing unit 212. In general, the number of differential processing units in the data receiving apparatus 200 is the same as the number of differential processing units in the data transmitting apparatus 100, and the connection manner can be regarded as symmetrical. Optionally, each differential processing unit in the plurality of differential processing units in the layer 1 may be connected to two or more common mode processing units, the number of the connected common mode processing units depends on the processing capability of the differential processing units, and taking a balun as an example, the balun may only input two paths of signals, so that each differential processing unit in the layer 1 may only be connected to two common mode processing units.

Specifically, in the present application, the layer 1 differential processing unit, for example, the differential processing unit 211a, performs differential processing on the multiple signals processed by the common mode processing unit 212, that is, two-by-two subtraction is performed on the multiple signals, since the interference signals in the multiple signals are common mode signals, that is, the frequencies are the same and the polarities are the same, the two-by-two subtraction is performed on the multiple signals, the interference signals are cancelled, and the generated signals include the clock signal with the expanded amplitude, but do not include the interference signals, that is, the interference signals in the combined signal can be filtered out by subtracting the multiple signals. After the differential processing units on the 1 st layer carry out differential processing on the N paths of signals from the common mode processing unit, the signals with the interference signals filtered are transmitted to the differential processing unit on the 2 nd layer connected with the differential processing unit, and the differential processing unit on the 2 nd layer continues to carry out differential processing on the received multiple paths of signals and sequentially circulates until clock signals with amplitude expanded by K times are obtained. It should be noted that K times is a multiple of the clock signal received by the clock data processing module 210.

In one example, when N in the N sets of combined signals is an odd number, K may be expressed as:

where Ceil () represents rounding up.

Alternatively, when N in the N groups of combined signals is an even number, K may be expressed as:

for example, if the Clock data processing module 210 receives 4 sets of combined signals, i.e., N =4, and the Clock signal in 2 sets of combined signals is Clock +, and the Clock signal in the other 2 sets of combined signals is Clock-, i.e., M =2, the amplitude of the Clock signal is expanded by 8 times after multiple iterations of differential processing. For example, if the Clock data processing module 210 receives 3 sets of combined signals, i.e. N =3, and the Clock signal in 1 set of combined signals is Clock +, and the Clock signal in the other 2 sets of combined signals is Clock-, i.e. M =1, after multiple iterations of differential processing, a Clock signal with an amplitude expanded by 8 times can be obtained.

It should be noted that the differential processing described in the present application may actually be understood as subtracting a plurality of signals, and therefore, based on the characteristics of the differential processing unit, the plurality of signals input to the differential processing unit should be differential signals with each other, that is, in the present application, the clock signals in the plurality of signals input to a single differential processing unit should be differential signals with each other.

Still referring to fig. 11, the phy module 220 is configured to process the N groups of combined signals to obtain N data signals, specifically, as described above, the data signals in the X groups of combined signals of the N groups of combined signals are differential signals, i.e., have the same amplitude and opposite polarity, and the interference signal and the clock signal are common signals, i.e., have the same amplitude and same polarity. The processing of the PHY module 220 may be understood as adding the X combined signals of each group of combined signals, thereby filtering the clock signal and the interference signal, and obtaining the data signal with the amplitude expanded by X times. Optionally, the PHY module 220 and the clock data processing module 210 are parallel modules, that is, N groups of combined signals may be processed in parallel.

Still referring to fig. 11, the filtering module 230 is connected to the clock data processing module 210, and configured to perform very narrow-band filtering processing on the clock signal output by the clock data processing module 210, so as to further improve the purity of the clock signal.

In a possible implementation manner, each device in the data sending device and the data receiving device may be integrated in the same chip, or may be an independent device, and are connected through a bus, which is not limited in this application.

In a possible implementation manner, the clock signal may be a single-tone clock signal, that is, a sine wave signal with a single frequency, so that the filter can obtain a better filtering effect.

According to the method and the device, a mode similar to clock direct transmission can be realized, and high-precision frequency synchronization of clock signals among cooperative APs is realized, so that the influence of phase noise on the frequency synchronization performance among the APs is eliminated.

In order that those skilled in the art may better understand the concepts of the present application, specific examples are set forth below.

Fig. 13 is a schematic structural diagram of an exemplary data transmitting device and data receiving device, and fig. 13 illustrates that the differential processing unit in the data transmitting device 100 and the data receiving device 200 is a balun, and the common mode processing unit is an ethernet transformer.

Specifically, the data transmission device 100 includes a clock combination transmission module 110, a clock source 120, and a PHY module 130. The clock combining transmission module 110 includes a differential processing unit 111a, a differential processing unit 111b, a differential processing unit 111c, and a common mode processing unit 112a, a common mode processing unit 112b, a common mode processing unit 112c, a common mode processing unit 112d. The difference processing unit 111a connects the difference processing unit 111b and the difference processing unit 111c. The differential processing unit 111b is connected to the common mode processing unit 112a and the common mode processing unit 112b, and the differential processing unit 111c is connected to the common mode processing unit 112c and the common mode processing unit 112d.

The data transmission apparatus 200 includes therein a clock data processing module 210, a PHY module 220, and a filtering module 230. The clock data processing module 210 includes a differential processing unit 211a, a differential processing unit 211b, a differential processing unit 211c, a common mode processing unit 212a, a common mode processing unit 212b, a common mode processing unit 212c, and a common mode processing unit 212d. The difference processing unit 211c connects the difference processing unit 211a and the difference processing unit 211b. The differential processing unit 211a is connected to the common mode processing unit 212a and the common mode processing unit 212b, and the differential processing unit 211b is connected to the common mode processing unit 212c and the common mode processing unit 212d.

The data transmission device 100 and the data reception device 200 are connected by an ethernet data line, the ethernet data line includes 4 twisted pairs, each twisted pair includes 2 data lines, and each twisted pair is connected to a common mode processing unit.

Referring to fig. 13, specifically, the PHY module 220 receives a data signal: data1, data2, data3, data4. The PHY module 220 generates 4 sets of differential Data signals based on the Data signals Data1, data2, data3, and Data 4: data1+ and Data1-, data2+ and Data2-, data3+ and Data3-, data4+ and Data4-. The PHY module 220 transmits the differential Data signals Data1+ and Data 1-to the common mode processing unit 112a, the differential Data signals Data2+ and Data 2-to the common mode processing unit 112b, the differential Data signals Data3+ and Data 3-to the common mode processing unit 112c, and the differential Data signals Data4+ and Data 4-to the common mode processing unit 112d.

The Clock source module 230 generates a Clock signal Clock + and transmits it to the differential processing unit 111a. The differential processing unit 111a generates Clock + and Clock-, based on Clock +, and transmits Clock + to the differential processing unit 111b and Clock to the differential processing unit 111c.

The differential processing unit 111b generates Clock + and Clock-, based on Clock +, and transmits Clock + to the common mode processing unit 112a and Clock-to the common mode processing unit 112b. The differential processing unit 111b generates Clock-and Clock + based on Clock-, and transmits Clock-to the common mode processing unit 112c, and Clock + to the common mode processing unit 112d.

The common mode processing unit 112a generates combined signals ((Data 1 +) + (Clock +)) and ((Data 1-) + (Clock +)) based on the received Data1+, data1-, and Clock +. The common mode processing unit 112b generates combined signals ((Data 2 +) + (Clock-)) and ((Data 2-) + (Clock-)) based on the received Data2+, data2-, and Clock-. The common mode processing unit 112c generates combined signals ((Data 3 +) + (Clock-)) and ((Data 3-) + (Clock-)) based on the received Data3+, data3-, and Clock-. The common mode processing unit 112d generates combined signals ((Data 4 +) + (Clock +)) and ((Data 4-) + (Clock +)) based on the received Data4+, data4-, and Clock +.

The common mode processing units 112a to 112d transmit the combined signals generated by the respective units to the data receiving device through the corresponding twisted pair.

In the transmission process, the combined signal received by the data receiving equipment also comprises an interference signal under the influence of external interference. Specifically, the combined signals received by the common mode processing unit 212a are ((Data 1 +) (Clock +) + (Interference)) and ((Data 1-) + (Clock +) (Interference)), the combined signals received by the common mode processing unit 212b are ((Data 2 +) (Clock-) + (Interference)) and ((Data 2-) + (Clock-) + (Interference)), and the combined signals received by the common mode processing unit 212c are ((Data 3 +) (Clock-) + (Interference)) and ((Data 3-) + (Clock-) + (Interference)), and the combined signals received by the common mode processing unit 212d are ((Data 4 +) (Clock +) (Interference)) and ((Data 4-) + (Clock +) (Interference)).

The common mode processing units 212a to 212d perform common mode processing on the received combined signals, which can be expressed as:

(2*Clock-)+2*(Interference)＝[(Data3+)+(Clock-)+(Interference)]+[(Data3-)+(Clock-)+(Interference)]

the common mode processing unit 212a and the common mode processing unit 212b transmit the generated signals (2 × clock +) +2 × (Interference) and (2 × clock-) +2 × (Interference), respectively, to the differential processing unit 211a. The common mode processing unit 212c and the common mode processing unit 212d transmit the generated signals (2 × clock +) +2 × and (2 × clock +) +2 × to the differential processing unit 211b, respectively.

The difference processing unit 211a and the difference processing unit 211b perform difference processing on the received signals, which can be expressed as:

4*Clock+＝[(2*Clock+)+2*(Interference)]-[(2*Clock-)+2*(Interference)]

4*Clock-＝[(2*Clock-)+2*(Interference)]-[(2*Clock+)+2*(Interference)]

the differential processing unit 211a and the differential processing unit 211b transmit the generated signals 4 × clock + and 4 × clock-, respectively, to the differential processing unit 211c. The difference processing unit 211c performs difference processing on the received signal, which can be expressed as:

8*Clock＝8*Clock+＝[4*Clock+]–[4*Clock-]

the difference processing unit 211c transmits the obtained Clock signal 8 × Clock to the filtering module 230 for filtering, so as to obtain a Clock signal Clock which is pure and has an amplitude increased by 8 times.

Specifically, the PHY module 220 processes in parallel with the clock data transmission module 210, and the processing of the N groups of combined signals by the PHY module 220 may be represented as:

2*Data1＝[(Data1+)+(Clock+)+(Interference)]–[(Data1-)+(Clock+)+(Interference)]

2*Data2＝[(Data2+)+(Clock-)+(Interference)]–[(Data2-)+(Clock-)+(Interference)]

2*Data3＝[(Data3+)+(Clock-)+(Interference)]–[(Data3-)+(Clock-)+(Interference)]

2*Data4＝[(Data4+)+(Clock+)+(Interference)]–[(Data4-)+(Clock+)+(Interference)]

the PHY module 220 may obtain a data signal with an amplitude that is enlarged by a factor of 2.

Alternatively, the synthesizer in the present application may employ different devices, and several possible implementations are described below:

fig. 14 is a schematic structural diagram of a possible data transmitting device and a data receiving device, where the differential processing unit is a balun, the common mode processing unit is a combiner and a power divider, and specifically, for the data transmitting device, a single power divider may separate a clock signal from the differential processing unit into X clock signals and transmit the X clock signals to X combiners connected thereto, and the combiners may combine a differential data signal from the PHY module and a clock signal from the differential processing unit to obtain a combined signal. For the data receiving device, the single power divider is connected with one data line to receive one path of combined signal on the data line and transmit the combined signal to the combiner connected with the combined signal. The single combiner receives X power dividers connected with the single combiner and is used for carrying out common-mode processing on X-path combined signals from the X power dividers. For details, reference may be made to the above description, which is not repeated here.

Fig. 15 is a schematic structural diagram of a data transmitting device and a data receiving device, where the differential processing unit is a balun and the common mode processing unit is an inductor, and reference may be made to the above for implementation of the data transmitting device and the data receiving device, which are not described herein again.

It should be noted that the differential processing unit and the common mode processing unit may also be other devices or chips that can implement the related functions, and the devices in this application are only exemplary examples, and the application is not limited thereto.

Optionally, another connection manner is provided in the present application, as shown in fig. 16, for example, for the data transmission device 100, the differential processing unit 111a connects the differential processing unit 111b and the differential processing unit 111c, the differential processing unit 111b connects the common mode processing unit 112a and the common mode processing unit 112b, and the differential processing unit 111c connects the common mode processing unit 112b and the common mode processing unit 112c. The processing manners of the common mode processing unit 112a and the common mode processing unit 112c are the same as the above, and are not repeated herein, for example, for the common mode processing unit 112b, it receives the Clock transmitted by the differential processing unit 111 b-and the Clock transmitted by the differential processing unit 111 c-, since the received Clock signals are both Clock-, i.e. the polarities are the same, the common mode processing unit 112b can synthesize the received differential data signals based on any Clock, so as to obtain the combined signal. For further details, reference may be made to the above description and further details will not be described here.

For the data receiving device, the connection mode is symmetrical to the data transmitting device, and the amplitude of the clock signal processed by the data transmitting device is 8 times of the clock signal generated by the clock source module, that is, when N is equal to 3, the clock signal with the same amplitude as that obtained when N =4 can be obtained.

The following explains the application of the present application in different application scenarios with the above principle:

scene one:

in this scenario, an application scenario shown in fig. 9 is taken as an example for explanation, as shown in fig. 17, an interaction schematic diagram between a central baseband and each access point AP (AP 1, AP2, AP 3) in this embodiment is shown, and in fig. 17:

step 101, the central baseband generates N groups of combined signals.

The central baseband is the data transmission device, and the processing method thereof can refer to the above, which is not described herein again.

Step 102, the central baseband sends N groups of combined signals to each AP (AP 1, AP2, AP3, AP 4).

Specifically, the central baseband transmits the combined signal to each AP through a data line between the central baseband and each AP. Optionally, the number of the combined signals sent by the central baseband to each AP may be the same or different, and is not limited in this application.

And 103, carrying out common mode processing and differential processing on the N groups of combined signals by each AP, and separating out clock signals.

Each AP is a data receiving device, and each AP may perform common mode processing and differential processing on the received N groups of signals to obtain a clock signal, and the specific processing manner may refer to the above, which is not described herein again.

Scene two:

in the present application, an application scenario shown in fig. 10 is taken as an example for explanation, fig. 18 is a schematic interaction diagram between access points AP (AP 1, AP2, AP 3) in the embodiment of the present application, and in fig. 18:

in step 201, ap1 generates N sets of combined signals.

In this embodiment, the AP1 is a data transmission device for generating an original clock signal and generating N sets of combined signals based on the original clock signal and the data signal.

For details, reference may be made to the above description and further details will not be described herein.

In step 202, AP1 sends N sets of combined signals to AP 2.

For details, reference may be made to the above description, which is not repeated here.

In step 203, the AP2 performs common mode processing and differential processing on the N groups of combined signals to separate out clock signals.

In step 204, the AP2 generates P sets of combined signals.

Illustratively, AP2 may separate the clock signal based on the N sets of combined signals transmitted by AP 1. Subsequently, the AP2 may generate P groups of combined signals based on the separated clock signals and the acquired data signals.

That is, in the present embodiment, the AP2 can realize the function of the data receiving apparatus as well as the function of the data transmitting apparatus.

It should be noted that the values of P and N may be the same or different, and the application is not limited thereto.

In step 205, AP2 sends P groups of combined signals to AP 3.

In step 206, the AP3 performs common mode processing and differential processing on the P groups of combined signals to separate out clock signals.

Alternatively, if AP3 is the end node in the tandem multi-AP, AP3 may be used only to implement the function of the data receiving device. If the AP3 is connected to another AP as an upstream device, the AP3 may implement the function of the data transmission device, similar to the AP 2.

It should be noted that the data signals received by the APs may be the same or different, and the present application is not limited thereto.

Fig. 19 is a schematic diagram showing a comparison of phase noise variation, including phase noise variation using the clock synchronization method of the present application, phase noise variation not using the clock synchronization method of the present application, for example, phase noise variation using a clock recovery method in the prior art, and phase noise variation of a source clock signal. Referring to fig. 19, the phase noise in the prior art is deteriorated by about 20dB in transmission compared to the phase noise of the source clock, while the phase noise in the present application is not substantially deteriorated.

The above-mentioned scheme provided by the embodiment of the present application is introduced mainly from the perspective of interaction between network elements. It is to be understood that the data transmitting apparatus and the data receiving apparatus contain corresponding hardware structures and/or software modules for performing the respective functions in order to realize the above functions. Those of skill in the art will readily appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiment of the present application, the data sending device and the data receiving device may be divided into function modules according to the method example, for example, each function module may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. It should be noted that, in the embodiment of the present application, the division of the module is schematic, and is only one logic function division, and there may be another division manner in actual implementation.

In the case of dividing each functional module by corresponding functions, fig. 20 shows a schematic diagram of a possible structure of the data receiving apparatus 300 according to the foregoing embodiment, and as shown in fig. 20, the data receiving apparatus 300 may include: a transceiver module 301 and a processing module 302.

In one example, the transceiver module 301 may be configured to perform a step of "receiving N groups of combined signals transmitted by the data transmitting apparatus", where each group of the N groups of combined signals includes X paths of combined signals; each of the X combined signals includes a data signal, a noise signal, and a clock signal. The data signals of the X-path combined signals in each group of combined signals are differential signals, and the noise signals in the X-path combined signals in each group of combined signals are common-mode signals; in the N groups of combined signals, the clock signal of the M groups of combined signals is a first clock signal, the clock signal of the N-M groups of combined signals is a second clock signal, and the first clock signal and the second clock signal are differential signals. For example, the transceiver module 301 may be configured to support the data receiving device to perform steps 102, 202, and 205 in the above method embodiments. The processing module 302 is configured to perform a step of performing common-mode processing and differential processing on the N groups of combined signals to separate out a clock signal, where the clock signal has the same frequency as the first clock signal and the second clock signal. For example, the processing module 302 may be configured to support the data receiving device to perform step 103, step 203, step 206 in the above method embodiments.

In a possible implementation manner, the processing module 302 may be specifically configured to perform common mode processing on the X signals in each group of combined signals to obtain M first signals and (N-M) second signals, where the first signals include a first clock signal with an amplitude increased by X times and a noise signal with an amplitude increased by X times, and the second signals include a second clock signal with an amplitude increased by X times and a noise signal with an amplitude increased by X times. And the data receiving equipment carries out multiple iterative difference processing on the M paths of first signals and the (N-M) paths of second signals to obtain clock signals, wherein the amplitude of the clock signals is K times of that of the first clock signals or the second clock signals.

In a possible implementation manner, if N =4,m =2, the processing module 302 may be specifically configured to subtract two by two the 2 paths of the first signal and the 2 paths of the second signal to obtain a third clock signal and a fourth clock signal, where an amplitude of the third clock signal is 2 times an amplitude of the first clock signal, an amplitude of the fourth clock signal is 2 times an amplitude of the second clock signal, and the third clock signal and the fourth clock signal are differential signals; the data receiving apparatus subtracts the third clock signal from the fourth clock signal to obtain a clock signal, the clock signal has the same frequency as the third clock signal and the fourth clock signal, the clock signal has the same phase as the third clock signal or the fourth clock signal, and the amplitude of the clock signal is 2 times the amplitude of the third clock signal or the fourth clock signal.

In a possible implementation manner, the processing module 302 is further configured to generate, by the data receiving device, P groups of combined signals in response to the acquired P groups of data signals and clock signals, where each group of combined signals in the P groups of combined signals includes Q paths of combined signals; each path of combined signal in the Q paths of combined signals comprises a data signal and a clock signal; the data signals of the Q paths of combined signals in each group of combined signals are differential signals; in the P groups of combined signals, the clock signal of the L groups of combined signals is a third clock signal, the clock signal of the (P-L) groups of combined signals is a fourth clock signal, and the frequencies of the third clock signal and the fourth clock signal are the same as the frequency of the clock signal. The transceiving module 301 is further configured to transmit the P-group combined signal to the second data receiving device.

In a possible implementation manner, the data receiving apparatus further includes a filtering module 303, configured to perform a very narrow-band filtering process on the clock signal.

In a possible implementation manner, the processing module 302 is further configured to subtract the X-path combined signals in each group of combined signals, and separate the data signals in each group of combined signals.

In one possible implementation, the clock signal is a single-tone clock signal.

Fig. 21 is a schematic diagram illustrating a possible structure of the data transmission apparatus 400 according to the foregoing embodiment, and as shown in fig. 21, the data transmission apparatus 400 may include: a processing module 401 and a transceiver module 402.

In one example, the processing module 401 is configured to perform a step of "generating N groups of combined signals in response to the acquired N groups of data signals and the original clock signal", where each group of the N groups of combined signals includes an X-path combined signal; each of the X combined signals includes a data signal and a clock signal. The data signals of the X-path combined signals in each group of combined signals are differential signals; in the N groups of combined signals, the clock signal of the M groups of combined signals is a first clock signal, the clock signal of the (N-M) groups of combined signals is a second clock signal, and the frequencies of the first clock signal and the second clock signal are the same as the frequency of the original clock signal. For example, the processing module 401 may be configured to support the data sending apparatus to perform step 101, step 201, and step 204 in the above method embodiments. The transceiver module 402 may be configured to perform the step of "transmitting N groups of combined signals to the data receiving device", for example, the transceiver module 402 may be configured to support the data transmitting device to perform the steps 102, 202, and 205 in the above method embodiments.

In a possible implementation manner, the processing module 401 is specifically configured to generate M paths of first clock signals and (N-M) paths of second clock signals in response to an obtained original clock signal; the data transmission equipment synthesizes the M paths of first clock signals with M groups of data signals in the N groups of data signals to generate M groups of combined signals; and, the (N-M) second clock signals are combined with the (N-M) group data signals in the N group data signals to generate (N-M) group combined signals.

An apparatus provided by an embodiment of the present application is described below. As shown in fig. 22:

fig. 22 is a schematic structural diagram of a communication device according to an embodiment of the present application. As shown in fig. 22, the communication device 500 may include: a processor 501, a transceiver 505, and optionally a memory 502.

The transceiver 505 may be referred to as a transceiving unit, a transceiver, or a transceiving circuit, etc. for implementing transceiving function. The transceiver 505 may include a receiver and a transmitter, and the receiver may be referred to as a receiver or a receiving circuit, etc. for implementing a receiving function; the transmitter may be referred to as a transmitter or a transmission circuit, etc. for implementing the transmission function.

The memory 502 may have stored therein computer programs or software codes or instructions 504, which computer programs or software codes or instructions 504 may also be referred to as firmware. The processor 501 may control the MAC layer and the PHY layer by running a computer program or software code or instructions 503 therein or by calling a computer program or software code or instructions 504 stored in the memory 502 to implement the OM negotiation method provided by the embodiments described below in the present application. The processor 501 may be a Central Processing Unit (CPU), and the memory 502 may be, for example, a read-only memory (ROM) or a Random Access Memory (RAM).

The processor 501 and transceiver 505 described herein may be implemented on an Integrated Circuit (IC), an analog IC, a Radio Frequency Integrated Circuit (RFIC), a mixed signal IC, an Application Specific Integrated Circuit (ASIC), a Printed Circuit Board (PCB), an electronic device, or the like.

The communication device 500 may further include an antenna 506, and the modules included in the communication device 500 are only for illustration and are not limited in this application.

As described above, the communication apparatus in the above description of the embodiment may be an access point or a station, but the scope of the communication apparatus described in the present application is not limited thereto, and the structure of the communication apparatus may not be limited by fig. 22. The communication means may be a stand-alone device or may be part of a larger device. For example, the communication device may be implemented in the form of:

(1) A stand-alone integrated circuit IC, or chip, or system-on-chip or subsystem; (2) A set of one or more ICs, which optionally may also include storage components for storing data, instructions; (3) modules that may be embedded within other devices; (4) Receivers, smart terminals, wireless devices, handsets, mobile units, in-vehicle devices, cloud devices, artificial intelligence devices, and the like; (5) others, and so forth.

For the case that the implementation form of the communication device is a chip or a chip system, the schematic structural diagram of the chip shown in fig. 23 can be referred to. The chip shown in fig. 23 includes a processor 601 and an interface 602. The number of the processors 601 may be one or more, and the number of the interfaces 602 may be more. Optionally, the chip or system of chips may include a memory 403.

All relevant contents of each step related to the above method embodiment may be referred to the functional description of the corresponding functional module, and are not described herein again.

Based on the same technical concept, embodiments of the present application further provide a computer-readable storage medium storing a computer program, where the computer program includes at least one code segment that is executable by a data transmission apparatus to control the data transmission apparatus to implement the method embodiments.

Based on the same technical concept, embodiments of the present application further provide a computer-readable storage medium storing a computer program, where the computer program includes at least one code segment that is executable by a data receiving apparatus to control the data receiving apparatus to implement the method embodiments.

Based on the same technical concept, the embodiment of the present application further provides a computer program, which is used to implement the above method embodiments when the computer program is executed by the data transmission device.

Based on the same technical concept, the embodiment of the present application further provides a computer program, which is used to implement the above method embodiments when the computer program is executed by the data receiving device.

The program may be stored in whole or in part on a storage medium packaged with the processor, or in part or in whole on a memory not packaged with the processor.

Based on the same technical concept, the embodiment of the present application further provides a processor, and the processor is configured to implement the above method embodiment. The processor may be a chip.

Based on the same technical concept, the embodiment of the present application further provides a communication system, where the communication system includes the data sending device and the data receiving device in the foregoing method embodiments.

The steps of a method or algorithm described in connection with the disclosure of the embodiments disclosed herein may be embodied in hardware or may be embodied in software instructions executed by a processor. The software instructions may be comprised of corresponding software modules that may be stored in Random Access Memory (RAM), flash Memory, read Only Memory (ROM), erasable Programmable Read Only Memory (EPROM), electrically Erasable Programmable Read Only Memory (EEPROM), registers, a hard disk, a removable disk, a compact disc Read Only Memory (CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. Of course, the storage medium may also be integral to the processor. The processor and the storage medium may reside in an ASIC. Additionally, the ASIC may reside in a network device. Of course, the processor and the storage medium may reside as discrete components in a network device.

Those skilled in the art will recognize that, in one or more of the examples described above, the functions described in the embodiments of the present application may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.

While the present embodiments have been described with reference to the accompanying drawings, it is to be understood that the invention is not limited to the precise embodiments described above, which are meant to be illustrative and not restrictive, and that various changes may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. The data receiving equipment is characterized in that the data receiving equipment is connected with data sending equipment through N groups of data lines, and the data receiving equipment comprises a transceiving module and a clock data processing module;

the transceiver module is configured to receive N groups of combined signals sent by the data sending device through the N groups of data lines, where each group of combined signals in the N groups of combined signals includes an X-path combined signal; each path of combined signal in the X paths of combined signals comprises a data signal, a noise signal and a clock signal;

the data signals of the X-path combined signals in each group of combined signals are differential signals, and the noise signals in the X-path combined signals in each group of combined signals are common-mode signals;

in the N groups of combined signals, the clock signal of the M groups of combined signals is a first clock signal, the clock signal of the N-M groups of combined signals is a second clock signal, and the first clock signal and the second clock signal are differential signals;

the clock data processing module is configured to perform common mode processing and differential processing on the N groups of combined signals and separate a clock signal, where the frequency of the clock signal is the same as that of the first clock signal and that of the second clock signal;

the clock data processing module comprises at least one common mode processing unit and at least one differential processing unit;

the common mode processing unit is configured to perform common mode processing on X signals in each group of combined signals to obtain M first signals and (N-M) second signals, where the first signals include a first clock signal whose amplitude is increased by X times and the noise signals whose amplitude is increased by X times, and the second signals include the second clock signal whose amplitude is increased by X times and the noise signals whose amplitude is increased by X times;

the differential processing unit is configured to perform multiple iterative differential processing on the M paths of first signals and the (N-M) paths of second signals, cancel the noise signal, and obtain the clock signal, where an amplitude of the clock signal is K times an amplitude of the first clock signal or the second clock signal;

the clock signal is a single tone clock signal.

2. The apparatus of claim 1, wherein the common mode processing unit comprises:

at least one of a transformer, a power divider, a combiner and an inductor.

3. The device according to claim 1, wherein N =4, m =2, and wherein the difference processing unit is specifically configured to:

the method comprises the steps of combining and subtracting two paths of 2 first signals and two paths of 2 second signals to obtain a third clock signal and a fourth clock signal, wherein the amplitude of the third clock signal is 2 times that of the first clock signal, the amplitude of the fourth clock signal is 2 times that of the second clock signal, and the third clock signal and the fourth clock signal are differential signals;

subtracting a fourth clock signal from the third clock signal to obtain the clock signal, where the frequency of the clock signal is the same as that of the third clock signal and that of the fourth clock signal, the phase of the clock signal is the same as that of the third clock signal or that of the fourth clock signal, and the amplitude of the clock signal is 2 times that of the third clock signal or that of the fourth clock signal.

4. The device of claim 1, wherein the data receiving device is connected to a second data receiving device via a P-group data line, the data receiving device further comprising a clock combining transmission module;

the clock combination transmission module is used for responding to the acquired P groups of data signals and the clock signals and generating P groups of combination signals, wherein each group of combination signals in the P groups of combination signals comprises Q paths of combination signals; each path of combined signal in the Q paths of combined signals comprises a data signal and a clock signal;

the data signals of the Q paths of combined signals in each group of combined signals are differential signals; in the P groups of combined signals, the clock signal of the L groups of combined signals is a third clock signal, the clock signal of the (P-L) groups of combined signals is a fourth clock signal, and the frequencies of the third clock signal, the fourth clock signal and the clock signal are the same;

the transceiver module is configured to send the P groups of combined signals to the second data receiving device through the P groups of data lines.

5. The device according to any one of claims 1 to 4, wherein the data receiving device further comprises a filtering module for performing a very narrow band filtering process on the clock signal.

6. The device according to any one of claims 1 to 4, wherein the data receiving device further comprises a physical layer (PHY) module, configured to subtract the X combined signals in each group of combined signals, and separate the data signal in each group of combined signals.

7. The data sending equipment is characterized by being connected with data receiving equipment through N groups of data lines and comprising a transceiving module and a clock combined transmission module;

the clock combination transmission module is used for responding to the acquired N groups of data signals and the original clock signal to generate N groups of combination signals, wherein each group of combination signals in the N groups of combination signals comprises X-path combination signals; each path of combined signal in the X paths of combined signals comprises a data signal, a noise signal and a clock signal;

the data signals of the X-path combined signals in each group of combined signals are differential signals, and the noise signals in the X-path combined signals in each group of combined signals are common-mode signals; in the N groups of combined signals, the clock signal of M groups of combined signals is a first clock signal, the clock signal of (N-M) groups of combined signals is a second clock signal, and the frequencies of the first clock signal and the second clock signal are the same as the frequency of the original clock signal;

the transceiver module is configured to send the N groups of combined signals to the data receiving device through the N groups of data lines;

the data receiving device is configured to perform common mode processing on the X-path combined signals in each group of combined signals to obtain M-path first signals, and (N-M) -path second signals, and configured to perform multiple iterative differential processing on the M-path first signals and the (N-M) -path second signals to cancel the noise signals, so as to obtain the clock signal, where an amplitude of the clock signal is K times an amplitude of the first clock signal or the second clock signal; wherein the first signal comprises a first clock signal with amplitude increased by X times and the noise signal with amplitude increased by X times, and the second signal comprises the second clock signal with amplitude increased by X times and the noise signal with amplitude increased by X times;

the clock signal is a single tone clock signal.

8. The apparatus of claim 7, wherein the clock combining transmission module comprises at least one common mode processing unit and at least one differential processing unit;

the differential processing unit is further configured to generate M paths of the first clock signals and (N-M) paths of the second clock signals in response to the acquired original clock signals;

the common mode processing unit is used for synthesizing the M paths of first clock signals with M groups of data signals in the N groups of data signals to generate M groups of combined signals; and synthesizing the (N-M) paths of the second clock signal with (N-M) groups of data signals in the N groups of data signals to generate the (N-M) groups of combined signals.

9. A clock signal synchronization method applied to a data receiving device includes:

receiving N groups of combined signals sent by data sending equipment, wherein each group of combined signals in the N groups of combined signals comprises X-path combined signals; each path of combined signal in the X paths of combined signals comprises a data signal, a noise signal and a clock signal;

carrying out common mode processing and differential processing on the N groups of combined signals, and separating out clock signals, wherein the frequency of the clock signals is the same as that of the first clock signal and that of the second clock signal;

wherein, the common mode processing and the differential processing are carried out on the N groups of combined signals, and a clock signal is separated out, and the method comprises the following steps:

performing common mode processing on the X-path signals in each group of combined signals to obtain M-path first signals and (N-M) path second signals, wherein the first signals comprise first clock signals with amplitude increased by X times and noise signals with amplitude increased by X times, and the second signals comprise the second clock signals with amplitude increased by X times and the noise signals with amplitude increased by X times;

carrying out multiple iterative difference processing on the M paths of first signals and the (N-M) paths of second signals to offset the noise signals to obtain the clock signals, wherein the amplitude of the clock signals is K times of that of the first clock signals or the second clock signals;

the clock signal is a single-tone clock signal.

10. The method of claim 9, wherein N =4,m =2, and wherein performing a plurality of iterative difference processes on the M first signals and the (N-M) second signals comprises:

subtracting the two combinations of the 2 paths of first signals and the 2 paths of second signals to obtain a third clock signal and a fourth clock signal, wherein the amplitude of the third clock signal is 2 times of the amplitude of the first clock signal, the amplitude of the fourth clock signal is 2 times of the amplitude of the second clock signal, and the third clock signal and the fourth clock signal are differential signals;

11. The method of claim 9, further comprising:

generating P groups of combined signals in response to the acquired P groups of data signals and the clock signal, wherein each group of combined signals in the P groups of combined signals comprises Q paths of combined signals; each path of combined signal in the Q paths of combined signals comprises a data signal and a clock signal;

and transmitting the P groups of combined signals to a second data receiving device.

12. The method according to any one of claims 9 to 11, further comprising:

and carrying out extremely narrow-band filtering processing on the clock signal.

13. The method according to any one of claims 9 to 11, further comprising:

and subtracting the X-path combined signals in each group of combined signals to separate the data signals in each group of combined signals.

14. A clock signal synchronization method applied to a data transmission apparatus, comprising:

generating N groups of combined signals in response to the acquired N groups of data signals and an original clock signal, wherein each group of combined signals in the N groups of combined signals comprises an X-path combined signal; each path of combined signal in the X paths of combined signals comprises a data signal, a noise signal and a clock signal;

transmitting the N groups of combined signals to a data receiving device;

the data receiving device is configured to perform common mode processing on the X-path combined signals in each group of combined signals to obtain M-path first signals, and (N-M) -path second signals, and configured to perform multiple iterative differential processing on the M-path first signals and the (N-M) -path second signals to cancel the noise signals, so as to obtain the clock signal, where an amplitude of the clock signal is K times an amplitude of the first clock signal or the second clock signal; the first signal comprises a first clock signal with amplitude increased by X times and the noise signal with amplitude increased by X times, and the second signal comprises a second clock signal with amplitude increased by X times and the noise signal with amplitude increased by X times;

the clock signal is a single tone clock signal.

15. The method of claim 14, wherein generating N sets of combined signals comprises:

generating M paths of the first clock signals and (N-M) paths of the second clock signals in response to the acquired original clock signals;

synthesizing the M paths of first clock signals with M groups of data signals in the N groups of data signals to generate M groups of combined signals; and synthesizing the (N-M) paths of the second clock signals with (N-M) groups of data signals in the N groups of data signals to generate the (N-M) groups of combined signals.

16. A chip, wherein the chip comprises at least one processor and an interface;

the interface is used for inputting N groups of combined signals sent by the data sending equipment to the processor, and each group of combined signals in the N groups of combined signals comprises X-path combined signals; each path of combined signal in the X paths of combined signals comprises a data signal, a noise signal and a clock signal;

the processor is configured to perform common mode processing and differential processing on the N groups of combined signals, and separate out a clock signal, where the frequency of the clock signal is the same as that of the first clock signal and that of the second clock signal;

the processor is configured to perform common mode processing on the X-path signals in each group of combined signals to obtain M-path first signals and (N-M) -path second signals, where the first signals include a first clock signal whose amplitude is increased by X times and the noise signal whose amplitude is increased by X times, and the second signals include the second clock signal whose amplitude is increased by X times and the noise signal whose amplitude is increased by X times;

the processor is further configured to perform multiple iterative difference processing on the M paths of first signals and the (N-M) paths of second signals to cancel the noise signals, so as to obtain the clock signal, where the amplitude of the clock signal is K times of the amplitude of the first clock signal or the amplitude of the second clock signal;

the clock signal is a single-tone clock signal.

17. The chip of claim 16, wherein N =4, m =2, and wherein the processor is configured to:

and subtracting a fourth clock signal from the third clock signal to obtain the clock signal, wherein the frequency of the clock signal is the same as that of the third clock signal, the frequency of the clock signal is the same as that of the fourth clock signal, the phase of the clock signal is the same as that of the third clock signal or the fourth clock signal, and the amplitude of the clock signal is 2 times that of the third clock signal or the fourth clock signal.

18. The chip of claim 16,

the processor is further configured to generate P groups of combined signals in response to the acquired P groups of data signals and the clock signal, where each group of combined signals in the P groups of combined signals includes Q paths of combined signals; each path of combined signal in the Q paths of combined signals comprises a data signal and a clock signal;

the interface is used for sending the P group combined signals to a second data receiving device.

19. The chip according to any of claims 16 to 18,

and the processor is used for carrying out extremely narrow-band filtering processing on the clock signal.

20. The chip according to any of claims 16 to 18,

and the processor is used for subtracting the X-path combined signals in each group of combined signals to separate the data signals in each group of combined signals.

21. A chip, wherein the chip comprises at least one processor and an interface;

the processor is used for responding to the acquired N groups of data signals and original clock signals and generating N groups of combined signals, wherein each group of combined signals in the N groups of combined signals comprises X-path combined signals; each path of combined signal in the X paths of combined signals comprises a data signal, a noise signal and a clock signal;

the interface is used for sending the N groups of combined signals to data receiving equipment;

the clock signal is a single-tone clock signal.

22. The chip of claim 21,

the processor is configured to generate M paths of the first clock signals and (N-M) paths of the second clock signals in response to the obtained original clock signals;

the processor is further configured to combine the M channels of the first clock signal with M groups of data signals in the N groups of data signals, and generate the M groups of combined signals; and synthesizing the (N-M) paths of the second clock signals with (N-M) groups of data signals in the N groups of data signals to generate the (N-M) groups of combined signals.