CN113676819A

CN113676819A - Soft mute control circuit, soft mute control method and device

Info

Publication number: CN113676819A
Application number: CN202111226869.4A
Authority: CN
Inventors: 方雨; 柯毅; 陈银茂
Original assignee: Wuhan Silicon Integrated Co Ltd
Current assignee: Wuhan Silicon Integrated Co Ltd
Priority date: 2021-10-21
Filing date: 2021-10-21
Publication date: 2021-11-19
Anticipated expiration: 2041-10-21
Also published as: CN113676819B

Abstract

The embodiment of the application discloses a soft mute control circuit, a soft mute control method and equipment, wherein the soft mute control circuit comprises a first logic processing circuit and a second logic processing circuit; the first logic processing circuit is used for receiving preset soft mute time, a soft mute control signal and a soft mute enable signal and generating a target soft mute signal according to the preset soft mute time, the soft mute control signal and the soft mute enable signal; and the second logic processing circuit is used for receiving the input audio signal, the soft mute enabling signal and the target soft mute signal, and performing soft mute control on the input audio signal according to the target soft mute signal to obtain an output audio signal when the soft mute enabling signal indicates that the soft mute enabling control function is started. Therefore, by controlling the falling time and the rising time of the soft mute of the electronic equipment, not only the noise interference to the user can be reduced, but also the accurate control of the soft mute time can be realized.

Description

Soft mute control circuit, soft mute control method and device

Technical Field

The present application relates to the field of audio signal processing technologies, and in particular, to a soft mute control circuit, a soft mute control method, and a device.

Background

Sound, one of the most basic signals of nature, is ubiquitous in daily life of people, and electronic devices such as mobile phones, telephones, computers, televisions, and stereos cannot spread sound. Nowadays, listening to music, watching movies and watching television are daily relaxing ways, so that pursuing more excellent sound quality is one of the important subjects at present.

Wherein, sound has high or low, and from the mathematical form, the amplitude of sound signal has big or small. The noise is large at the moment of switching on and off the loudspeakers, which affects the listening experience of the listener. The advent of soft mute (soft mute) technology could solve this problem. However, in the existing soft mute technology, digital logic devices such as an adder, a multiplier, a data selector, a delayer and the like are adopted, although the circuit is simple, the soft mute time is long, and the drop time cannot be accurately controlled, which brings a certain difficulty to accurately control the loudspeaker.

Disclosure of Invention

The application provides a soft mute control circuit, a soft mute control method and equipment, which not only can reduce noise interference to users, but also can realize accurate control of soft mute time of electronic equipment.

In order to achieve the purpose, the technical scheme of the application is realized as follows:

in a first aspect, an embodiment of the present application provides a soft mute control circuit, where the soft mute control circuit includes a first logic processing circuit and a second logic processing circuit; the first logic processing circuit is used for receiving preset soft mute time, a soft mute control signal and a soft mute enable signal and generating a target soft mute signal according to the preset soft mute time, the soft mute control signal and the soft mute enable signal;

and the second logic processing circuit is used for receiving the input audio signal, the soft mute enabling signal and the target soft mute signal, and performing soft mute control on the input audio signal according to the target soft mute signal to obtain an output audio signal when the soft mute enabling signal indicates that the soft mute enabling control function is started.

In a second aspect, an embodiment of the present application provides a soft mute control method, including:

determining a preset soft mute time, a soft mute control signal, a soft mute enable signal and an input audio signal;

performing logic processing according to the preset soft mute time, the soft mute control signal and the soft mute enable signal to generate a target soft mute signal;

and when the soft mute enable signal indicates to start the soft mute enable control function, performing soft mute control on the input audio signal by using the target soft mute signal to obtain an output audio signal.

In a third aspect, an embodiment of the present application provides an electronic device, which includes at least the soft mute control circuit and the audio apparatus as described in the first aspect.

The soft mute control circuit comprises a first logic processing circuit and a second logic processing circuit; the first logic processing circuit is used for receiving preset soft mute time, a soft mute control signal and a soft mute enable signal and generating a target soft mute signal according to the preset soft mute time, the soft mute control signal and the soft mute enable signal; and the second logic processing circuit is used for receiving the input audio signal, the soft mute enabling signal and the target soft mute signal, and performing soft mute control on the input audio signal according to the target soft mute signal to obtain an output audio signal when the soft mute enabling signal indicates that the soft mute enabling control function is started. Therefore, the first logic processing circuit and the second logic processing circuit control the falling time and the rising time of the soft mute of the electronic equipment, so that not only can the noise interference on users be reduced, but also the accurate control of the soft mute time can be realized.

Drawings

Fig. 1 is a schematic structural diagram of a soft mute control circuit according to an embodiment of the present disclosure;

fig. 2 is a hardware circuit diagram of a second logic processing circuit according to an embodiment of the present disclosure;

fig. 3 is a hardware circuit diagram of a first logic processing circuit according to an embodiment of the present disclosure;

fig. 4A is a schematic diagram illustrating a variation trend of a target soft mute signal when a sound is turned off according to an embodiment of the present application;

fig. 4B is a schematic diagram illustrating a variation trend of a target soft mute signal when a sound is turned on according to an embodiment of the present application;

fig. 5 is a hardware circuit diagram of another first logic processing circuit according to an embodiment of the present disclosure;

fig. 6 is a hardware circuit diagram of a first logic processing circuit according to an embodiment of the present disclosure;

fig. 7A is a schematic diagram illustrating a variation trend of a target soft mute signal when a sound is turned off according to an embodiment of the present application;

fig. 7B is a schematic diagram illustrating a variation trend of a target soft mute signal when a sound is turned on according to an embodiment of the present application;

FIG. 8 is a timing diagram of a logic processing sub-circuit according to an embodiment of the present application;

fig. 9 is a schematic diagram of a hardware structure of a soft mute control circuit according to an embodiment of the present disclosure;

fig. 10 is a schematic flowchart of a soft mute control method according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

So that the manner in which the features and elements of the present embodiments can be understood in detail, a more particular description of the embodiments, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the application.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict. It should also be noted that reference to the terms "first \ second \ third" in the embodiments of the present application is only used for distinguishing similar objects and does not represent a specific ordering for the objects, and it should be understood that "first \ second \ third" may be interchanged with a specific order or sequence where possible so that the embodiments of the present application described herein can be implemented in an order other than that shown or described herein.

Sound, one of the most basic signals of nature, is ubiquitous in daily life of people, and electronic devices such as mobile phones, telephones, computers, televisions, and stereos cannot spread sound. Nowadays, listening to music, watching movies and watching television are daily relaxing ways, so that pursuing more excellent sound quality is one of the important subjects at present. The sound has high or low, and mathematically speaking, the amplitude of the sound signal has large or small. The noise will be larger at the moment of starting and closing the horn, which will affect the listening feeling of the listener. The soft mute (soft mute) technology can solve the problem, and the specific method is that when the loudspeaker is turned on, in order to obtain higher hearing and reduce noise, the system controls the audio signal to gradually and smoothly rise; when the loudspeaker is closed, the system controls the audio signal to gradually and smoothly drop, so that the discomfort of a listener is reduced.

The soft mute technology is to adopt a gradually decreasing strategy when the mute is turned on to control the gradient pull-down of the loudspeaker. The traditional soft mute technology adopts digital logic devices such as an adder, a multiplier, a data selector, a delayer and the like, has the advantages of simple circuit, long soft mute time and incapability of accurately controlling the descending time, and brings certain trouble to accurately controlling a loudspeaker.

Based on this, the embodiment of the present application provides a soft mute control circuit, which includes a first logic processing circuit and a second logic processing circuit; the first logic processing circuit is used for receiving preset soft mute time, a soft mute control signal and a soft mute enable signal and generating a target soft mute signal according to the preset soft mute time, the soft mute control signal and the soft mute enable signal; and the second logic processing circuit is used for receiving the input audio signal, the soft mute enabling signal and the target soft mute signal, and performing soft mute control on the input audio signal according to the target soft mute signal to obtain an output audio signal when the soft mute enabling signal indicates that the soft mute enabling control function is started. Therefore, the first logic processing circuit and the second logic processing circuit control the falling time and the rising time of the soft mute of the electronic equipment, so that not only can the noise interference on users be reduced, but also the accurate control of the soft mute time can be realized.

Embodiments of the present application will be described in detail below with reference to the accompanying drawings.

In an embodiment of the present application, referring to fig. 1, a schematic diagram of a composition structure of a soft mute control circuit provided in an embodiment of the present application is shown. As shown in fig. 1, soft mute control circuit 10 may comprise a first logic processing circuit 101 and a second logic processing circuit 102; the first logic processing circuit 101 is configured to receive a preset soft mute time, a soft mute control signal, and a soft mute enable signal, and generate a target soft mute signal according to the preset soft mute time, the soft mute control signal, and the soft mute enable signal;

the second logic processing circuit 102 is configured to receive an input audio signal, the soft mute enable signal, and the target soft mute signal, and perform soft mute control on the input audio signal according to the target soft mute signal when the soft mute enable signal indicates to turn on a soft mute enable control function, so as to obtain an output audio signal.

It should be noted that the soft mute technique may refer to that when an audio device (e.g., a speaker, a loudspeaker, etc.) is turned on, the soft mute control circuit 10 may control the audio signal to smoothly rise at this time in order to obtain a higher listening feeling and reduce noise; when the audio device is turned off, the soft mute control circuit 10 can control the audio signal to drop smoothly, so as to realize the accurate control of the soft mute time of the audio device.

Specifically, in the soft mute control circuit 10, a target soft mute signal is obtained by the first logic processing circuit 101, and the target soft mute signal can measure the soft mute process and accurately control the rising and falling time of the soft mute; and according to the target soft mute signal, the second logic processing circuit 102 realizes soft mute control on the input audio signal, so as to obtain the output audio signal, and further realize accurate control on soft mute time.

It should be further noted that, in the embodiment of the present application, the preset soft mute time indicates a soft mute time that needs to be set, and may be configured by a register. The preset soft mute time is expressed by Smtime and used for indicating time control of soft mute completion, the value of the Smtime is optional, the value range of the Smtime can be 0.5 ms-128 ms, and specific setting is carried out according to actual requirements.

It should be further noted that, in the embodiment of the present application, the soft mute control signal may include a first control signal and a second control signal. Wherein, the first control signal represents the soft mute opening and closing control, and the soft mute process is started from 0- - > 1; here, the first control signal is represented by Smute, where the value of Smute is 1, which represents that soft mute is turned on, and the output audio signal slowly drops to 0; the value of Smute is 0, which indicates that soft mute is turned off, and the output audio signal slowly rises to the amplitude of the input audio signal, namely Smute can be regarded as a soft mute switch. In addition, the second control signal may be considered a soft mute fast control switch, denoted by Smute _ slw; when the value of Smute _ slw is 1, it indicates that the linearity rapidly decreases after reaching the lower threshold (e.g., 6%), or that the linearity rapidly increases after reaching the upper threshold (e.g., 94%).

It should be further noted that, in the embodiment of the present application, the soft mute enable signal indicates whether to turn on the soft mute enable control function, which is indicated by Smt _ int _ en; wherein the value of Smt _ int _ en is 1, which indicates that the soft mute enabling control function is started, namely the soft mute is effective; the value of Smt _ int _ en is 0, which means that the soft mute enable control function is turned off, i.e. no soft mute.

It should be further noted that, In the embodiment of the present application, the input audio signal may be denoted by In, and the output audio signal may be denoted by Out. The target soft mute signal may be represented by Smute _ cur, where Smute _ cur is used to represent the ratio of the output audio signal to the input audio signal, which may be a measure of the soft mute process. In addition, in the embodiment of the present application, a soft mute completion flag signal may be further set, which is represented by Mut _ unmute _ fin and may be regarded as a soft mute completion flag; and when the soft mute process is finished, setting the value of Mut _ unmute _ fin to be 1.

In some embodiments, referring to fig. 2, a hardware circuit diagram of a second logic processing circuit is shown for the second logic processing circuit 102. As shown in fig. 2, the second logic processing circuit 102 may include a first multiplier 21, a first selector 22, and a first delay 23; the first multiplier 21 is configured to perform multiplication processing on an input audio signal and a target soft mute signal to obtain a first intermediate signal;

a first selector 22, configured to perform selection processing on the first intermediate signal and the input audio signal according to the soft mute enable signal to obtain a second intermediate signal;

the first delayer 23 is configured to delay the second intermediate signal to obtain an output audio signal.

It should be noted that, in the embodiment of the present application, the multiplier may be used

It is shown that the selector can be represented by MUX and the delay can be represented by z^-1And (4) showing. In addition, the soft mute enable signal is denoted by Smt _ int _ en, the input audio signal is denoted by In, the output audio signal is denoted by Out, and the target soft mute signal is denoted by Smute _ cur.

Further, in some embodiments, the first selector 22 is specifically configured to determine the first intermediate signal as the second intermediate signal when the soft mute enable signal indicates that the soft mute enable control function is turned on; and determining the input audio signal as a second intermediate signal when the soft mute enable signal indicates that the soft mute enable control function is turned off.

In the embodiment of the present application, if the value of the soft mute enable signal is a first value, it is determined that the soft mute enable signal indicates to turn on a soft mute enable control function; and if the value of the soft mute enabling signal is a second value, determining that the soft mute enabling signal indicates to close the soft mute enabling control function.

Here, the first value and the second value are different. Wherein the first value may be 1 and the second value may be 0; alternatively, the first value may be 0 and the second value may be 1; alternatively, the first value may be true and the second value may be false; alternatively, the first value may be false and the second value may be true, but is not limited thereto. Preferably, in the embodiment of the present application, the first value may be 1, and the second value may be 0.

That is, if the value of Smt _ int _ en is 1, that is, the soft mute enable control is turned on, the multiplication processing is performed on the input audio signal and the target soft mute signal, and then the delay processing is performed on the obtained signal, so that the output audio signal can be obtained; if the value of the Smt _ int _ en is 0, that is, the soft mute enable control is turned off, the delayed input audio signal may be determined as the output audio signal. The following will be described in these two application scenarios:

when the value of Smt _ int _ en is 0, it indicates that the soft mute enable control is turned off, i.e., the soft mute is inactive. At this time, since the selection signal of the first selector 22 is 0, the signal of the lower branch (i.e., the input audio signal) is selected; that is, the output audio signal at this time is directly equal to the input audio signal delayed by one sampling interval.

When the value of the Smt _ int _ en is 1, it indicates that the soft mute enable control is turned on, i.e., the soft mute is active. At this time, since the selection signal of the first selector 22 is 1, the signal of the upper branch (i.e., the input audio signal multiplied by the target soft mute signal) is selected, and at this time, the output audio signal is equal to the input audio signal multiplied by a coefficient

Post-delayOne sampling interval.

Specifically, after the soft mute enable control is turned on, when the sound of the audio device is turned off, the control is performed assuming that the input audio signal is unchanged

Gradually decreasing from 1 to 0, the output audio signal will also gradually decrease to 0; when the sound of the audio device is turned on, assuming that the input audio signal is unchanged, control

Gradually rising from 0 to 1, the output audio signal will also gradually rise to 1.

In some embodiments, for the first logic processing circuit 101, refer to fig. 3, which shows a hardware circuit schematic diagram of a first logic processing circuit. As shown in fig. 3, the first logic processing circuit 101 may include a configuration unit 41, a second selector 42, a first adder 43, a second multiplier 44, a second adder 45, a third selector 46, a fourth selector 47, and a second delayer 48; the configuration unit 41 is configured to perform configuration processing on a preset soft mute time to obtain a first parameter value;

a second selector 42, configured to perform selection processing on the first preset signal and the second preset signal according to the first control signal to obtain a third intermediate signal;

a first adder 43, configured to perform subtraction processing on the target soft mute signal and the third intermediate signal to obtain a fourth intermediate signal;

a second multiplier 44, configured to multiply the fourth intermediate signal by the first parameter value to obtain a fifth intermediate signal;

a second adder 45, configured to add the third intermediate signal and the fifth intermediate signal to obtain a first result signal;

a third selector 46, configured to perform selection processing on the first result signal and the temporary output signal according to the second control signal to obtain a sixth intermediate signal;

a fourth selector 47, configured to perform selection processing on the sixth intermediate signal and the first preset signal according to the soft mute enable signal to obtain a seventh intermediate signal;

and a second delayer 48, configured to delay the seventh intermediate signal to obtain the target soft mute signal.

It should be noted that, in the embodiment of the present application, the soft mute control signal includes a first control signal and a second control signal, where the first control signal is denoted by Smute and the second control signal is denoted by Smute _ slw. In addition, the first preset signal is a level signal (denoted by 0) having an amplitude of 0, and the second preset signal is a level signal (denoted by 1) having an amplitude of 1.

It is also noted that the first parameter value (in)aRepresentation) can be determined by the input Smtime, which represents the soft mute time that needs to be set, and can be configured by a register. In particular,

is composed of smitime andfsto further process the soft mute process to enable precise control. In the embodiment of the present application,

is a value close to 1 but less than 1, which is specifically set according to practical circumstances and is not limited in any way.

Exemplarily, the configuration unit 41 is specifically configured to perform configuration processing on the preset soft mute time by using equation (1) to obtain a first parameter value;

（1）

wherein the content of the first and second substances,

represents a first parameter value, Smtime represents a preset soft mute time,fsrepresenting the sampling frequency of the input audio signal. Thus, the configuration unit may also be represented by a function (Func) in fig. 3.

In the embodiment of the application, the Smtime of the input configuration can determine the required soft mute time by controlling the size of a, namely Smute from 0->1 or from 1->Time of 0. Specifically, the value range of Smtime is 0.5 ms-128 ms, and the value of fs is generally 1/(20.8 us) =48KHz, so that Smtime can be obtainedfsIs a larger number and is between 24 and 6144; while the value of log9 is small, according to the characteristics of an exponential function, so

Is a value close to 1 but less than 1.

Further, in some embodiments, the third selector 46 is specifically configured to determine the temporary output signal as a sixth intermediate signal when the value of the second control signal is the first value; and determining the first result signal as a sixth intermediate signal when the value of the second control signal is the second value;

a fourth selector 47, configured to determine the sixth intermediate signal as the seventh intermediate signal when the value of the soft mute enable signal is the first value; and determining the first preset signal as a seventh intermediate signal under the condition that the value of the soft mute enable signal is the second value.

It should be noted that, in the embodiment of the present application, the first value and the second value are different. Preferably, the first value may be 1 and the second value may be 0.

It should be further noted that, in this embodiment of the present application, when the value of the soft mute enable signal is a first value, the value of the second control signal is a second value, and the value of the first control signal is the first value, it is determined that the target soft mute signal is in a power exponent decreasing trend;

and under the condition that the value of the soft mute enable signal is a first value, the value of the second control signal is a second value, and the value of the first control signal is the second value, determining that the target soft mute signal is in a power exponential rising trend.

That is, in the case where the value of smit _ int _ en is 1 and the value of smite _ slw is 0, if the value of smite is 1, the target soft mute signal has a power exponent decreasing trend; if Smute is 0, the target soft mute signal has a power exponential rising trend.

It can be understood that, according to fig. 3, in the case where the value of Smt _ int _ en is 1 and the value of Smute _ slw is 0, since the selection signal of the third selector 46 is 0, the signal of the lower branch (i.e., the first result signal) is selected; and the selection signal of the fourth selector 47 is 1, when the signal of the upper branch (i.e., the signal selected by the third selector 46) is selected; that is, the Smute _ cur at this time is the first Result signal (indicated by Result 1) after the delay processing.

In a specific embodiment, when the value of Smute is 1, this time indicates a process of turning off sound, at this time, the output of the second selector 42 is 0, then the subtraction is performed with the feedback of Smute _ cur, then a is multiplied, Result1 obtained by adding 0 to the Result is added, and Smute _ cur of the next sampling interval is obtained after delay processing; i.e. after a number of samplings

The target soft mute signal of the sub-sampling interval is equal to

First resulting signal of subsampling interval, i.e. equal to

. Thus, due toaLess than 1, with each sampling and performing the iterations,

will gradually approach 0, which can be seen as the time required for the whole soft mute process, and in digital circuits, the operators are fixed, in which case the multiplication of two very small numbers will tend to be more and more towards 0, and will therefore eventually equal 0, with the trend shown in fig. 4A.

In another toolIn the embodiment of the present invention, when the value of Smute is 0, this time indicates the process of turning on the sound, at this time, the output of the second selector 42 is 1, then subtracted from the feedback of Smute _ cur, multiplied by a, the Result added with Result1 obtained by 1, and the Smute _ cur of the next sampling interval is obtained after the delay processing; i.e. after a number of samplings

The target soft mute signal of the sub-sampling interval is equal to

The first result signal of the subsampling interval, i.e. equal to 1-

. Thus, due toaLess than 1, with each sampling for the iterations,

will gradually approach 0, which can be seen as the time required for the whole soft mute process, and in digital circuits, the operators are fixed, in which case the multiplication of two very small numbers will tend more and more towards 0, and therefore eventually to 1, with a trend as shown in fig. 4B.

In some embodiments, for the first logic processing circuit 101, see fig. 5, which shows a hardware circuit schematic diagram of another first logic processing circuit. As shown in fig. 5, the first logic processing circuit 101 may further include a first calculating unit 61, a second calculating unit 62, a first comparator 63, a logic sub-circuit 64, and a fifth selector 65; the first calculating unit 61 is configured to perform score calculation on the first parameter value to obtain a second parameter value;

a second calculating unit 62, configured to perform absolute value calculation on the fourth intermediate signal to obtain an eighth intermediate signal;

the first comparator 63 is configured to compare the eighth intermediate signal with the second parameter value to obtain a ninth intermediate signal;

a logic processing sub-circuit 64 for obtaining a second result signal according to the first result signal, the ninth intermediate signal and the target soft mute signal;

a fifth selector 65, configured to perform selection processing on the first result signal and the second result signal according to the ninth intermediate signal to obtain a temporary output signal.

Further, in some embodiments, for the logic processing sub-circuit 64, as shown in fig. 6, the logic processing sub-circuit 64 may include a logic gate 641, a third adder 642, a sixth selector 643, a seventh selector 644, a third delay 645, and a fourth adder 646; the logic gate 641 is configured to perform a logic operation on the ninth intermediate signal to obtain a tenth intermediate signal;

a third adder 642, configured to subtract the first result signal and the target soft mute signal to obtain an eleventh intermediate signal;

a sixth selector 643, configured to perform selection processing on the eleventh intermediate signal and the output delayed signal according to the tenth intermediate signal, so as to obtain a twelfth intermediate signal;

a seventh selector 644, configured to perform selective processing on the twelfth intermediate signal and the first preset signal according to the soft mute enable signal, to obtain a thirteenth intermediate signal;

a third delay 645, configured to perform delay processing on the thirteenth intermediate signal to obtain an output delayed signal;

a fourth adder 646, configured to add the twelfth intermediate signal and the target soft mute signal to obtain a second result signal.

It should be noted that, in fig. 6, the logic gate 641 may be composed of logic devices such as an inverter, a delay, and an and gate. In addition, Sel5 denotes a ninth intermediate signal, Sel6 denotes a tenth intermediate signal, Out _ delay denotes an output delay signal, Out _ temp denotes a temporary output signal, Result1 denotes a first Result signal, and Result2 denotes a second Result signal, which is obtained by the logic processing sub-circuit 64 through a correlation logic operation.

It should be further noted that after obtaining the first result signal and the second result signal, it may also be determined whether the obtained temporary output signal (i.e., Out temp) is the first result signal or the second result signal according to the selection signal (i.e., Sel 5) of the fifth selector 65.

In some embodiments, the fifth selector 65 is specifically configured to determine the first result signal as the temporary output signal if the ninth intermediate signal takes the first value; and determining the second result signal as the temporary output signal when the ninth intermediate signal takes the second value.

It should be further noted that, in this embodiment of the application, when the value of the soft mute enable signal is the first value, the value of the second control signal is the first value, and the value of the first control signal is the first value, if the value of the ninth intermediate signal is the first value, it is determined that the target soft mute signal is in a power exponent decreasing trend; if the value of the ninth intermediate signal is a second value, determining that the target soft mute signal is in a linear descending trend;

under the condition that the value of the soft mute enable signal is a first value, the value of the second control signal is a first value, and the value of the first control signal is a second value, if the value of the ninth intermediate signal is the first value, determining that the target soft mute signal is in a power exponent rising trend; and if the value of the ninth intermediate signal is the second value, determining that the target soft mute signal is in a linear ascending trend.

That is, when the value of smite is 1 and the value of smite _ slw is 1, if the value of Sel5 is 1, the target soft mute signal has a power exponent decreasing trend; if the value of Sel5 is 0, the target soft mute signal has a linearly decreasing trend. Or when the value of Smute is 0, if the value of Sel5 is 1, the target soft mute signal is in a power exponential rising trend; if the value of Sel5 is 0, the target soft mute signal has a linear rising trend.

It can be understood that, with reference to fig. 6, when the value of smit _ int _ en is 1 and the value of smite _ slw is 1, since the value of smite _ slw is 1, the third selector 46 selects the up-branch signal, that is, the Out _ temp output by the fifth selector 65; for the fifth selector 65, if the value of Sel5 is 1, the fifth selector 65 selects the up-branch signal, i.e., Out _ temp is the first Result signal (Result 1); if Sel5 takes a value of 0, the fifth selector 65 selects the lower branch signal, i.e. Out temp is the second Result signal (Result 2). Here, the value of Sel5 is related to the first comparator 63, and may specifically include:

when Smute is 1, the value of Sel5 is determined

And

is determined by the comparison result of (1); if it is

>=

Then Sel5 takes a value of 1; otherwise Sel5 takes a value of 0. When Smute is 0, the value of Sel5 is determined

And

is determined by the comparison result of (1); if it is

>=

Then Sel5 takes a value of 1; otherwise Sel5 takes a value of 0.

In short, if

>=

Or

>=

Then the value of Sel5 is 1, which means that the change trend of the process is the same as that of Smute _ slw when the value of Smute _ cur is 0 before Smute _ cur rises or falls to the preset threshold (a/16), and the change is exponential. If it is not

<=

Or

<=

Then Sel5 takes a value of 0, which means that the change of Smute _ cur changes in a linear trend after rising or falling to the preset threshold (a/16).

Further, as can be seen from FIG. 6, only when the Sel5 is from 1->When the sampling point is 0, the value of Sel6 is 1, and other sampling points are 0; at this time, the analysis results in

Equal to the difference between the first resulting signal and the target soft mute signal, delayed by one more sampling interval, i.e. second

The output delay signal of the sub-sampling interval being equal to

First result signal of subsampling interval minus first

A target soft mute signal at a sub-sampling interval; and in the case that the value of Sel6 is 0, the output delay signal of each sampling interval obtained by analysis at this time is kept unchanged. A specific timing diagram is shown in FIG. 8, where

After the change-over, the user can,

a constant value is maintained at x (where x is constant negative when the sound is turned off and constant positive when the sound is turned on).

Further, it can also be seen from fig. 6 that for the second Result signal (Result 2), it is equal to the sum of the target soft mute signal and the output delay signal; however, because

Delayed by one sampling interval

Therefore, it is

The target soft mute signal of the sub-sampling interval is equal to

Second result signal of sub-sampling interval, i.e. equal to

The sum of the target soft mute signal for the sub-sampling interval and a constant value x. Therefore, the trend of the change at this time is linearly changed. Fig. 7A is a schematic diagram illustrating a variation trend of a target soft mute signal when a sound is turned off according to another embodiment of the present application, and fig. 7B is a schematic diagram illustrating a variation trend of the target soft mute signal when a sound is turned off according to another embodiment of the present applicationThe application embodiment provides another schematic diagram of the variation trend of the target soft mute signal when the sound is turned on.

In fig. 7A, a thin line indicates a variation trend in the case where the value of Smt _ int _ en is 1 and the value of Smute _ slw is 0, which is a power exponent decreasing trend; the bold line indicates the variation trend when the value of Smt _ int _ en is 1 and the value of Smute _ slw is 1, which falls to the preset threshold value (c)aThe power exponent is still decreased before (coinciding with the thin line) and is decreased to a preset threshold value (aA linear downward trend after/16).

In fig. 7B, a thin line indicates a variation trend in the case where the value of Smt _ int _ en is 1 and the value of Smute _ slw is 0, which is a power exponent increasing trend; the bold line indicates a variation trend in the case where the value of Smt _ int _ en is 1 and the value of Smute _ slw is 1, which rises to a preset threshold value (c)a(16) before it is raised to a predetermined threshold, the trend is raised to a power exponent (coinciding with the thin line) ((aA linear rising trend follows/16).

In addition, the soft mute control circuit 10 according to the embodiment of the present application may further include a soft mute completion indication circuit, which may be configured to receive a fourth intermediate signal (c

Or is or

) A ninth intermediate signal (Sel 5), a second control signal (Smute _ slw) and a soft mute enable signal (Smt _ int _ en), and then finally outputs a soft mute completion indication signal through logic processing of devices such as a selector, a not gate, a comparator and a delay. In the embodiment of the present application, the soft mute completion indication signal may be represented by Mut _ unmute _ fin and set to 1 after the soft mute process is completed.

That is, Mut _ unmute _ fin may indicate whether the soft mute process is complete. When the value of Smute is 1 and the value of Mut _ unmut _ fin is 1, the volume of the audio device is adjusted to be the lowest; when the value of Smute is 0 and the value of Mut _ unmut _ fin is 1, the soft mute control circuit of the audio device adjusts the output audio signal to the amplitude of the input audio signal.

Briefly, referring to fig. 9, a schematic diagram of a hardware structure of a soft mute control circuit provided in an embodiment of the present application is shown. As can be seen from fig. 9, the soft mute control circuit includes a plurality of comparators and data selectors, multipliers, adders, delays, and respective logic gates. The on and off of soft mute can be determined through Smute input, different soft mute time can be configured according to requirements, and soft mute operation can be completed according to the configured time. In addition, the embodiment of the application also has a Mut _ unmut _ fin output which can indicate the completion state of the soft mute process.

That is to say, in the embodiment of the present application, taking a speaker as an example, the design of the speaker power control circuit is implemented by reasonably using digital logic devices including logic gates such as a comparator, a data selector, an adder, a multiplier, and an and gate or an or gate. Compared with the traditional loudspeaker soft mute control technology, the input Smtime is further processed by adding a comparator, a multiplier, a logic gate and other devices to accurately control the soft mute completion time, so that the output audio signal can show power exponent rise or fall, and the further processing is carried out to accurately control the soft mute completion time. In addition, the embodiment of the application can input the soft mute time to be configured, and various soft mute times can be selected, and the soft mute completion state can be indicated through the Mut _ unmut _ fin output.

The embodiment provides a soft mute control circuit, which comprises a first logic processing circuit and a second logic processing circuit; the first logic processing circuit is used for receiving preset soft mute time, a soft mute control signal and a soft mute enable signal and generating a target soft mute signal according to the preset soft mute time, the soft mute control signal and the soft mute enable signal; and the second logic processing circuit is used for receiving the input audio signal, the soft mute enabling signal and the target soft mute signal, and performing soft mute control on the input audio signal according to the target soft mute signal to obtain an output audio signal when the soft mute enabling signal indicates that the soft mute enabling control function is started. Therefore, the first logic processing circuit and the second logic processing circuit control the descending and ascending time of the soft mute of the electronic equipment, thereby not only reducing the noise interference to users, but also realizing the accurate control of the soft mute time; in addition, the soft mute control circuit provided by the embodiment is simple and convenient to implement and high in practicability, and solves the problems of low practicability and inconvenient practical application in the related technology, so that the experience of a user can be improved, and the soft mute control circuit has important market value.

In another embodiment of the present application, referring to fig. 10, a flowchart of a soft mute control method provided in an embodiment of the present application is shown. As shown in fig. 10, the method may include:

s1001: a preset soft mute time, a soft mute control signal, a soft mute enable signal and an input audio signal are determined.

S1002: and carrying out logic processing according to the preset soft mute time, the soft mute control signal and the soft mute enable signal to generate a target soft mute signal.

S1003: and when the soft mute enable signal indicates to start the soft mute enable control function, performing soft mute control on the input audio signal by using the target soft mute signal to obtain an output audio signal.

It should be noted that, when the soft mute control method according to the embodiment of the present application is applied to the soft mute control circuit according to any one of the foregoing embodiments, the soft mute completion time duration can be precisely controlled, so that the output audio signal can show a power exponent rise or fall, and can be further processed to show a linear rise or fall, thereby further precisely controlling the soft mute completion time duration.

In some embodiments, for S1003, the performing soft mute control on the input audio signal by using the target soft mute signal to obtain the output audio signal may include:

multiplying the input audio signal and the target soft mute signal through a first multiplier to obtain a first intermediate signal;

selecting the first intermediate signal and the input audio signal through a first selector and a soft mute enabling signal to obtain a second intermediate signal;

and carrying out delay processing on the second intermediate signal through the first delayer to obtain an output audio signal.

Further, in some embodiments, the performing, by the first selector and the soft mute enable signal, the selection processing on the first intermediate signal and the input audio signal to obtain a second intermediate signal may include:

determining the first intermediate signal as a second intermediate signal when the soft mute enable signal indicates to turn on the soft mute enable control function;

the input audio signal is determined to be the second intermediate signal when the soft mute enable signal indicates that the soft mute enable control function is turned off.

In a specific example, the method may further include: if the value of the soft mute enable signal is a first value, determining that the soft mute enable signal indicates to start the soft mute enable control function; and if the value of the soft mute enable signal is a second value, determining that the soft mute enable signal indicates to close the soft mute enable control function.

That is, if the value of Smt _ int _ en is 1, that is, the soft mute enable control is turned on, the multiplication processing is performed on the input audio signal and the target soft mute signal, and then the delay processing is performed on the obtained signal, so that the output audio signal can be obtained; if the value of the Smt _ int _ en is 0, that is, the soft mute enable control is turned off, the delayed input audio signal may be determined as the output audio signal.

In some embodiments, for S1002, the soft mute control signal comprises a first control signal and a second control signal. Correspondingly, the performing logic processing according to the preset soft mute time, the soft mute control signal and the soft mute enable signal to generate the target soft mute signal may include:

the method comprises the steps that configuration processing is carried out on preset soft mute time through a configuration unit to obtain a first parameter value;

selecting the first preset signal and the second preset signal through a second selector and the first control signal to obtain a third intermediate signal;

subtracting the target soft mute signal and the third intermediate signal by using a first adder to obtain a fourth intermediate signal;

multiplying the fourth intermediate signal and the first parameter value by a second multiplier to obtain a fifth intermediate signal;

adding the third intermediate signal and the fifth intermediate signal by a second adder to obtain a first result signal;

selecting the first result signal and the temporary output signal through a third selector and a second control signal to obtain a sixth intermediate signal;

selecting the sixth intermediate signal and the first preset signal through a fourth selector and the soft mute enable signal to obtain a seventh intermediate signal;

and carrying out delay processing on the seventh intermediate signal through a second delayer to obtain a target soft mute signal.

It should be noted that, in the embodiment of the present application, the soft mute enable signal may be represented by Smt _ int _ en, the target soft mute signal may be represented by Smute _ cur, the first control signal may be represented by Smute, the second control signal may be represented by Smute _ slw, and the first Result signal may be represented by Result 1.

It should be noted that, in the embodiment of the present application, the first preset signal is a level signal with an amplitude of 0 (denoted by 0), and the second preset signal is a level signal with an amplitude of 1 (denoted by 1).

Further, in some embodiments, in a case that the value of the soft mute enable signal is a first value and the value of the second control signal is a second value, the method may further include:

if the value of the first control signal is a first value, determining that the target soft mute signal is decreased in a power exponent;

and if the value of the first control signal is a second value, determining that the target soft mute signal rises in a power exponent manner.

That is, under the condition that the value of Smt _ int _ en is 1 and the value of Smute _ slw is 0, if the value of Smute is 1, the target soft mute signal has a power exponent decreasing trend; if Smute is 0, the target soft mute signal has a power exponential rising trend.

Further, for the determination of the provisional output signal, in some embodiments, the method may further comprise:

performing score calculation on the first parameter value through a first calculating unit to obtain a second parameter value;

calculating the absolute value of the fourth intermediate signal through a second calculating unit to obtain an eighth intermediate signal;

comparing the eighth intermediate signal with the second parameter value through the first comparator to obtain a ninth intermediate signal;

obtaining a second result signal through a logic processing sub-circuit according to the first result signal, the ninth intermediate signal and the target soft mute signal;

and carrying out selection processing on the first result signal and the second result signal through a fifth selector and a ninth intermediate signal to obtain a temporary output signal.

Further, for the determination of the second result signal, the obtaining the second result signal by the logic processing sub-circuit according to the first result signal, the ninth intermediate signal and the target soft mute signal may include:

performing logic operation on the ninth intermediate signal through a logic gate to obtain a tenth intermediate signal;

performing subtraction processing on the first result signal and the target soft mute signal through a third adder to obtain an eleventh intermediate signal;

selectively processing the eleventh intermediate signal and the output delay signal through a sixth selector and a tenth intermediate signal to obtain a twelfth intermediate signal;

selecting the twelfth intermediate signal and the first preset signal through a seventh selector and the soft mute enable signal to obtain a thirteenth intermediate signal;

performing delay processing on the thirteenth intermediate signal through a third delayer to obtain an output delay signal;

and adding the twelfth intermediate signal and the target soft mute signal by a fourth adder to obtain a second result signal.

In the embodiment of the present application, the temporary output signal may be represented by Out _ temp, the first Result signal may be represented by Result1, the second Result signal may be represented by Result2, and the ninth intermediate signal may be represented by Sel 5. Thus, after obtaining the first result signal and the second result signal, it is possible to determine whether the obtained provisional output signal is the first result signal or the second result signal based on the selection signal (i.e., Sel 5) of the fifth selector.

In a possible implementation manner, in a case that the value of the soft mute enable signal is the first value, and the value of the second control signal is the first value, the method may further include:

if the value of the first control signal is the first value and the value of the ninth intermediate signal is the first value, determining that the target soft mute signal is in a power exponent descending trend;

and if the value of the first control signal is a first value and the value of the ninth intermediate signal is a second value, determining that the target soft mute signal is in a linear descending trend.

In another possible embodiment, in the case that the value of the soft mute enable signal is the first value, and the value of the second control signal is the first value, the method may further include:

if the value of the first control signal is the second value and the value of the ninth intermediate signal is the first value, determining that the target soft mute signal is in a power exponent ascending trend;

and if the value of the first control signal is the second value and the value of the ninth intermediate signal is the second value, determining that the target soft mute signal is in a linear ascending trend.

Here, the first value and the second value are different. Preferably, in the embodiment of the present application, the first value is equal to 1, and the second value is equal to 0.

The embodiment provides a soft mute control method, which determines a preset soft mute time, a soft mute control signal, a soft mute enable signal and an input audio signal; performing logic processing according to the preset soft mute time, the soft mute control signal and the soft mute enable signal to generate a target soft mute signal; and when the soft mute enable signal indicates to start the soft mute enable control function, performing soft mute control on the input audio signal by using the target soft mute signal to obtain an output audio signal. Therefore, the descending and ascending time of the soft mute of the electronic equipment is controlled according to the target soft mute signal, so that not only can the noise interference on users be reduced, but also the accurate control of the soft mute time can be realized.

In another embodiment of the present application, referring to fig. 11, a schematic structural diagram of an electronic device provided in the embodiment of the present application is shown. As shown in fig. 11, the electronic device 110 may include at least a soft mute control circuit 1101 and an audio apparatus 1102.

In this embodiment, the soft mute control circuit 1101 may be the soft mute control circuit described in any of the previous embodiments, and the audio apparatus 1102 may be a sound output device or apparatus, such as a bluetooth headset, a speaker, a loudspeaker, or the like.

In this way, according to the soft mute control circuit 1101, the falling and rising times of the soft mute of the audio apparatus 1102 are controlled, so that not only can noise interference to the user be reduced, but also accurate control of the soft mute time can be realized, so that the output audio signal can exhibit power exponent rising or falling, and can be further processed to exhibit linear rising or falling, thereby further realizing accurate control of the soft mute completion time.

In the embodiments of the present application, each component may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware or a form of a software functional module.

Based on the understanding that the technical solution of the present embodiment essentially or a part contributing to the related art, or all or part of the technical solution, may be embodied in the form of a software product stored in a storage medium, and include several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the method of the present embodiment. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

Accordingly, the present embodiments provide a computer storage medium storing a computer program that, when executed, implements the method of any of the preceding embodiments.

It should also be noted that, in the present application, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.

The methods disclosed in the several method embodiments provided in the present application may be combined arbitrarily without conflict to obtain new method embodiments.

Features disclosed in several of the product embodiments provided in the present application may be combined in any combination to yield new product embodiments without conflict.

The features disclosed in the several method or apparatus embodiments provided in the present application may be combined arbitrarily, without conflict, to arrive at new method embodiments or apparatus embodiments.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A soft mute control circuit, wherein the soft mute control circuit comprises a first logic processing circuit and a second logic processing circuit; wherein the content of the first and second substances,

the first logic processing circuit is configured to receive a preset soft mute time, a soft mute control signal, and a soft mute enable signal, and generate a target soft mute signal according to the preset soft mute time, the soft mute control signal, and the soft mute enable signal;

the second logic processing circuit is configured to receive an input audio signal, the soft mute enable signal, and the target soft mute signal, and perform soft mute control on the input audio signal according to the target soft mute signal when the soft mute enable signal indicates to turn on a soft mute enable control function, so as to obtain an output audio signal.

2. The soft mute control circuit of claim 1, wherein the second logic processing circuit comprises a first multiplier, a first selector, and a first delay; wherein the content of the first and second substances,

the first multiplier is configured to multiply the input audio signal and the target soft mute signal to obtain a first intermediate signal;

the first selector is configured to perform selection processing on the first intermediate signal and the input audio signal according to the soft mute enable signal to obtain a second intermediate signal;

the first delayer is configured to delay the second intermediate signal to obtain the output audio signal.

3. The soft mute control circuit of claim 2,

the first selector is specifically configured to determine the first intermediate signal as the second intermediate signal when the soft mute enable signal indicates to turn on a soft mute enable control function; and determining the input audio signal as the second intermediate signal when the soft mute enable signal indicates turning off a soft mute enable control function.

4. The soft mute control circuit of claim 3,

if the value of the soft mute enable signal is a first value, determining that the soft mute enable signal indicates to start a soft mute enable control function;

and if the value of the soft mute enabling signal is a second value, determining that the soft mute enabling signal indicates to close the soft mute enabling control function.

5. The soft mute control circuit of claim 1, wherein the soft mute control signal comprises a first control signal and a second control signal, the first logic processing circuit comprises a configuration unit, a second selector, a first adder, a second multiplier, a second adder, a third selector, a fourth selector, and a second delay; wherein the content of the first and second substances,

the configuration unit is used for configuring the preset soft mute time to obtain a first parameter value;

the second selector is used for carrying out selection processing on the first preset signal and the second preset signal according to the first control signal to obtain a third intermediate signal;

the first adder is configured to perform subtraction processing on the target soft mute signal and the third intermediate signal to obtain a fourth intermediate signal;

the second multiplier is configured to multiply the fourth intermediate signal by the first parameter value to obtain a fifth intermediate signal;

the second adder is configured to add the third intermediate signal and the fifth intermediate signal to obtain a first result signal;

the third selector is configured to perform selection processing on the first result signal and the temporary output signal according to the second control signal to obtain a sixth intermediate signal;

the fourth selector is configured to perform selective processing on the sixth intermediate signal and the first preset signal according to the soft mute enable signal to obtain a seventh intermediate signal;

and the second delayer is used for carrying out delay processing on the seventh intermediate signal to obtain the target soft mute signal.

6. The soft mute control circuit of claim 5,

the third selector is specifically configured to determine the temporary output signal as the sixth intermediate signal when the value of the second control signal is the first value; and determining the first result signal as the sixth intermediate signal when the value of the second control signal is a second value;

the fourth selector is specifically configured to determine the sixth intermediate signal as the seventh intermediate signal when the value of the soft mute enable signal is the first value; and determining the first preset signal as the seventh intermediate signal when the value of the soft mute enable signal is the second value.

7. The soft mute control circuit of claim 5,

determining that the target soft mute signal is in a power exponent descending trend under the condition that the value of the soft mute enable signal is a first value, the value of the second control signal is a second value, and the value of the first control signal is the first value;

8. The soft mute control circuit of claim 5, wherein the first logic processing circuit further comprises a first computational unit, a second computational unit, a first comparator, a logic sub-circuit, and a fifth selector; wherein the content of the first and second substances,

the first calculating unit is used for performing score calculation on the first parameter value to obtain a second parameter value;

the second calculating unit is configured to perform absolute value calculation on the fourth intermediate signal to obtain an eighth intermediate signal;

the first comparator is configured to compare the eighth intermediate signal with the second parameter value to obtain a ninth intermediate signal;

the logic processing sub-circuit is configured to obtain a second result signal according to the first result signal, the ninth intermediate signal, and the target soft mute signal;

and the fifth selector is configured to perform selection processing on the first result signal and the second result signal according to the ninth intermediate signal to obtain the temporary output signal.

9. The soft mute control circuit of claim 8, wherein the logic subcircuit comprises a logic gate, a third adder, a sixth selector, a seventh selector, a third delay, and a fourth adder; wherein the content of the first and second substances,

the logic gate is used for carrying out logic operation on the ninth intermediate signal to obtain a tenth intermediate signal;

the third adder is configured to subtract the first result signal and the target soft mute signal to obtain an eleventh intermediate signal;

the sixth selector is configured to perform selection processing on the eleventh intermediate signal and the output delayed signal according to the tenth intermediate signal to obtain a twelfth intermediate signal;

the seventh selector is configured to perform selection processing on the twelfth intermediate signal and the first preset signal according to the soft mute enable signal to obtain a thirteenth intermediate signal;

the third delayer is configured to delay the thirteenth intermediate signal to obtain the output delayed signal;

and the fourth adder is configured to add the twelfth intermediate signal and the target soft mute signal to obtain the second result signal.

10. The soft mute control circuit of claim 9,

the fifth selector is specifically configured to determine the first result signal as the temporary output signal when the value of the ninth intermediate signal is the first value; and determining the second result signal as the temporary output signal when the ninth intermediate signal takes the second value.

11. The soft mute control circuit of claim 10,

under the condition that the value of the soft mute enable signal is a first value, the value of the second control signal is a first value, and the value of the first control signal is a first value, if the value of the ninth intermediate signal is a first value, determining that the target soft mute signal is in a power exponent descending trend; if the value of the ninth intermediate signal is a second value, determining that the target soft mute signal is in a linear descending trend;

under the condition that the value of the soft mute enable signal is a first value, the value of the second control signal is a first value, and the value of the first control signal is a second value, if the value of the ninth intermediate signal is the first value, determining that the target soft mute signal is in a power exponential rising trend; and if the value of the ninth intermediate signal is a second value, determining that the target soft mute signal is in a linear ascending trend.

12. A method of soft mute control, the method comprising:

and when the soft mute enable signal indicates to start a soft mute enable control function, performing soft mute control on the input audio signal by using the target soft mute signal to obtain an output audio signal.

13. The method of claim 12, wherein said soft-mute controlling said input audio signal with said target soft-mute signal to obtain an output audio signal comprises:

multiplying the input audio signal and the target soft mute signal by a first multiplier to obtain a first intermediate signal;

selecting the first intermediate signal and the input audio signal through a first selector and the soft mute enabling signal to obtain a second intermediate signal;

and carrying out delay processing on the second intermediate signal through a first delayer to obtain the output audio signal.

14. The method of claim 13, wherein the selectively processing the first intermediate signal and the input audio signal via a first selector and the soft mute enable signal to obtain a second intermediate signal comprises:

determining the first intermediate signal as the second intermediate signal when the soft mute enable signal indicates to turn on a soft mute enable control function;

determining the input audio signal as the second intermediate signal when the soft mute enable signal indicates turning off a soft mute enable control function.

15. The method of claim 14, further comprising:

16. The method of claim 12, wherein the soft mute control signal comprises a first control signal and a second control signal, and wherein the generating a target soft mute signal by performing logic processing according to the preset soft mute time, the soft mute control signal and the soft mute enable signal comprises:

configuring the preset soft mute time through a configuration unit to obtain a first parameter value;

multiplying the fourth intermediate signal by the first parameter value through a second multiplier to obtain a fifth intermediate signal;

selecting the first result signal and the temporary output signal through a third selector and the second control signal to obtain a sixth intermediate signal;

and performing delay processing on the seventh intermediate signal through a second delayer to obtain the target soft mute signal.

17. The method of claim 16, wherein the first predetermined signal is a level signal with an amplitude of 0, and the second predetermined signal is a level signal with an amplitude of 1.

18. The method of claim 16, wherein when the soft mute enable signal takes a first value and the second control signal takes a second value, the method further comprises:

19. The method of claim 16, further comprising:

calculating an absolute value of the fourth intermediate signal through a second calculating unit to obtain an eighth intermediate signal;

comparing the eighth intermediate signal with the second parameter value through a first comparator to obtain a ninth intermediate signal;

and selecting and processing the first result signal and the second result signal through a fifth selector and the ninth intermediate signal to obtain the temporary output signal.

20. The method of claim 19, wherein obtaining a second resulting signal from a logic processing sub-circuit based on the first resulting signal, the ninth intermediate signal, and the target soft mute signal comprises:

subtracting the first result signal and the target soft mute signal by using a third adder to obtain an eleventh intermediate signal;

selectively processing the eleventh intermediate signal and the output delayed signal through a sixth selector and the tenth intermediate signal to obtain a twelfth intermediate signal;

performing delay processing on the thirteenth intermediate signal through a third delayer to obtain the output delay signal;

and adding the twelfth intermediate signal and the target soft mute signal by a fourth adder to obtain the second result signal.

21. The method of claim 20, wherein when the soft mute enable signal takes a first value and the second control signal takes a first value, the method further comprises:

if the value of the first control signal is a first value and the value of the ninth intermediate signal is a first value, determining that the target soft mute signal is in a power exponent descending trend;

22. The method of claim 20, wherein when the soft mute enable signal takes a first value and the second control signal takes a first value, the method further comprises:

if the value of the first control signal is a second value and the value of the ninth intermediate signal is a first value, determining that the target soft mute signal is in a power exponent rising trend;

and if the value of the first control signal is a second value and the value of the ninth intermediate signal is a second value, determining that the target soft mute signal is in a linear ascending trend.

23. The method according to claim 21 or 22, wherein the first value is equal to 1 and the second value is equal to 0.

24. An electronic device, characterized in that it comprises at least a soft mute control circuit and an audio apparatus according to any of claims 1 to 11.