CN113676181B - Two-order all-passive noise shaping SAR ADC based on double-input comparator - Google Patents
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Abstract
The invention discloses a two-order all-passive noise shaping SAR ADC based on a double-input comparator, which comprises a basic SAR ADC module and a margin processing circuit, wherein the margin processing circuit comprises four margin sampling capacitors, a first-time integrating capacitor, a second-time integrating capacitor, a clock and control switches corresponding to the capacitors; the integration of the residual voltage and the summation of the passive signal-integration voltage are controlled by switches corresponding to different capacitors, so that the effect of realizing second-order passive noise shaping by a single branch circuit is achieved. The passive structure can reduce power consumption, and meanwhile, the passive structure can enable the final noise transfer function coefficient to be determined by the capacitance proportion, so that the overall PVT stability of the circuit is higher; since second order shaping is achieved with a single branch, noise and design requirements of the comparator are reduced. In consideration of the passive integral gain loss, the structure also comprises double passive gain to compensate the gain loss, thereby ensuring higher shaping effect.
Description
Technical Field
The invention relates to a two-order fully passive noise shaping SAR ADC based on a double-input comparator, and belongs to the technical field of passive noise shaping SAR ADCs.
Background
The SAR ADC is widely applied by the characteristics of medium resolution and low power consumption, but the resolution of the SAR ADC is limited due to noise and quantization noise of an internal comparator, and in order to reduce the influence of the quantization noise in the bandwidth of the SAR ADC and the noise of the comparator on the precision of the SAR ADC, noise shaping is used as a popular technology to effectively reduce the noise power in the bandwidth and improve the resolution of the SAR ADC.
In the existing research, the noise shaping mode mainly comprises active noise shaping and passive noise shaping, and the active noise shaping SAR ADC [1] The excess voltage is amplified by the operational amplifier and then integrated, so that the processing has the advantages that a better noise transfer function can be realized, a better noise shaping effect is achieved, but the introduction of the operational amplifier can bring aboutThe improvement of power consumption and the reduction of the stability of the whole circuit PVT. By means of passive noise shaping [2] The power consumption of the circuit can be reduced, meanwhile, the passive integration enables the designed noise transfer function coefficient to be determined by the capacitance ratio, therefore, the PVT stability of the circuit is high, but the passive integration has gain loss, so the shaping effect is poorer than that of the active mode. In both an active mode and a passive mode, the conventional first-order noise shaping SAR ADC needs an additional comparator input to sum an input signal and an integration result, and in order to achieve a better shaping effect than the first-order, a second-order noise shaping circuit is often designed, and the conventional second-order noise shaping circuit is designed [3] Two additional comparator input pairs are needed, which results in more thermal noise, and meanwhile, to compensate for the loss of passive integral gain, the comparator input pair needs to be amplified to a certain extent according to the size of the tube, which leads to increase of kickback noise, and thus, a certain negative effect is generated on the final shaping effect. Aiming at the problem that a multi-input comparator is introduced into the traditional shaping structure, a passive noise shaping structure based on a dual-input comparator is also provided [4] But only first order passive noise shaping, the SAR ADC accuracy is not high.
[1]C.-C.Liu and M.-C.Huang,“A 0.46mW 5MHz-BW 79.7dB-SNDR noise-shaping SAR ADC with dynamic-amplififier-based FIR-IIR fifilter,”in IEEE Int.Solid-State Circuits Conf.(ISSCC)Dig.Tech.Papers,Feb.2017,pp.466–467.
[2]W.Guo,N.Sun,‘A 13b-ENOB 173dB-FoM 2nd-order NS SAR ADC with passive integrators,’IEEE Symp.VLSI Circuits,pp.236-237,June 2017.
[3]H.Zhuang,W.Guo,J.Liu,H.Tang,Z.Zhu,L.Chen,and N.Sun,“A Second-Order Noise-Shaping SAR ADC With Passive Integrator and Tri-Level Voting,”Ieee Journal of Solid-State Circuits,vol.54,no.6,pp.1636-1647,Jun,2019.
[4]Y.-Z.Lin,C.-Y.Lin,S.-C.Tsou,C.-H.Tsai,and C.-H.Lu,"A 40MHz-BW 320MS/sPassive Noise-Shaping SAR ADC with Passive Signal-Residue Summation in 14nm FinFET,"IEEE International Solid State Circuits Conference.pp.330-+,2019.
Disclosure of Invention
The invention aims to provide a two-order fully passive noise-shaped SAR ADC based on a double-input comparator, which is used for solving the problem that the traditional noise-shaped SAR ADC needs to use a multi-input comparator.
In order to realize the purpose, the invention adopts the technical scheme that:
a two-input comparator-based second-order all-passive noise shaping SAR ADC comprises a basic SAR ADC module and a margin processing circuit, wherein the basic SAR ADC module comprises a sampling switch, a DAC capacitor array, a comparator and control logic, the margin processing circuit comprises four margin sampling capacitors, a first-time integrating capacitor, a second-time integrating capacitor, a clock and control switches corresponding to the capacitors, the four margin sampling capacitors are respectively Cresn1, cresn2, cresp1 and Cresp2 and are connected between upper polar plates of an upper DAC capacitor array and a lower DAC capacitor array in a bridging mode and used for sampling margin voltages after conversion of the SAR ADC; the first-time integrating capacitor comprises an N-end first-time integrating capacitor Cint1N and a P-end first-time integrating capacitor Cint1P, and the second-time integrating capacitor comprises an N-end second-time integrating capacitor Cint2N1 and Cint2N2 and a P-end second-time integrating capacitor Cint2P1 and Cint2P2; the clock comprises a clock S0, a clock S1 and a clock S2, wherein the clock S0 controls the work of the whole SAR ADC and comprises the sampling of the residual voltage, the clock S1 controls the first integration of the residual sampling capacitor and the first integration capacitor, and the clock S2 controls the second integration of the residual sampling capacitor and the second integration capacitor;
the working time sequence of the noise shaping SAR ADC is as follows: the integration of the residual voltage and the summation of the passive signal-integration voltage are controlled by switches corresponding to different capacitors, so that the effect of realizing second-order passive noise shaping by a single branch circuit is achieved.
The working timing of the noise-shaping SAR ADC comprises the following stages:
stage A, SAR ADC conversion stage;
stage B, passive integration stage;
and C, summing the input signals and the two integration results, and performing the next conversion of the SAR ADC.
The stage A specifically comprises the following steps:
input signals Vip and Vin are sampled in a bottom plate sampling mode, then the signals are quantized by the SAR ADC and converted into corresponding digital codes, residual voltage is generated on upper plates of an upper DAC capacitor array and a lower DAC capacitor array after conversion is finished, and the residual sampling capacitor is bridged between the upper plates of the two DAC capacitor arrays, so that the voltage difference between two ends of the residual capacitor after conversion is twice of the single-end residual voltage. Compared with the traditional mode of adding a grounded margin sampling capacitor on the upper DAC capacitor array and the lower DAC capacitor array for margin sampling, the margin voltage sampling mode obtains double margin gain on one hand, namely the margin voltage sampled by the four margin capacitors of Cresn1, cresn2, cresp1 and Cresp2 is double of that of the traditional mode, so that a certain compensation effect is realized on the first integral gain loss; on the other hand, when SAR ADC conversion is completed, the voltage difference between two ends of the margin capacitor is the sampled margin voltage, and extra time is not required to be allocated to collect the margin voltage like the traditional mode, so that the conversion period of the SAR ADC can be shortened, and the conversion speed of the SAR ADC can be improved.
The stage B specifically comprises the following steps:
phase B1, first passive integration phase:
and performing first passive integration on the two-fold residual voltage obtained by sampling, performing charge redistribution on charges on the residual capacitor and the integrating capacitor based on charge conservation, and establishing a new voltage difference at two ends of the capacitor so as to complete the first integration. For convenience of description, taking the N terminal as an example, the voltage differences across the residual capacitors Cresn1, cresn2 and the integrating capacitor Cint1N are the first integration result, where the integrated voltages on Cresn1 and Cresn2 are used for the input of the second integration, and the first integration is completed when the clock S1 is at a high level.
Phase B2, second passive integration phase:
and taking the result of the first passive integration as the input of the passive integrator to perform second passive integration, wherein the principle is the same as that of the first integration. After the first integration of the two residual capacitors Cresn1 and Cresn2 is completed, the differential pressure at the two ends is the first integration result, similarly for convenience of description, for example, when the clock S2 is at a high level, the residual capacitors Cresn1 and Cresn2 are simultaneously and respectively connected to the two ends of the integrating capacitors Cint2N1 and Cint2N2 to perform the second integration, so that two same integration results are obtained.
The stage C specifically includes:
after the passive integration stage is finished, the clocks S1 and S2 are both low level, at the moment, a first integration result is stored in Cint1N, and second integration results are stored in Cint2N1 and Cint2N 2; and next, the clock S0 is changed into high level, the next SAR ADC conversion is carried out, the residual capacitor is connected between the upper polar plates of the two DAC capacitor arrays again and is used for sampling the residual voltage after the conversion, meanwhile, the integrating capacitors Cint1N, cint2N1 and Cint2N2 are connected in series, and the superposition of the input signal and the two integration results is realized by using a single branch circuit to serve as the input of the comparator.
The comparator is a dual-input comparator, so that the thermal noise and kickback noise of the comparator are reduced.
Has the advantages that: the conventional noise shaping SAR ADC needs to use a multi-input comparator, and meanwhile, in order to compensate for the loss of integral gain, the size of an input tube of the comparator is properly increased, so that more thermal noise and kickback noise are introduced, so that the conventional noise shaping structure has to achieve a compromise between the noise suppression capability in a bandwidth and the noise introduced by the multi-input comparator, and the improvement of the shaping effect of the whole SAR ADC is influenced. The invention controls each stage of margin processing by utilizing the switch, including the first integration and the second integration, and realizes the superposition of integral voltage by adopting the series connection of the integral capacitors, thereby achieving the summation effect of the input signal and the integral voltage of noise shaping, reducing the number of noise shaping branches, and simultaneously reducing the number of input ends of the comparator, thereby greatly reducing the thermal noise and kickback noise of the comparator caused by the increase of the input pair of the comparator, and being beneficial to the improvement of the ADC shaping effect. Aiming at the defects of low speed of active noise shaping and poor PVT stability, the second-order passive shaping structure provided by the invention utilizes passive integration to ensure that the final noise transfer function coefficient is determined by the size proportion of the capacitor, thereby enhancing the PVT stability, and simultaneously improving the shaping speed in a passive mode. In order to ensure the second-order passive noise shaping precision, the invention focuses on realizing passive double gain, including amplification of residual voltage and integral voltage, thereby alleviating gain loss in the passive integration process and improving the precision of second-order passive noise shaping.
The double-input-comparator-based second-order fully passive noise shaping SAR ADC provided by the invention utilizes the idea that capacitors are connected in series to carry out voltage summation, and compared with the traditional structure for realizing second-order passive noise shaping, the double-input-comparator-based second-order fully passive noise shaping SAR ADC avoids using a plurality of input pairs of comparators, thereby greatly reducing the limitation of thermal noise and kickback noise of the comparators on the shaping effect of the SAR ADC, simultaneously considering the gain loss of passive integration, realizing double passive gain by the provided structure to compensate the gain loss of twice integration, and finally achieving a better shaping effect than the traditional second-order passive noise shaping. In the aspect of conversion speed of the SAR ADC, because the used margin sampling capacitor is connected between the upper polar plates of the upper DAC capacitor array and the lower DAC capacitor array, the margin sampling is finished when the conversion of the SAR ADC is finished, extra time does not need to be allocated for the margin sampling in the whole conversion period, in addition, the conversion period of the SAR ADC cannot be prolonged in the process of integrating the margin voltage twice, the reason is that the integration can be finished in the next sampling process, compared with the traditional second-order passive noise shaping SAR ADC, the method has higher conversion rate, can achieve relatively higher precision, and is suitable for high-speed and high-precision application occasions.
Drawings
FIG. 1 is a schematic diagram of the overall circuit structure of the present invention;
FIG. 2a is a timing diagram illustrating the operation of the present invention;
FIG. 2b is a flow chart of equivalent signals corresponding to a specific working timing sequence of the present invention;
FIG. 3a is a dynamic diagram of SARADC conversion phase of the noise-shaped SAR ADC of the present subject matter;
FIG. 3b is a first integration phase dynamic diagram of the noise-shaped SAR ADC of the present invention;
FIG. 3c is a second integration phase dynamic diagram of the noise-shaped SAR ADC of the present subject matter;
fig. 4a to 4d are performance parameter simulation results of the present invention applied to a 10-bit dual-channel SAR ADC, where the SAR ADC has a bandwidth of 20MHz and a sampling rate of 320MHz, and four input signals with different frequencies are selected from low frequency to high frequency within the bandwidth for simulation.
Detailed Description
The present invention will be further described with reference to the accompanying drawings.
As shown in fig. 1, the two-order fully passive noise-shaping SAR ADC based on the dual-input comparator of the present invention includes two modules, one is a basic SAR ADC module, and the other is a margin processing circuit, where the basic SAR ADC module includes a sampling switch, a DAC capacitor array, a comparator and a control logic, the margin processing circuit includes four margin sampling capacitors, a first integration capacitor, a second integration capacitor, a clock and control switches corresponding to the capacitors, where the four margin sampling capacitors are respectively a Cresn1, a Cresn2, a Cresp1 and a Cresp2, and are connected across upper plates of the upper and lower DAC capacitor arrays for sampling a margin voltage after conversion of the SAR ADC; the first-time integrating capacitor comprises an N-end first-time integrating capacitor Cint1N and a P-end first-time integrating capacitor Cint1P, and the second-time integrating capacitor comprises an N-end second-time integrating capacitor Cint2N1 and Cint2N2, and a P-end second-time integrating capacitor Cint2P1 and Cint2P2; the clock comprises a clock S0, a clock S1 and a clock S2, wherein the clock S0 controls the work of the whole SAR ADC and comprises the sampling of the residual voltage, the clock S1 controls the first integration of the residual sampling capacitor and the first integration capacitor, and the clock S2 controls the second integration of the residual sampling capacitor and the second integration capacitor;
the integration of the residual voltage and the summation of the passive signal-integration voltage are controlled by the on and off of the corresponding switches of different capacitors, so that the effect of realizing second-order passive noise shaping by a single branch is achieved. Fig. 2a clearly shows several working phases of the whole SAR ADC, which are divided into a conversion phase (including the acquisition of the residue voltage), a first passive integration phase and a second passive integration phase of the SAR ADC.
The circuit working phase is specifically explained as follows:
phase A, SAR ADC conversion phase
Input signals Vip and Vin are sampled in a bottom plate sampling mode, as shown in fig. 3a, at this time, a clock S0 is at a high level, margin sampling capacitors Cresn1, cresn2, cresp1 and Cresp2 are connected to upper plates of DAC capacitor arrays at two ends, all integrating capacitors are connected in series, a shaping branch is connected, an SAR ADC quantizes the input signals and converts the quantized input signals into corresponding digital codes, and after conversion, margin voltages are generated on the upper plates of the upper and lower DAC capacitor arrays, because the margin capacitors are bridged between the upper plates of the two capacitor arrays, a differential pressure at two ends of the capacitors after conversion is twice of a single-end margin voltage, compared with a traditional mode in which margin sampling is performed by adding a grounded margin sampling capacitor on the upper and lower DAC capacitor arrays, on one hand, the mode obtains twice of a margin voltage gain, that is, in fig. 1, the margin voltage sampled by four margin capacitors of Cresn1, cresn2, cresp1 and Cresp2 is twice of the traditional mode, and thus has a certain compensation effect on a first-time integral gain loss; on the other hand, when SAR ADC conversion is completed, the voltage difference between two ends of the residue capacitor is the sampled residue voltage, and extra time is not required to be allocated to sample the residue voltage like the traditional mode, so that the conversion period of the noise shaping SAR ADC can be shortened, the overall conversion speed is improved, and the method is suitable for high-speed application.
Stage B, passive integration stage
In stage B1, as shown in fig. 3B, at this time, the S1 clock is at a high level, the residue sampling capacitor is connected to two ends of the integrating capacitors Cint1N and Cint1P, and the first passive integration is performed on the two sampled residue voltages, the main idea is that charge is conserved, charge redistribution is performed on the residue capacitors and the integrating capacitors, and a new differential pressure is established between two ends of the capacitors, so as to complete the first integration.
In stage B2, as shown in fig. 3c, the clock S2 is at a high level, the residue capacitors are connected to two ends of Cint2N1, cint2N2, cint2P1, and Cint2P2, the first integration result is used as the input of the passive integrator to perform the second passive integration, the principle is the same as the first integration, and the differential pressures at two ends of the two residue capacitors Cresn1 and Cresn2 after the first integration is completed are the first integration results.
And C, sampling the signal, summing the two integration results, and performing the next conversion of the SAR ADC
After the first integration and the second integration are finished, the clocks S1 and S2 are both at a low level, and at this time, the integration result of the first time is stored in Cint1N, and the integration results of the second time are stored in Cint2N1 and Cint2N 2. Next, the clock S0 is changed into high level, next SAR ADC conversion is carried out, the residual capacitor is connected between the upper electrode plates of the two capacitor arrays again and is used for sampling the residual voltage after conversion, meanwhile, the integrating capacitors Cint1N, cint2N1 and Cint2N2 are connected in series, the superposition of an input signal and two integration results is realized by using a single branch circuit to serve as the input of the comparator, the comparator can use a simple double-input comparator, and therefore the thermal noise and kickback noise of the comparator are reduced.
The flow chart of the equivalent signal obtained by combining the whole circuit structure and the specific working timing is shown in fig. 2b, which includes the double passive gains g1 and g2. The passive integrator coefficients a1 and a2 are determined by the ratio of the margin sampling capacitance to the integrating capacitance, so that the PVT stability of the final noise transfer function NTF is high.
The invention utilizes the integration capacitors to be connected in series to realize the summation of a sampling signal and an integration voltage, and simultaneously, the margin sampling capacitor bridged between the upper polar plates of DAC capacitor arrays at two ends realizes double passive gain of the margin voltage, thereby compensating the gain loss of the integration, and the second-order passive noise shaping can be realized through a single branch.
Considering that the invention is suitable for high-speed and high-precision application occasions, the invention is applied to a 10-bit dual-channel SAR ADC for simulation verification, and the invention is specifically described by combining simulation results.
The structure of the invention is applied to each channel ADC of a 10-bit dual-channel SAR ADC, the control clock adopts the control clock shown in figure 2a, and the whole working process of the SAR ADC is divided into three stages: 1. a normal conversion (including sampling of the residual voltage) stage 2, a first integration stage 3 and a second integration stage. For convenience of description, the following description is made with a single channel SAR ADC:
phase A, SAR ADC conversion phase (including sampling of margin voltage)
Input signals Vip and Vin are sampled in a bottom plate sampling mode, as shown in fig. 3a, at this time, a clock S0 is at a high level, margin sampling capacitors Cresn1, cresn2, cresp1 and Cresp2 are connected to upper plates of DAC capacitor arrays at two ends, all integrating capacitors are connected in series, a shaping branch is connected, an SAR ADC quantizes the input signals and converts the input signals into corresponding digital codes, margin voltages are generated on the upper plates of the upper and lower DAC capacitor arrays after conversion, and since the margin capacitors are bridged between the upper plates of the two capacitor arrays, the voltage difference between two ends of the capacitors after conversion is twice of the single-ended margin voltage. After the conversion period of the SAR ADC in the current period is finished, the pressure difference between Cresn1, cresn2, cresp1 and Cresp2 is the residual voltage, so that the extra time is prevented from being consumed for sampling the residual voltage, and the conversion period of the SAR ADC is shortened.
Stage B, first passive integration
As shown in fig. 3b, at this time, the S1 clock is at a high level, the residual sampling capacitor is connected to two ends of the integrating capacitors Cint1N and Cint1P, the sampled double residual voltages are subjected to first passive integration, and the coefficient of the passive integrator is determined by setting the relative size of the residual capacitors and the integrating capacitors. The main idea is that charge is conserved, the residual capacitance and the integrating capacitance are redistributed, and a new voltage difference is established at two ends of the capacitance, thereby completing the first integration.
Stage C, second passive integration
As shown in fig. 3c, the S2 clock is at a high level, the residue capacitors are connected to two ends of Cint2N1, cint2N2, cint2P1 and Cint2P2, the first integration result is used as the input of the passive integrator to perform the second passive integration, the principle is the same as the first integration, the differential pressure at two ends of the two residue capacitors Cresn1 and Cresn2 after the first integration is completed is the first integration result, and the two integration results are simultaneously connected to two ends of the integration capacitors Cint2N1 and Cint2N2 respectively to perform the second integration, so as to obtain two same integration results, and provide a doubled passive gain to compensate the gain loss of the second integration.
The SAR ADC has the sampling rate of 320MHz, the input signal bandwidth of 20MHz, the input signal frequencies of 3.75MHz, 8.75MHz, 13.75MHz and 18.75MHz are selected in the bandwidth for simulation, the frequency spectrogram obtained by simulation is shown in figures 4a to 4d, the simulation result shows that the effective digits of the SAR ADC are all more than 13 digits in the 20MHz bandwidth, the SNDR reaches more than 80dB, and the SFDR reaches more than 85 dB.
In conclusion, the invention realizes the summation of signal-integral voltage by utilizing the series connection of the integral capacitors, realizes the noise shaping by depending on a single branch circuit, reduces the thermal noise and kickback noise of the comparator by adopting the traditional double-input structure, achieves better noise shaping effect, does not consume extra time for processing the margin, has shorter conversion period of the SAR ADC and improves the conversion speed of the noise shaping SAR ADC.
The above description is only of the preferred embodiments of the present invention, and it should be noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and these are intended to be within the scope of the invention.
Claims (6)
1. A two-order all-passive noise shaping SAR ADC based on a dual-input comparator is characterized in that: the SAR ADC circuit comprises a basic SAR ADC module and a margin processing circuit, wherein the basic SAR ADC module comprises a sampling switch, a DAC capacitor array, a comparator and control logic, the margin processing circuit comprises four margin sampling capacitors, a first-time integrating capacitor, a second-time integrating capacitor, a clock and control switches corresponding to the capacitors, the four margin sampling capacitors are respectively Cresn1, cresn2, cresp1 and Cresp2, and are bridged between upper polar plates of an upper DAC capacitor array and a lower DAC capacitor array and used for sampling margin voltages after conversion of the SAR ADC; the first-time integrating capacitor comprises an N-end first-time integrating capacitor Cint1N and a P-end first-time integrating capacitor Cint1P, and the second-time integrating capacitor comprises an N-end second-time integrating capacitor Cint2N1 and Cint2N2 and a P-end second-time integrating capacitor Cint2P1 and Cint2P2; the clock comprises a clock S0, a clock S1 and a clock S2, wherein the clock S0 controls the work of the whole SAR ADC and comprises the sampling of the residual voltage, the clock S1 controls the first integration of the residual sampling capacitor and the first integration capacitor, and the clock S2 controls the second integration of the residual sampling capacitor and the second integration capacitor;
the working time sequence of the noise shaping SAR ADC is as follows: the integration of the residual voltage and the summation of the passive signal-integration voltage are controlled by switches corresponding to different capacitors, so that the effect of realizing second-order passive noise shaping by a single branch circuit is achieved.
2. The dual-input comparator based second-order fully passive noise-shaping SAR ADC of claim 1, wherein: the working timing sequence of the noise-shaped SAR ADC comprises the following stages:
stage A, SAR ADC conversion stage;
stage B, passive integration stage;
and in the stage C, summing the input signals and the two integration results, and performing the next conversion of the SAR ADC.
3. The dual-input comparator based second-order fully passive noise-shaping SAR ADC of claim 2, wherein: the stage A specifically comprises the following steps:
the input signals Vip and Vin are sampled in a bottom plate sampling mode, then the signals are quantized by the SAR ADC and converted into corresponding digital codes, residual voltage is generated on upper plates of an upper DAC capacitor array and a lower DAC capacitor array after the conversion is finished, and the residual sampling capacitor is bridged between the upper plates of the two DAC capacitor arrays, so that the differential pressure at two ends of the residual capacitor after the conversion is finished is twice of the single-end residual voltage.
4. The dual-input comparator based second-order fully passive noise-shaping SAR ADC of claim 2, wherein: the stage B is specifically as follows:
phase B1, first passive integration phase:
performing first passive integration on the two times of residual voltage obtained by sampling, redistributing charges on the residual capacitor and the integrating capacitor based on charge conservation, and establishing a new voltage difference at two ends of the capacitor so as to complete the first integration;
stage B2, second passive integration stage:
and taking the result of the first passive integration as the input of the passive integrator to carry out second passive integration, wherein the principle is the same as that of the first integration.
5. The dual-input comparator based second-order fully passive noise-shaping SAR ADC of claim 2, wherein: the stage C specifically includes:
after the passive integration stage is finished, the clocks S1 and S2 are both low level, at the moment, the first integration result is stored in Cint1N, and the second integration result is stored in Cint2N1 and Cint2N 2; and then the clock S0 is changed into high level, next SAR ADC conversion is carried out, the residual capacitor is connected between the upper electrode plates of the two DAC capacitor arrays again and is used for sampling the residual voltage after conversion, meanwhile, the integrating capacitors Cint1N, cint2N1 and Cint2N2 are connected in series, and the superposition of an input signal and two integration results is realized by utilizing a single branch circuit to serve as the input of the comparator.
6. The dual-input comparator based second-order fully passive noise-shaping SAR ADC of claim 5, wherein: the comparator is a dual-input comparator.
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| CN110492885A (en) * | 2019-07-11 | 2019-11-22 | 东南大学 | A kind of passive noise shaping Approach by inchmeal SAR analog-digital converter |
| CN111211783A (en) * | 2020-02-17 | 2020-05-29 | 西安交通大学 | Double-feedback-loop noise shaping oversampling successive approximation analog-to-digital converter and method |
| CN111327323A (en) * | 2020-02-17 | 2020-06-23 | 西安交通大学 | Passive noise shaping oversampling successive approximation analog-to-digital converter and control method |
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