CN113675337A - PIP capacitor and forming method - Google Patents

PIP capacitor and forming method Download PDF

Info

Publication number
CN113675337A
CN113675337A CN202110961310.XA CN202110961310A CN113675337A CN 113675337 A CN113675337 A CN 113675337A CN 202110961310 A CN202110961310 A CN 202110961310A CN 113675337 A CN113675337 A CN 113675337A
Authority
CN
China
Prior art keywords
forming
polysilicon
insulating layer
sine wave
pip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110961310.XA
Other languages
Chinese (zh)
Inventor
汤志林
王卉
付永琴
曹子贵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huahong Grace Semiconductor Manufacturing Corp filed Critical Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority to CN202110961310.XA priority Critical patent/CN113675337A/en
Publication of CN113675337A publication Critical patent/CN113675337A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Abstract

The invention provides a PIP capacitor and a forming method thereof, comprising the following steps: providing a substrate, wherein the substrate comprises a CELL area and a PIP area; forming a shallow trench isolation structure in the substrate of the PIP region; forming a plurality of spaced grid structures on a substrate of a CELL area by using a photomask of the grid structure, forming a plurality of spaced pseudo grid structures on a shallow trench isolation structure by using the photomask of the grid structure, exposing the surface of the shallow trench isolation structure among the pseudo grid structures, and forming the longitudinal section of each pseudo grid structure into a square shape; word line polycrystalline silicon and an insulating layer which are all in a sine wave shape are sequentially formed on the pseudo gate structure; a gate polysilicon is formed on the insulating layer. The insulating layer is in a sine wave shape with fluctuating height, so that the relative area between the word line polysilicon and the grid polysilicon is increased, and the capacitance value of the PIP capacitor is increased. And, because the dummy gate structure is formed simultaneously with the gate structure, no additional mask and process steps are required.

Description

PIP capacitor and forming method
Technical Field
The invention relates to the technical field of semiconductors, in particular to a PIP capacitor and a forming method thereof.
Background
Until now, semiconductor integrated circuit designs have come to have a variety of capacitors available for selection, including MOS (metal-oxide-semiconductor) capacitors, PIP (polysilicon-insulator-polysilicon) capacitors, MIM (metal-insulator-metal) capacitors, MOM (metal-oxide-metal) capacitors, and the like. PIP capacitors have been widely used to meet the customer requirements for capacitor characteristics and low cost.
Referring to fig. 1, a method for forming a PIP capacitor in the prior art includes forming a shallow trench isolation structure 120 in a substrate 110, and forming a word line polysilicon 130 on the shallow trench isolation structure 120 as a lower plate of the PIP capacitor; forming an oxide layer 140 as a PIP capacitor insulating layer on the word line polysilicon 130; a gate polysilicon 150 is formed over the oxide layer 140, the gate polysilicon 150 serving as the top plate of the PIP capacitor. However, as the size of electronic products is reduced, the size of the PIP capacitor also needs to be reduced, which results in the area of the upper plate and the lower plate of the PIP capacitor being reduced, and finally, the capacitance value of the manufactured PIP capacitor is reduced. The demand of high capacitance PIP capacitors for electronic devices is affected.
Disclosure of Invention
The invention aims to provide a PIP capacitor and a forming method thereof, which can improve the capacitance value of the PIP capacitor by increasing the area of an insulating layer.
In order to achieve the above object, the present invention provides a method for forming a PIP capacitor, including:
providing a substrate, wherein the substrate comprises a CELL area and a PIP area;
forming a shallow trench isolation structure in the substrate of the PIP region;
forming a plurality of spaced grid structures on the substrate of the CELL area by using a light shield of the grid structure, and simultaneously forming a plurality of spaced pseudo grid structures on the shallow trench isolation structure by using the light shield of the grid structure, wherein the surface of the shallow trench isolation structure is exposed among the pseudo grid structures, and the longitudinal section of each pseudo grid structure is square;
word line polycrystalline silicon and an insulating layer which are all in a sine wave shape are sequentially formed on the pseudo gate structure;
and forming gate polysilicon on the insulating layer.
Optionally, in the forming method of the PIP capacitor, the dummy gate structure is the same as the gate structure.
Optionally, in the method for forming the PIP capacitor, the width of the longitudinal section of each dummy gate structure is 0.2 micrometers, the height of each dummy gate structure is 3900 angstroms to 4100 angstroms, and the distance between adjacent dummy gate structures is 0.3 micrometers.
Optionally, the method for forming the PIP capacitor includes forming a sine wave word line polysilicon on the dummy gate structure, where the sine wave word line polysilicon includes:
and forming a first polycrystalline silicon layer to cover the surfaces of the pseudo gate structures and the shallow trench isolation structures positioned between the pseudo gate structures, etching the first polycrystalline silicon layer to form word line polycrystalline silicon in a sine wave shape, and positioning the wave trough of the sine wave between the adjacent pseudo gate structures.
Optionally, in the method for forming the PIP capacitor, the thickness of the first polysilicon layer is 1710 angstroms to 2090 angstroms.
Optionally, the method for forming the PIP capacitor includes:
and depositing an oxide layer on the word line polysilicon in a sine wave shape, wherein the oxide layer is changed into a sine wave shape along with the shape of the word line polysilicon, and the wave trough of the sine wave of the insulating layer is opposite to the wave trough of the word line polysilicon.
Optionally, in the method for forming the PIP capacitor, the thickness of the insulating layer is 140 angstroms to 160 angstroms.
Optionally, in the method for forming the PIP capacitor, a height difference between a valley and a peak of the sine wave insulating layer is 2400 angstroms to 2600 angstroms.
Optionally, the method for forming the PIP capacitor includes:
and depositing a second polysilicon layer on the insulating layer, wherein the second polysilicon layer fills the groove formed between the wave trough and the wave crest of the insulating layer.
The invention also provides a PIP capacitor, comprising:
a substrate;
a shallow trench isolation structure located within the substrate;
a plurality of dummy gate structures which are arranged on the shallow trench isolation structure at intervals, wherein the longitudinal section of each dummy gate structure is square;
word line polycrystalline silicon and an insulating layer which are respectively positioned on the pseudo gate structure and are in sine wave shapes;
and the gate polysilicon is positioned on the insulating layer.
In the PIP capacitor and the forming method thereof provided by the invention, a plurality of spaced pseudo gate structures are formed at first, and the pseudo gate structures enable the formed insulating layer to be in a sine wave shape with undulate heights, so that the relative area between the word line polycrystalline silicon and the gate polycrystalline silicon is increased, and the capacitance value of the PIP capacitor is increased. And because the dummy gate structure and the CELL area gate structure are formed at the same time, no additional photomask and process steps are needed, and the cost is not increased.
Drawings
Fig. 1 is a schematic diagram of a PIP capacitor of the prior art;
fig. 2 is a flowchart of a method for forming a PIP capacitor according to an embodiment of the present invention;
FIG. 3 is a diagram of CELL and PIP region division according to an embodiment of the present invention
Fig. 4 to 7 are schematic diagrams illustrating a method for forming a PIP capacitor according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a PIP capacitor according to an embodiment of the present invention;
in the figure: 110-substrate, 120-shallow trench isolation structure, 130-word line polysilicon, 140-oxide layer, 150-grid polysilicon, 210-substrate, 220A-CELL area, 220B-PIP area, 220-shallow trench isolation structure, 230-pseudo grid structure, 241-first polysilicon layer, 242-word line polysilicon, 250-insulating layer and 260-grid polysilicon.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. Advantages and features of the present invention will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 2, the present invention provides a method for forming a PIP capacitor, including:
s11: providing a substrate, wherein the substrate comprises a CELL area and a PIP area;
s12: forming a shallow trench isolation structure in the substrate of the PIP region;
s13: forming a plurality of spaced grid structures on the substrate of the CELL area by using a light shield of the grid structure, and simultaneously forming a plurality of spaced pseudo grid structures on the shallow trench isolation structure by using the light shield of the grid structure, wherein the surface of the shallow trench isolation structure is exposed among the pseudo grid structures, and the longitudinal section of each pseudo grid structure is square;
s14: word line polycrystalline silicon and an insulating layer which are both in a sine wave shape are sequentially formed on the pseudo gate structure;
s15: and forming gate polysilicon on the insulating layer.
Referring to fig. 3, a substrate 210 is first provided, the substrate 210 is a P-type substrate, the substrate 210 is divided into a CELL region 210A and a PIP region 210B, the CELL region 210A is a device region, the PIP region 210B is a capacitor region, the CELL region 210A is not adjacent to the PIP region 210B, the CELL region 210A and the PIP region 210B can be divided according to a layout design of a wafer or a chip, and the specific positional relationship and the connection relationship thereof are based on the actual requirement of the product.
Referring to fig. 3 and 4, a shallow trench isolation structure 220 is formed in the substrate 210 of the PIP region 210B, specifically, the shallow trench isolation structure 220 is formed by etching the substrate 210 to form a shallow trench, and filling oxide into the shallow trench to form a front trench isolation structure.
The inventor has found that if the capacitance of the PIP capacitor is increased, either by increasing the relative areas of the word line polysilicon and the gate polysilicon, or by decreasing the distance between the word line polysilicon and the gate polysilicon, i.e., the thickness of the insulating layer, there is a possibility that the thickness cannot be further decreased due to the process requirements, and at this time, the capacitance can be increased by increasing the relative areas of the word line polysilicon and the gate polysilicon. The inventors have also found that when the gate structure is formed in the CELL region 210A, a dummy gate structure can be formed on the substrate 210 in the PIP region, so as to change the shapes of the word line polysilicon and the gate polysilicon to increase the area of the insulating layer, thereby increasing the capacitance of the PIP capacitor, and the structure is directly formed using the mask of the gate structure in the CELL region, and is also formed simultaneously when the gate structure is formed, so that no additional mask plate and process are required, and no additional production machine and time are required.
Therefore, with reference to fig. 4, a plurality of dummy gate structures 230 are formed at intervals on the sti structure 220, the longitudinal section of each dummy gate structure 230 is square, the embodiment of the present invention is rectangular, and the height of the longitudinal section of each dummy gate structure 230 may be 3900 angstroms to 4100 angstroms, for example, 4000 angstroms; the width of the dummy gate structure 230 may be 0.2 micrometers. There are gaps between the dummy gate structures 230, and the distance between adjacent dummy gate structures 230 may be 0.3 μm, so that the surfaces of the dummy gate structures 230 and the surface of the shallow trench isolation structure 220 form a sinusoidal surface (a shape of an undulation). The structure and method of the dummy gate structure 230 are the same as those of the gate structure, and include forming a gate oxide layer on the shallow trench isolation structure, forming a floating gate on the gate oxide layer, forming first side walls on the floating gate, forming second side walls between the first side walls, the second side walls covering the first side walls and the side walls of the floating gate and being connected to the substrate, and forming source lines between the second side walls. Although the dummy gate structure 230 is the same as the gate structure in the CELL region, the dummy gate structure 230 does not have any electrical function, but only serves to change the shape of the insulating layer to be formed later, i.e., serves to increase the height of a portion of the insulating layer.
Next, referring to fig. 5 and 6, a first layer of polysilicon 241 is formed on the dummy gate structure 230, the thickness of the first layer of polysilicon is 1710 angstroms to 2090 angstroms, and the first layer of polysilicon 241 is etched to form a sinusoidal word line polysilicon 242. The first polysilicon layer 241 may refer to the shape formed by the surfaces of the dummy gate structures 230 and the shallow trench isolation structures 220, the etching position is the position between the adjacent dummy gate structures 230, the etching position is at least one, preferably, the etching is performed between every two adjacent dummy gate structures 230, the etching thickness is about 2500 angstroms, and the longitudinal section of the trench formed after etching is rectangular. After etching, the remaining first polysilicon layer forms the word line polysilicon, so the word line polysilicon 240 is also in a sine wave shape (a shape of an undulation), the valley of the word line polysilicon 242 is located between the adjacent dummy gate structures 230, the height difference between the valley and the peak of the insulating layer of the sine wave is 2400 angstroms to 2600 angstroms, for example, the vertical height difference between the peak and the valley may be 2500 angstroms.
Next, with continued reference to fig. 7 and 8, an insulating layer 250 is formed on the word line polysilicon 242, the insulating layer 250 covers the surface of the word line polysilicon 242 and the side walls of the trenches formed by the peaks and valleys of the word line polysilicon 242, so that the profile of the insulating layer 250 is influenced by the shape of the word line polysilicon 242, and therefore the insulating layer 250 also has a wavy sine wave shape, and the valleys of the sine wave of the insulating layer 250 are opposite to the valleys of the word line polysilicon 242, that is, preferably, the valleys of the sine wave of the insulating layer 250 are located at the valleys of the word line polysilicon 242 in the horizontal plane. The upper surface of the insulating layer 250 is in a sine wave shape, the lower surface is also in an undulated shape, the undulated shapes of the upper surface and the lower surface are consistent, and the distances between the upper surface and the lower surface at any place are the same, so that the thickness of the insulating layer 250 is unique, and the thickness of the insulating layer 250 is as follows: 140 to 160 angstroms, for example, 780 angstroms. Further, the material of the insulating layer 250 includes an oxide, and specifically, may be silicon dioxide. The surface of the insulating layer 250 is wavy, which means that the surface area of the insulating layer 250 of the embodiment of the present invention is much larger than that of the insulating layer of the prior art, compared to the surface of the planar structure of the prior art. And it is also possible to obtain a larger surface area of the insulating layer 230 by reducing the width of the longitudinal section of the dummy gate structures 230 and the distance between the adjacent dummy gate structures 230. The insulating layer 230 serves as an insulating layer between the upper board and the lower board of the PIP capacitor, and the larger the area is, the larger the capacitance value of the PIP capacitor is.
Next, with reference to fig. 7, a second polysilicon layer is deposited on the insulating layer 250, and the second polysilicon layer fills the trenches formed between the peaks and the valleys of the insulating layer 250, so as to form a gate polysilicon 260. The wordline polysilicon 260 may serve as a lower plate of the PIP capacitor, the insulating layer 230 may serve as an insulating layer of the PIP capacitor, and the gate polysilicon may serve as an upper plate of the PIP capacitor. Since the insulating layer is in a sine wave shape, the surface area is increased, the relative area between the word line polysilicon 240 and the gate polysilicon 260 is increased, the thickness of the insulating layer 250 is not changed, and it can be known from C to E to S/d that the method for forming the PIP capacitor according to the embodiment of the present invention increases the value of S, so that the capacitance value can be increased. In C ═ E × S/d: c is the capacitance value, E is the dielectric constant, S is the relative area of the word line polysilicon 240 and the gate polysilicon 260, and d is the distance between the word line polysilicon 240 and the gate polysilicon 260, i.e., the thickness of the insulating layer 250.
With reference to fig. 8, the present invention further provides a PIP capacitor formed by using the above method for forming a PIP capacitor, including: a substrate 210; a shallow trench isolation structure 220 located within the substrate 210; a plurality of dummy gate structures 230 located at intervals on the shallow trench isolation structure 220, wherein the longitudinal section of the dummy gate structures 230 is square; word line polysilicon 242 and insulating layer 250, both in a sine wave shape, on the dummy gate structure 230, respectively; a gate polysilicon 260 on the insulating layer 250.
In summary, in the PIP capacitor and the forming method provided by the embodiments of the present invention, a plurality of spaced dummy gate structures are formed first, and the dummy gate structures make the insulating layer formed in a sine wave shape with undulating heights, so that the relative area between the word line polysilicon and the gate polysilicon is increased, thereby increasing the capacitance of the PIP capacitor. And because the dummy gate structure and the CELL area gate structure are formed at the same time, no additional photomask and process steps are needed, and the cost is not increased.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A method for forming a PIP capacitor includes:
providing a substrate, wherein the substrate comprises a CELL area and a PIP area;
forming a shallow trench isolation structure in the substrate of the PIP region;
forming a plurality of spaced grid structures on the substrate of the CELL area by using a light shield of the grid structure, and simultaneously forming a plurality of spaced pseudo grid structures on the shallow trench isolation structure by using the light shield of the grid structure, wherein the surface of the shallow trench isolation structure is exposed among the pseudo grid structures, and the longitudinal section of each pseudo grid structure is square;
word line polycrystalline silicon and an insulating layer which are all in a sine wave shape are sequentially formed on the pseudo gate structure;
and forming gate polysilicon on the insulating layer.
2. The method of forming a PIP capacitor of claim 1, wherein the dummy gate structure and the gate structure are the same.
3. The method of claim 1, wherein the dummy gate structures have a longitudinal cross-section with a width of 0.2 μm, a height of 3900 angstroms to 4100 angstroms, and a distance between adjacent dummy gate structures of 0.3 μm.
4. The method of forming a PIP capacitor of claim 1, wherein the method of forming the wordline polysilicon in a sine wave shape on the dummy gate structure includes:
and forming a first polycrystalline silicon layer to cover the surfaces of the pseudo gate structures and the shallow trench isolation structures positioned between the pseudo gate structures, etching the first polycrystalline silicon layer to form word line polycrystalline silicon in a sine wave shape, and positioning the wave trough of the sine wave between the adjacent pseudo gate structures.
5. The method of forming a PIP capacitor of claim 4, wherein the first polysilicon layer has a thickness of 1710-2090 angstroms.
6. The method of forming a PIP capacitor of claim 1, wherein the method of forming the insulating layer in a sine wave shape includes:
and depositing an oxide layer on the word line polysilicon in a sine wave shape, wherein the oxide layer is changed into a sine wave shape along with the shape of the word line polysilicon, and the wave trough of the sine wave of the insulating layer is opposite to the wave trough of the word line polysilicon.
7. The method of forming a PIP capacitor of claim 1, wherein the insulating layer has a thickness of 140 to 160 angstroms.
8. The method of forming a PIP capacitor of claim 1, wherein a height difference between a valley and a peak of the insulating layer of a sine wave is 2400 a to 2600 a.
9. The method of forming a PIP capacitor of claim 1, wherein the method of forming the gate polysilicon includes:
and depositing a second polysilicon layer on the insulating layer, wherein the second polysilicon layer fills the groove formed between the wave trough and the wave crest of the insulating layer.
10. A PIP capacitor formed using the method of forming a PIP capacitor of any one of claims 1 to 9, comprising:
a substrate;
a shallow trench isolation structure located within the substrate;
a plurality of dummy gate structures which are arranged on the shallow trench isolation structure at intervals, wherein the longitudinal section of each dummy gate structure is square;
word line polycrystalline silicon and an insulating layer which are respectively positioned on the pseudo gate structure and are in sine wave shapes;
and the gate polysilicon is positioned on the insulating layer.
CN202110961310.XA 2021-08-20 2021-08-20 PIP capacitor and forming method Pending CN113675337A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110961310.XA CN113675337A (en) 2021-08-20 2021-08-20 PIP capacitor and forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110961310.XA CN113675337A (en) 2021-08-20 2021-08-20 PIP capacitor and forming method

Publications (1)

Publication Number Publication Date
CN113675337A true CN113675337A (en) 2021-11-19

Family

ID=78544579

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110961310.XA Pending CN113675337A (en) 2021-08-20 2021-08-20 PIP capacitor and forming method

Country Status (1)

Country Link
CN (1) CN113675337A (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060077654A (en) * 2004-12-30 2006-07-05 동부일렉트로닉스 주식회사 Method of fabricating embossing-typed capacitor
KR20080037798A (en) * 2006-10-27 2008-05-02 동부일렉트로닉스 주식회사 Method for manufacturing analog capacitor
CN102117780A (en) * 2010-01-06 2011-07-06 上海华虹Nec电子有限公司 PIP (Polysilicon-Insulator-Polysilicon) capacitor forming method based on BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process
CN111403392A (en) * 2020-03-26 2020-07-10 上海华力微电子有限公司 Stacked capacitor, flash memory device and manufacturing method thereof
CN111969111A (en) * 2020-08-26 2020-11-20 上海华虹宏力半导体制造有限公司 Capacitor and manufacturing method thereof
CN113192927A (en) * 2021-04-27 2021-07-30 上海华虹宏力半导体制造有限公司 Manufacturing method of PIP capacitor

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060077654A (en) * 2004-12-30 2006-07-05 동부일렉트로닉스 주식회사 Method of fabricating embossing-typed capacitor
KR20080037798A (en) * 2006-10-27 2008-05-02 동부일렉트로닉스 주식회사 Method for manufacturing analog capacitor
CN102117780A (en) * 2010-01-06 2011-07-06 上海华虹Nec电子有限公司 PIP (Polysilicon-Insulator-Polysilicon) capacitor forming method based on BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process
CN111403392A (en) * 2020-03-26 2020-07-10 上海华力微电子有限公司 Stacked capacitor, flash memory device and manufacturing method thereof
CN111969111A (en) * 2020-08-26 2020-11-20 上海华虹宏力半导体制造有限公司 Capacitor and manufacturing method thereof
CN113192927A (en) * 2021-04-27 2021-07-30 上海华虹宏力半导体制造有限公司 Manufacturing method of PIP capacitor

Similar Documents

Publication Publication Date Title
US9978829B2 (en) Low impedance high density deep trench capacitor
US9178080B2 (en) Deep trench structure for high density capacitor
US7663207B2 (en) Semiconductor device
CN105575959A (en) Integrated circuit device
JP4777668B2 (en) MIM type capacitor
CN110970436A (en) Semiconductor structure and manufacturing method thereof
CN109326596A (en) The production method of semiconductor structure and capacitive connection pad with capacitive connection pad
US6784477B2 (en) Structure of a deep trench-type DRAM
CN100438040C (en) Structure of dynamic RAM
CN111725247A (en) Self-alignment etching method for drain-source contact hole of CIS chip
CN111009526A (en) Integrated assembly and method of forming an integrated assembly
US7678659B2 (en) Method of reducing current leakage in a metal insulator metal semiconductor capacitor and semiconductor capacitor thereof
US20230262965A1 (en) Memory structure and method of forming thereof
CN115332251A (en) Semiconductor structure and manufacturing method thereof
KR0137229B1 (en) Semiconductor memory device and fabrication method thereof
US5087951A (en) Semiconductor memory device transistor and cell structure
CN113675337A (en) PIP capacitor and forming method
CN113192927A (en) Manufacturing method of PIP capacitor
US11342333B2 (en) Semiconductor device
KR100368569B1 (en) Semiconductor device and its manufacturing method
KR100644526B1 (en) Method of fabricating embossing-typed capacitor
JPH06112429A (en) Semiconductor memory and manufacture method thereof
US7829928B2 (en) Semiconductor structure of a high side driver and method for manufacturing the same
KR101128726B1 (en) Manufacturing Method of a variable MIM capacitor
US6916671B2 (en) Gate oxide measurement apparatus

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination