CN113673690B - Underwater noise classification convolutional neural network accelerator - Google Patents
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Abstract
The invention discloses an underwater noise classification convolutional neural network accelerator, which comprises: the device comprises a DMA controller, a feature map transpose vector unit, a convolution kernel transpose vector unit, a plurality of minimum calculation units and a data cache pool; the DMA controller reads in the input characteristic diagram and the first layer convolution kernel; the feature map transposition vector unit completes calculation vector transposition according to the feature map to obtain a feature map vector, and writes the feature map vector into a data cache pool; the convolution kernel vector transferring unit is used for transferring a first convolution kernel vector according to the first layer of convolution kernels to obtain a convolution kernel vector, and writing the convolution kernel vector into a data cache pool; and each minimum calculation unit reads the feature map vector and the first convolution kernel vector in the data cache pool, performs dot multiplication on the feature map vector and the first convolution kernel vector to obtain a dot multiplication result, and stores the dot multiplication result in the data cache pool. The invention can adapt to FPGA devices with different resource conditions, and realizes an accelerator scheme for flexibly increasing and decreasing hardware parallelism.
Description
Technical Field
The invention belongs to the technical field of convolutional neural networks for underwater noise classification application, and particularly relates to an underwater noise classification convolutional neural network accelerator.
Background
The traditional underwater noise classification is to obtain classification results through experience by trained sonar staff and continuous monitoring sonar. This approach relies heavily on the sonar operator's experience and working state. The sonar signal can be converted into a one-dimensional digital signal after being amplified and sampled.
In recent years, convolutional neural networks have been widely used in deep learning for classification problems. A plurality of practical results show that the convolutional neural network has the characteristic of high recognition accuracy when the convolutional neural network is used for processing the classification problem. The underwater noise classification network is deployed in an embedded environment, and needs to face the problems of weak computing capacity and limited resources of a hardware platform.
Aiming at the special convolutional neural network formed by the underwater target classification problem, a special convolutional neural network accelerator can be used for realizing calculation force improvement, so that the real-time problem is solved.
In the related art, the convolutional neural network usually completes all convolutions, then performs activation and then pooling operation, and completes calculation acceleration in layers. The disadvantages of this approach are: each level needs a cache layer to store intermediate calculation results, and the consumption of cache resources is high; the scale of each layer of computing unit is fixed, and expansion or cutting cannot be performed according to the size of FPGA resources.
Disclosure of Invention
The invention solves the technical problems that: the accelerator scheme has the advantages that the defects of the prior art are overcome, the accelerator for the underwater noise classification convolutional neural network is provided, the accelerator can adapt to FPGA devices with different resource conditions, and the accelerator scheme for flexibly increasing and decreasing the hardware parallelism is realized.
The invention aims at realizing the following technical scheme: an underwater noise classification convolutional neural network accelerator comprising: the device comprises a DMA controller, a feature map transpose vector unit, a convolution kernel transpose vector unit, a plurality of minimum calculation units and a data cache pool; the DMA controller reads in the input characteristic diagram and the first layer convolution kernel; the feature map transposition vector unit completes calculation vector transposition according to the feature map to obtain a feature map vector, and writes the feature map vector into a data cache pool; the convolution kernel vector transferring unit is used for transferring a first convolution kernel vector according to the first layer of convolution kernels to obtain a convolution kernel vector, and writing the convolution kernel vector into a data cache pool; each minimum calculation unit reads the feature map vector and the first convolution kernel vector in the data cache pool, performs dot multiplication on the feature map vector and the first convolution kernel vector to obtain a dot multiplication result, and stores the dot multiplication result into the data cache pool; and the DMA controller reads the dot multiplication result in the data cache pool as an input characteristic diagram and a convolution kernel of the next layer until the calculation of the convolution layer number is completed.
In the underwater noise classification convolutional neural network accelerator, the data cache pool size Amax is obtained by the following formula:
Amax＝AI+MAX(AVi，APki，AO)+AVKi；
Wherein AI is the size of the input data buffer pool, AO is the size of the output data buffer pool, AVi is the size of the buffer pool after the data of each layer of characteristic map are diverted, AVki is the size of convolution kernel diverted, and APki is the size of each layer of data after pooling.
In the underwater noise classification convolutional neural network accelerator, for the case that A is larger than Amax, B=1 indicates that the system is not segmented, data can be completely not stored in the FPGA, and a DMA controller only needs to complete data reading and calculation result writing back once in the calculation process; for the case of a < Amax, b=max (AVi, APki, AO)/a, representing the input data decomposed into B blocks, if B is calculated as a fraction, then b=int (B) +1.
In the underwater noise classification convolutional neural network accelerator, the number V of the calculated vectors of the multiplier is obtained according to the number Kri of the convolutional kernels and the number Kci of the convolutional kernels.
In the above underwater noise classification convolutional neural network accelerator, the number of multipliers is calculated as v= MAX (Kri x Kci).
In the underwater noise classification convolutional neural network accelerator, the number V of the calculated vectors of the multiplier determines the throughput requirement of the data input of a single accelerator calculation unit.
In the underwater noise classification convolutional neural network accelerator, the minimum calculation unit is the minimum unit of the calculation unit, and vector multiplication, activation and pooling operations are realized.
In the underwater noise classification convolutional neural network accelerator, when the byte number A of the data cache pool is smaller than the size Amax of the data cache pool and the blocking parameter B is larger than 1, the DMA controller reads in the input feature map, converts the input feature map into the feature vector, and blocks the feature vector and writes the feature vector into the RAM outside the FPGA.
Compared with the prior art, the invention has the following beneficial effects:
(1) The convolution calculation process is multi-layer multiplexing, so that the storage multiplexing capacity in the accelerator can be enhanced;
(2) The invention can realize flexible configuration from small-sized FPGA to large-sized FPGA, and provides flexible hardware acceleration scheme for FPGAs with different level resources.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 is a block diagram of an underwater noise classification convolutional neural network accelerator provided by an embodiment of the present invention;
FIG. 2 is a block diagram of an embodiment of a multiplier-adder implementation provided by the present invention;
Fig. 3 is another block diagram of a multiplier-adder implementation provided by an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other. The invention will be described in detail below with reference to the drawings in connection with embodiments.
Fig. 1 is a block diagram of an underwater noise classification convolutional neural network accelerator provided by an embodiment of the present invention. As shown in FIG. 1, the underwater noise classification convolutional neural network accelerator comprises a DMA controller, a feature map transpose vector unit, a convolutional kernel transpose vector unit, a plurality of minimum calculation units and a data cache pool; wherein,
The DMA controller reads in the input characteristic diagram and the first layer convolution kernel; the feature map transposition vector unit completes calculation vector transposition according to the feature map to obtain a feature map vector, and writes the feature map vector into a data cache pool; the convolution kernel vector transferring unit is used for transferring a first convolution kernel vector according to the first layer of convolution kernels to obtain a convolution kernel vector, and writing the convolution kernel vector into a data cache pool; each minimum calculation unit reads the feature map vector and the first convolution kernel vector in the data cache pool, performs dot multiplication on the feature map vector and the first convolution kernel vector to obtain a dot multiplication result, and stores the dot multiplication result into the data cache pool; and the DMA controller reads the dot multiplication result in the data cache pool as an input characteristic diagram and a convolution kernel of the next layer until the calculation of the convolution layer number is completed.
The comprehensive script and the minimum calculation unit provided by the invention can be adapted to FPGA devices with different resource conditions, and the accelerator scheme for flexibly increasing and decreasing the hardware parallelism is realized.
The invention realizes the generation of the hardware accelerator through the comprehensive script, and the user is required to provide the following parameters in the comprehensive script: inputting the number C of the feature graphs, the height H of the feature graphs and the width W of the feature graphs; the number Cki of convolution kernels, the number Kri of the convolution kernels, the number Kci of the convolution kernels and the number Ksi of convolution steps are input respectively; the number Pr of the pooling unit lines, the number Pc of the pooling unit lines and the displacement length Ps of the pooling unit lines; a minimum number of calculation units M; data cache pool byte number a.
The minimum calculation unit is the minimum unit of the calculation unit in the invention, and can realize vector multiplication, activation and pooling operation. The types of the activation functions are configured in the comprehensive script, and for the condition that different convolution layers use different activation functions in one network, multiple activation functions can be synthesized, and the selection of the activation functions is completed through configuration options.
The convolutional neural network can realize the configuration of a minimum computing unit and a maximum N computing units, and the configuration quantity is determined by the real-time requirement of the system and the quantity of logic resources which can be provided by the FPGA.
FIG. 2 is a block diagram of an embodiment of a multiplier-adder implementation provided by the present invention; fig. 3 is another block diagram of a multiplier-adder implementation provided by an embodiment of the present invention. As shown in fig. 2 and 3, the invention realizes the FPGA chip which can adapt to different resource capacities by configuring the comprehensive options through the script based on the minimum calculation unit structure. The implementation process is as follows:
the following configuration is completed in the integrated script:
1) Inputting characteristic diagram parameters: C. h, W;
2) Inputting convolution kernel parameters: cki, kri, kci, ksi;
3) Pooling unit parameters: pr, pc, ps;
4) Minimum calculation unit parameters: m;
5) The byte number A of the data cache pool;
6) Number of convolutions: i;
The comprehensive script calculates the input data buffer pool size AI, the output data buffer pool size AO, the buffer pool size AVi after the transfer of the data of each layer of characteristic map, the convolution kernel transfer amount size AVki and the data size APki of each layer after the pooling according to the parameters 1) -4). Because of the pipelining relation in the calculation process of each convolution layer, after the calculation of one layer of convolution is completed, the next layer of convolution is carried out; the maximum amount of data which can exist simultaneously in each layer is considered in the script algorithm, the size of the cache pool is obtained, and the algorithm is as follows: amax=ai+max (AVi, APki, AO) + AVKi, where i (1, nk), nk is the number of convolutional layers.
And the script completes the setting of the blocking parameter B according to the parameters 5 and Amax. The algorithm for the B parameter is as follows:
For the case that A > Amax, B=1 indicates that the system is not blocked, the data can be completely not stored in the FPGA, and the DMA only needs to complete once data reading and calculation result writing back in the calculation process; for the case of a < Amax, b=max (AVi, APki, AO)/a, representing the input data decomposed into B blocks, if B is calculated as a fraction, then b=int (B) +1.
The multiplier calculates the vector number v= MAX (Kri x Kci). This parameter determines the throughput requirements of the individual accelerator computing unit data inputs.
After the configuration is completed, running a script, and realizing an accelerator circuit matched with the current FPGA resource quantity through a comprehensive tool. After the circuit is comprehensively completed and deployed to the FPGA, the calculation process is as follows:
in embodiment one, for a > Amax, B <1 is not blocked.
6) The DMA integrally reads in the input feature map and the first layer convolution kernel, and puts the input feature map and the first layer convolution kernel into a calculation buffer pool;
7) Starting a feature map transposition vector unit, completing calculation vector transposition, and writing the result into a calculation buffer pool;
8) Starting a convolution kernel vector transposition unit, completing the transposition of a first convolution kernel vector, and writing the result into a calculation buffer pool;
9) According to the minimum calculation unit parameter M, the allocation of the convolution calculation data stream is realized, and the number of entries of each calculation unit reading vector is determined by the size of the pooling unit after one convolution calculation is finished, namely Prx Pc.
10 After the vector enters a minimum calculation unit, finishing the point multiplication of the input feature map vector and the convolution kernel vector;
11 The calculation results are accumulated in a minimum calculation unit;
12 Adding the accumulated result to the bias;
13 The addition result in the previous step is activated;
14 Repeating the actions of 10) -13) until the designated number of units are pooled to complete the calculation;
15 Starting pooling operation, outputting a calculation result, and entering a data cache pool until all vector calculation is completed;
16 Using data in the data cache pool as an input feature map, reading the next layer of convolution kernel data into the data cache pool by using DMA, and repeating the steps of 7) -16) to complete data calculation;
17 Until the convolution calculation of the specified layer number of the convolution layer number i is completed, the operation behavior of the accelerator is stopped.
In embodiment two, for the case of A < Amax, B >1 is blocked.
And the DMA integrally reads in the feature map, converts the feature map into feature vectors, and then writes the feature vectors back into the RAM outside the FPGA in blocks.
The first block vector is then read back into the calculation unit for preparation for calculation.
18 And (3) executing the actions in the steps 6) to 14), starting a pooling operation, completing the calculation of the input characteristic data of the current block, and entering a data cache pool until the calculation of the vector of the current block is completed. The data cache pool results are written back to external RAM.
19 Initiating DMA reading the second block vector into the calculation unit, completing the calculation process described in step 18).
20 Reading all calculation results of the first layer convolution according to the blocks, repeating 18), 19) the appointed action until the convolution calculation of the appointed layer number of i is completed, and stopping the operation action of the accelerator.
The convolution calculation process is multi-layer multiplexing, so that the storage multiplexing capacity in the accelerator can be enhanced; the invention can realize flexible configuration from small-sized FPGA to large-sized FPGA, and provides flexible hardware acceleration scheme for FPGAs with different level resources.
Although the present invention has been described in terms of the preferred embodiments, it is not intended to be limited to the embodiments, and any person skilled in the art can make any possible variations and modifications to the technical solution of the present invention by using the methods and technical matters disclosed above without departing from the spirit and scope of the present invention, so any simple modifications, equivalent variations and modifications to the embodiments described above according to the technical matters of the present invention are within the scope of the technical matters of the present invention.
Claims (8)
1. An underwater noise classification convolutional neural network accelerator, comprising: the device comprises a DMA controller, a feature map transpose vector unit, a convolution kernel transpose vector unit, a plurality of minimum calculation units and a data cache pool; wherein,
The DMA controller reads in the input characteristic diagram and the first layer convolution kernel; the feature map transposition vector unit completes calculation vector transposition according to the feature map to obtain a feature map vector, and writes the feature map vector into a data cache pool; the convolution kernel vector transferring unit is used for transferring a first convolution kernel vector according to the first layer of convolution kernels to obtain a convolution kernel vector, and writing the convolution kernel vector into a data cache pool; and each minimum calculation unit reads the feature map vector and the first convolution kernel vector in the data cache pool, performs dot multiplication on the feature map vector and the first convolution kernel vector to obtain a dot multiplication result, and stores the dot multiplication result in the data cache pool.
2. The underwater noise classification convolutional neural network accelerator of claim 1, wherein: the data cache pool size Amax is obtained by the following formula:
Amax＝AI+MAX(AVi，APki，AO)+AVKi；
Wherein AI is the size of the input data buffer pool, AO is the size of the output data buffer pool, AVi is the size of the buffer pool after the data of each layer of characteristic map are diverted, AVki is the size of convolution kernel diverted, and APki is the size of each layer of data after pooling.
3. The underwater noise classification convolutional neural network accelerator of claim 2, wherein: for the case that a > Amax, b=1 indicates that the system is not blocked, the data can be completely not stored in the FPGA, and the DMA controller only needs to complete once data reading and calculation result writing back in the calculation process; for the case of a < Amax, b=max (AVi, APki, AO)/a, representing the input data decomposed into B blocks, if B is calculated as a fraction, then b=int (B) +1.
4. The underwater noise classification convolutional neural network accelerator of claim 2, wherein: and obtaining the number V of the calculated vectors of the multiplier according to the number Kri of the convolution kernel and the number Kci of the convolution kernel.
5. The underwater noise classification convolutional neural network accelerator of claim 4, wherein: the number of the calculated vectors of the multiplier is v= MAX (Kri x Kci).
6. The underwater noise classification convolutional neural network accelerator of claim 5, wherein: the number of multiplier calculation vectors V determines the throughput requirements of the data inputs of the individual accelerator calculation units.
7. The underwater noise classification convolutional neural network accelerator of claim 5, wherein: the minimum computation unit is the minimum unit of computation units, implementing vector multiplication, activation, and pooling operations.
8. The underwater noise classification convolutional neural network accelerator of claim 2, wherein: when the byte number A of the data cache pool is smaller than the size Amax of the data cache pool and the blocking parameter B is larger than 1, the DMA controller reads in the input feature map, converts the input feature map into a feature vector, and then blocks and writes the feature vector into a RAM outside the FPGA.
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