CN113672373A

CN113672373A - Thread binding method and device and electronic equipment

Info

Publication number: CN113672373A
Application number: CN202111004253.2A
Authority: CN
Inventors: 滕开恩; 马东星; 魏齐良
Original assignee: Zhejiang Dahua Technology Co Ltd
Current assignee: Zhejiang Dahua Technology Co Ltd
Priority date: 2021-08-30
Filing date: 2021-08-30
Publication date: 2021-11-19
Anticipated expiration: 2041-08-30

Abstract

A method, a device and an electronic device for thread binding are provided, wherein the method comprises the following steps: screening and isolating N CPUs in all CPUs according to a preset rule, sequencing all threads according to the sequence of occupying the CPU utilization rate from high to low, screening the first N threads, and binding the threads of the unbound CPUs in the first N threads with the threads of the unbound CPUs in the N CPUs. By the method, the same number of CPUs and threads are screened out, the first N threads with the highest CPU occupancy rate in the system are circularly obtained according to the preset period, the binding states of the N CPUs and the N threads are checked, and the N CPUs and the N threads with the high CPU occupancy rates can be bound one to one, so that the bidirectional binding of the CPUs and the threads is realized, the threads can be efficiently executed on the CPUs, and the thread execution efficiency and the thread processing efficiency of the CPUs are improved.

Description

Thread binding method and device and electronic equipment

Technical Field

The present application relates to the field of data storage technologies, and in particular, to a method and an apparatus for thread binding, and an electronic device.

Background

In a linux operating system, each CPU has a running queue, threads in a ready state share a certain CPU, the threads are dispatched in turn in a CPU cycle, the CPU determines the running time allocated to each thread according to the priority owned by the threads, the higher the priority of the threads is, the more time the CPU can occupy the running time of the CPU in a dispatching cycle, when the CPU is dispatched from one thread to the next thread, the thread context switching needs to be executed, the excessive thread switching causes frequent context switching, and the CPU is wasted in the context switching process without service relation, so that the CPU efficiency is influenced;

at present, a method for binding a multi-queue network card with a CPU is adopted, one CPU can run a plurality of threads, the plurality of threads in the CPU running queue can still run in turn, and the network card packet receiving thread is frequently interrupted by other threads, so that the processing efficiency of the CPU on the network card packet receiving thread is low.

In addition, the adopted method is a data compression method, a CPU core and a compression transaction thread are bound in advance, other business threads with high CPU occupancy rate are not dynamically bound according to the actual business condition of the system, and the current CPU is still bound after the compression transaction thread finishes working, so the current CPU is idle, and the threads with high CPU occupancy rate cannot be bound to the current CPU at the moment, so the processing efficiency of the CPU on the threads is lower.

Disclosure of Invention

The application provides a method, a device and an electronic device for binding threads, wherein the threads with high CPU occupancy rates are dynamically bound and monopolize the CPUs through a bidirectional binding method of the CPUs and the threads, the threads with high CPU occupancy rates can be bound to the corresponding CPUs, efficient execution of the threads on the CPUs is realized, and therefore execution efficiency of the threads and efficiency of processing the threads by the CPUs are improved.

In a first aspect, the present application provides a method for thread binding, where the method includes:

screening and isolating N CPUs from all CPUs according to a preset rule, wherein the CPUs are multiple independent CPUs or multiple CPUs simulated by integrating multiple cores in a single independent CPU;

sequencing all threads according to the sequence of occupying the CPU utilization rate from high to low, and screening out the first N threads;

and binding the thread of the unbound CPU in the first N threads with the CPU of the unbound thread in the N CPUs.

This application is through screening the CPU and the thread of the same quantity, checks the binding state of N CPU and N thread makes the thread that the CPU occupancy rate is high can both bind to the CPU with the mode one to one, ensures N CPU with N thread can carry out the binding one to realize the two-way binding of CPU and thread, make the thread can high-efficiently carry out on CPU, improve the efficiency of execution of thread and CPU processing thread.

In one possible design, screening and isolating N CPUs from all CPUs according to a preset rule, where the CPU is a plurality of independent CPUs or a plurality of CPUs simulated by integrating a plurality of cores in a single independent CPU, and the method includes:

the preset rule is that N CPUs consistent with the preset CPU serial number are screened out according to the matching of the serial number of the input CPU and the preset CPU serial number;

or screening N CPUs in an idle state from all CPUs;

or screening N CPUs according to the number of CPU occupancy rates sequenced by threads exceeding a preset value;

and removing the screened N CPUs from the thread scheduler of the operating system, and isolating the N CPUs.

In one possible design, binding a thread of an unbound thread of the first N threads with a CPU of an unbound thread of the N CPUs includes:

circularly acquiring the first N threads with the highest CPU occupancy rate in the system according to a preset period, and checking the binding states of the N CPUs and the N threads;

if the CPUs in the N CPUs have binding threads, binding the CPUs according to a preset rule;

and if the CPU in the N CPUs is not bound to the thread, binding the thread which is not bound to the CPU in the first N threads with the CPU.

In one possible design, the binding the CPU according to a preset rule includes:

judging whether the bound threads are threads in the first N threads or not;

if yes, maintaining the binding state of the CPU and the thread;

and if not, unbinding the thread bound by the CPU.

In a second aspect, the present application provides an apparatus for thread binding, the apparatus comprising:

the screening module is used for screening and isolating N CPUs from all CPUs according to a preset rule, wherein the CPUs are multiple independent CPUs or multiple CPUs simulated by integrating multiple cores in a single independent CPU;

the sequencing module is used for sequencing all threads according to the sequence of the occupation of the CPU from high to low, and screening out the first N threads;

and the binding module is used for binding the thread of the unbound CPU in the first N threads with the CPU of the unbound thread in the N CPUs.

In one possible design, the screening module is specifically configured to screen out N CPUs that are consistent with a preset CPU serial number according to the preset rule by matching the serial number of the input CPU with the preset CPU serial number; or screening N CPUs in an idle state from all CPUs; or screening N CPUs according to the number of CPU occupancy rates sequenced by threads exceeding a preset value; and removing the screened N CPUs from the thread scheduler of the operating system, and isolating the N CPUs.

In one possible design, the binding module is specifically configured to cyclically acquire, according to a preset period, the first N threads with the highest CPU occupancy rate in the system and check the binding states of the N CPUs and the N threads; if the CPUs in the N CPUs have binding threads, binding the CPUs according to a preset rule; and if the CPU in the N CPUs is not bound to the thread, binding the thread which is not bound to the CPU in the first N threads with the CPU.

In one possible design, the binding module is further configured to determine whether a bound thread is a thread of the first N threads; if yes, maintaining the binding state of the CPU and the thread; and if not, unbinding the thread bound by the CPU.

In a third aspect, the present application provides an electronic device, comprising:

a memory for storing a computer program;

and the processor is used for realizing the steps of the thread binding method when executing the computer program stored in the memory.

In a fourth aspect, a computer-readable storage medium has stored therein a computer program which, when executed by a processor, implements one of the above-described method steps of thread binding.

For each of the first to fourth aspects and possible technical effects of each aspect, please refer to the above description of the possible technical effects for the first aspect or each possible solution in the first aspect, and no repeated description is given here.

Drawings

FIG. 1 is a flow chart of method steps for thread binding provided herein;

FIG. 2 is a schematic structural diagram of a thread binding apparatus provided in the present application;

fig. 3 is a schematic structural diagram of an electronic device provided in the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more clear, the present application will be further described in detail with reference to the accompanying drawings. The particular methods of operation in the method embodiments may also be applied to apparatus embodiments or system embodiments. It should be noted that "a plurality" is understood as "at least two" in the description of the present application. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. A is connected with B and can represent: a and B are directly connected and A and B are connected through C. In addition, in the description of the present application, the terms "first," "second," and the like are used for descriptive purposes only and are not intended to indicate or imply relative importance nor order to be construed.

The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

At present, one CPU binds a plurality of threads, the CPU runs a plurality of threads in turn, the thread running is frequently interrupted by thread switching, the execution speed of the thread is influenced, and the processing efficiency of the CPU to the thread is low, or one CPU binds one thread, and after the thread finishes working, the current CPU is still bound, so the current CPU is idle, at the moment, the threads with high CPU occupancy rate cannot be bound to the current CPU, and the processing efficiency of the CPU to the thread is low, so the low execution efficiency of the thread and the low processing efficiency of the CPU to the thread become the problems to be solved.

In order to solve the above problem, an embodiment of the present application provides a method for binding a thread, so as to implement bidirectional binding between a CPU and the thread, improve execution efficiency of the thread, and improve processing efficiency of the CPU on the thread. The method and the device in the embodiment of the application are based on the same technical concept, and because the principles of the problems solved by the method and the device are similar, the device and the embodiment of the method can be mutually referred, and repeated parts are not repeated.

Referring to fig. 1, the present application provides a method for binding a thread, which can improve the execution efficiency of the thread and the processing efficiency of a CPU on the thread, and the implementation flow of the method is as follows:

step S1: and screening and isolating N CPUs in all CPUs according to a preset rule.

Before thread binding is performed, a CPU which can be used for binding threads needs to be screened and isolated, and in the embodiment of the present application, the screening of the CPU may be performed in the following manner, where the CPU is multiple independent CPUs or multiple CPUs simulated by integrating multiple cores inside a single independent CPU:

the first method is as follows: in the method, the CPUs are screened according to the serial numbers of the CPUs, namely, the serial numbers of the input CPUs are matched with the serial numbers of the preset CPUs, and if N consistent serial numbers are matched, the N required CPUs are screened, wherein the serial numbers of the preset CPUs are automatically sorted from 0 by a system.

Such as: the preset CPU serial numbers are {0, 1, 2, 3, 4, 5, 6 and 7}, the input CPU serial numbers are {2, 3 and 5}, the {2, 3 and 5} are compared with the {0, 1, 2, 3, 4, 5, 6 and 7}, the result of comparison is {2, 3 and 5}, and the CPUs corresponding to the serial numbers 2, 3 and 5 are screened out.

By adopting the mode, the CPUs are screened according to the serial numbers of the CPUs, so that the required CPUs can be screened out quickly, and the purpose of screening out the required CPUs can be achieved in a short time.

The second method comprises the following steps: in this manner, the value of the number N of screened CPUs is determined according to the number of CPUs in the idle state.

Reading the current state of the CPU, and determining the number of the CPUs in an idle state;

and reading and recording the serial number of the screened CPU in the idle state.

Such as: and reading the current CPU state, if 5 CPUs in the idle state exist, determining that the number of the screened CPUs is 5, and reading and recording the serial number of the currently screened CPUs.

Through the mode, the CPUs are screened according to the idle states of the CPUs, the CPUs in the idle states can be screened, and waste of CPU resources is avoided.

The third method comprises the following steps: in the method, the value of the number N of screened CPUs is determined according to the number of CPUs with occupancy rates of threads exceeding the preset value;

counting the CPU occupancy rates of all threads, and sequencing the CPU occupancy rates according to a descending order to obtain a sequencing result;

and counting the number exceeding the preset value occupancy rate in the sequencing result, and taking the counted number as the number of screened CPUs.

Such as: the CPU occupancy rates are respectively sorted from large to small by 45%, 32%, 23%, 12%, 8%, 7%, 6%, 5%, 4% and 3% … …, the corresponding threads are sorted by a, b, c, d, e, f, g, h, i and j … …, the preset value is 30%, and two threads with the CPU occupancy rates exceeding 30% are: a. and b, determining the value of the screened CPU number N to be 2.

Through the mode, the CPUs bound by the threads with high CPU occupancy rates are screened out, the number N of the CPUs to be isolated is determined, and the N CPUs with the most posterior serial numbers are screened out, so that the CPUs with more proper number can be screened out and isolated according to the service load condition of a specific system.

The threads are bound to the N isolated CPUs through system call of the operating system, and the threads can be operated on the N isolated CPUs, so that the N CPUs are screened out through the three modes, the serial number parameters of the N CPUs are input into the operating system, and the CPUs corresponding to the input serial numbers are removed from the thread scheduler in the next starting process of the operating system, so that the purpose of isolating the N CPUs is achieved, and the bidirectional binding of the CPUs and the threads is convenient to realize.

Step S2: and sequencing all threads according to the occupation rate of the CPU from high to low, and screening the first N threads.

In order to ensure that the threads with higher CPU occupancy rates can be preferentially bound or preferentially processed, the CPU occupancy rates of all the threads are sorted from large to small, and the threads corresponding to the first N values are screened out.

Such as: when N is 8, the system has 8 CPUs or 8-core CPUs, all threads are sorted according to the values of the CPU occupancy rates, and the sorting of the values of the current CPU occupancy rates of all the threads from high to low is sequentially as follows: 23%, 12%, 9%, 8.5%, 8%, 7%, 6%, 5%, 4% … …, the corresponding threads being in order: a. b, c, d, e, f, g, h and i … …, wherein the threads with the current CPU occupancy rate of the first 8 bits are screened as follows: a. b, c, d, e, f, g and h.

By the mode, the N threads with high CPU occupancy rates are screened, and one-to-one binding of the N threads with high CPU occupancy rates and the N CPUs is facilitated.

Step S3: and binding the thread of the unbound CPU in the first N threads with the CPU of the unbound thread in the N CPUs.

And circularly acquiring the first N threads with the highest CPU occupancy rate in the system by taking a preset period as a unit, and checking the binding states of the N CPUs and the N threads.

If the CPU in the N CPUs has a bound thread, the CPU is in a bound state currently; extracting the threads currently bound with the CPU, and reading whether consistent threads exist in the N threads; if not, unbinding the current CPU and the thread, and binding the thread which is not bound in the N threads with the CPU; and if so, retaining the thread currently bound with the CPU.

If the CPU in the N CPUs is not bound to the thread, the CPU is in an unbound state currently; and binding the thread in an unbound state in the N threads to the CPU.

Such as: and reordering the CPU occupancy rates of the threads according to a preset period, wherein the preset period time is 5min, determining the current N threads, and checking the binding states of the CPUs in the N CPUs and the N threads.

If the thread is detected to be in a binding state, judging whether the thread bound by the CPU is a thread in the N threads, if so, maintaining the binding state of the CPU and the thread; and if not, unbinding the thread bound by the CPU.

In one possible design, after the threads bound to the CPU are unbound, in order to achieve bidirectional binding between the CPU and the threads, the threads in an unbound state of the N threads need to be bound to the current CPU.

And if the thread is detected to be in an unbound state, binding the thread in the unbound state in the N threads to the current CPU.

Through the mode, the binding states of the N CPUs and the N threads are periodically and circularly checked, so that the threads with high CPU occupancy rate can be bound to the CPUs and monopolize the CPUs, and the threads can be efficiently executed on the CPUs.

According to the method, the binding state of the N CPUs and the N threads is periodically and circularly checked, the threads in the N threads are bound to the CPUs in the N CPUs, the quantity of the CPUs is equal to that of the threads, the CPUs are bound to the threads one to one, the two-way binding of the CPUs and the threads is realized, the threads can be efficiently executed on the CPUs, and the thread executing efficiency and the thread processing efficiency of the CPUs are improved.

Based on the same inventive concept, an embodiment of the present application further provides a thread binding apparatus, where the thread binding apparatus is configured to implement a function of a thread binding method, and with reference to fig. 2, the apparatus includes:

the screening module 201 is configured to screen and isolate N CPUs from all CPUs according to a preset rule;

the sorting module 202 is configured to sort all the threads in an order from a large CPU utilization rate to a small CPU utilization rate, and screen out the first N threads;

a binding module 203, configured to bind a thread of an unbound CPU in the first N threads with a CPU of an unbound thread in the N CPUs.

In a possible design, the screening module 201 is specifically configured to screen, according to the preset rule, N CPUs that are consistent with a preset CPU serial number according to matching between the serial number of the input CPU and the preset CPU serial number; or screening N CPUs in an idle state from all CPUs; or screening N CPUs according to the number of CPU occupancy rates sequenced by threads exceeding a preset value; and removing the screened N CPUs from the thread scheduler of the operating system, and isolating the N CPUs.

In a possible design, the binding module 203 is specifically configured to cyclically acquire, according to a preset period, the first N threads with the highest CPU occupancy rate in the system and check the binding states of the N CPUs and the N threads, bind the CPUs of the N CPUs according to a preset rule if the CPUs of the N have bound threads, and bind the threads not bound with the CPUs of the first N threads with the CPUs of the N CPUs if the CPUs of the N have no bound threads.

In a possible design, the binding module 203 is further configured to determine whether a bound thread is a thread in the first N threads, maintain a binding state between the CPU and the thread if the bound thread is a thread in the first N threads, and unbundle the thread bound by the CPU if the bound thread is not a thread in the first N threads.

Based on the same inventive concept, an embodiment of the present application further provides an electronic device, where the electronic device can implement the function of the thread binding apparatus, and with reference to fig. 3, the electronic device includes:

at least one processor 301 and a memory 302 connected to the at least one processor 301, in this embodiment, a specific connection medium between the processor 301 and the memory 302 is not limited in this application, and fig. 3 illustrates an example where the processor 301 and the memory 302 are connected through a bus 300. The bus 300 is shown in fig. 3 by a thick line, and the connection between other components is merely illustrative and not limited thereto. The bus 300 may be divided into an address bus, a data bus, a control bus, etc., and is shown with only one thick line in fig. 3 for ease of illustration, but does not represent only one bus or type of bus. Alternatively, the processor 301 may also be referred to as a controller, without limitation to name a few.

In the embodiment of the present application, the memory 302 stores instructions executable by the at least one processor 301, and the at least one processor 301 can execute the thread binding method discussed above by executing the instructions stored in the memory 302. The processor 301 may implement the functions of the various modules in the apparatus shown in fig. 2.

The processor 301 is a control center of the apparatus, and may connect various parts of the entire control device by using various interfaces and lines, and perform various functions of the apparatus and process data by operating or executing instructions stored in the memory 302 and calling up data stored in the memory 302, thereby performing overall monitoring of the apparatus.

In one possible design, processor 301 may include one or more processing units, and processor 301 may integrate an application processor that primarily handles operating systems, user interfaces, application programs, and the like, and a modem processor that primarily handles wireless communications. It will be appreciated that the modem processor described above may not be integrated into the processor 301. In some embodiments, the processor 301 and the memory 302 may be implemented on the same chip, or in some embodiments, they may be implemented separately on separate chips.

The processor 301 may be a general-purpose processor, such as a Central Processing Unit (CPU), digital signal processor, application specific integrated circuit, field programmable gate array or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or the like, that may implement or perform the methods, steps, and logic blocks disclosed in embodiments of the present application. A general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the thread binding method disclosed in the embodiments of the present application may be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor.

Memory 302, which is a non-volatile computer-readable storage medium, may be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. The Memory 302 may include at least one type of storage medium, and may include, for example, a flash Memory, a hard disk, a multimedia card, a card-type Memory, a Random Access Memory (RAM), a Static Random Access Memory (SRAM), a Programmable Read Only Memory (PROM), a Read Only Memory (ROM), a charge Erasable Programmable Read Only Memory (EEPROM), a magnetic Memory, a magnetic disk, an optical disk, and so on. The memory 302 is any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to such. The memory 302 in the embodiments of the present application may also be circuitry or any other device capable of performing a storage function for storing program instructions and/or data.

By programming the processor 301, the code corresponding to one of the thread binding methods described in the foregoing embodiments may be solidified into the chip, so that the chip can perform one of the thread binding steps of the embodiment shown in fig. 1 when running. How to program the processor 301 is well known to those skilled in the art and will not be described herein.

Based on the same inventive concept, the present application also provides a storage medium storing computer instructions, which when executed on a computer, cause the computer to perform the thread binding method discussed above.

In some possible embodiments, the present application provides that the various aspects of a method of thread binding may also be implemented in the form of a program product comprising program code means for causing a control device to perform the steps of a method of thread binding according to various exemplary embodiments of the present application described above in this specification, when the program product is run on an apparatus.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. A method of thread binding, comprising:

2. The method of claim 1, wherein the screening and isolating N CPUs among all CPUs according to a preset rule comprises:

or screening N CPUs in an idle state from all CPUs;

3. The method of claim 1, wherein said binding threads of unbound ones of the first N threads with CPUs of unbound ones of the N CPUs, comprises:

4. The method of claim 3, wherein said binding said CPU according to a preset rule comprises:

judging whether the bound threads are threads in the first N threads or not;

if yes, maintaining the binding state of the CPU and the thread;

and if not, unbinding the thread bound by the CPU.

5. An apparatus for thread binding, the apparatus comprising:

the screening module is used for screening and isolating N CPUs in all CPUs according to a preset rule;

6. The apparatus according to claim 5, wherein the screening module is specifically configured to screen out N CPUs that are consistent with a preset CPU serial number according to matching between a serial number of an input CPU and the preset CPU serial number, or screen out N CPUs in an idle state among all CPUs, or screen out N CPUs according to a number of CPU occupancy rates sorted by threads exceeding a preset value.

7. The apparatus according to claim 5, wherein the binding module is specifically configured to cyclically check the binding states of the N CPUs and the N threads according to a preset period, bind the CPUs of the N CPUs according to a preset rule if the CPUs of the N CPUs have a bound thread, and bind the threads that are not bound to the CPUs of the first N threads to the CPUs if the CPUs of the N CPUs do not have a bound thread.

8. The apparatus of claim 5, wherein the binding module is further configured to determine whether a bound thread is a thread of the first N threads, maintain a bound state between the CPU and the thread if the bound thread is a thread of the first N threads, and unbundle the thread bound by the CPU if the bound thread is not a thread of the first N threads.

9. An electronic device, comprising:

a memory for storing a computer program;

a processor for implementing the method steps of any one of claims 1-4 when executing the computer program stored on the memory.

10. A computer-readable storage medium, characterized in that a computer program is stored in the computer-readable storage medium, which computer program, when being executed by a processor, carries out the method steps of any one of claims 1-4.