CN113659078B - Synaptic transistor device based on polyimide novel gate insulating layer and preparation method thereof - Google Patents
Synaptic transistor device based on polyimide novel gate insulating layer and preparation method thereof Download PDFInfo
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- JOTQIXXCBHIDKJ-UHFFFAOYSA-N 1-ethyl-3-methylimidazolidine Chemical compound CCN1CCN(C)C1 JOTQIXXCBHIDKJ-UHFFFAOYSA-N 0.000 claims description 4
- JVERADGGGBYHNP-UHFFFAOYSA-N 5-phenylbenzene-1,2,3,4-tetracarboxylic acid Chemical compound OC(=O)C1=C(C(O)=O)C(C(=O)O)=CC(C=2C=CC=CC=2)=C1C(O)=O JVERADGGGBYHNP-UHFFFAOYSA-N 0.000 claims description 4
- YTPLMLYBLZKORZ-UHFFFAOYSA-N Thiophene Chemical group C=1C=CSC=1 YTPLMLYBLZKORZ-UHFFFAOYSA-N 0.000 claims description 4
- 235000010290 biphenyl Nutrition 0.000 claims description 4
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- 125000001889 triflyl group Chemical group FC(F)(F)S(*)(=O)=O 0.000 claims description 3
- XUCRLOWTZDEVDG-UHFFFAOYSA-N 2-(3-bromohexyl)thiophene Chemical compound CCCC(Br)CCC1=CC=CS1 XUCRLOWTZDEVDG-UHFFFAOYSA-N 0.000 claims description 2
- FXHOOIRPVKKKFG-UHFFFAOYSA-N N,N-Dimethylacetamide Chemical compound CN(C)C(C)=O FXHOOIRPVKKKFG-UHFFFAOYSA-N 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- RTZKZFJDLAIYFH-UHFFFAOYSA-N ether Substances CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 claims description 2
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- 229930192474 thiophene Natural products 0.000 claims description 2
- NXDMHKQJWIMEEE-UHFFFAOYSA-N 4-(4-aminophenoxy)aniline;furo[3,4-f][2]benzofuran-1,3,5,7-tetrone Chemical compound C1=CC(N)=CC=C1OC1=CC=C(N)C=C1.C1=C2C(=O)OC(=O)C2=CC2=C1C(=O)OC2=O NXDMHKQJWIMEEE-UHFFFAOYSA-N 0.000 claims 1
- 238000009413 insulation Methods 0.000 claims 1
- 229920003223 poly(pyromellitimide-1,4-diphenyl ether) Polymers 0.000 claims 1
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- ZXMGHDIOOHOAAE-UHFFFAOYSA-N 1,1,1-trifluoro-n-(trifluoromethylsulfonyl)methanesulfonamide Chemical compound FC(F)(F)S(=O)(=O)NS(=O)(=O)C(F)(F)F ZXMGHDIOOHOAAE-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
- H10K10/471—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising only organic materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
Abstract
The invention discloses a synaptic transistor device based on a polyimide novel gate insulating layer and a preparation method thereof. The artificial synapse device structure comprises: a part of gate insulating layer is distributed on the substrate, and a semiconductor layer and a metal layer are sequentially arranged on the gate insulating layer; the gate insulating layer is made of polyimide material doped with ionic liquid, and the semiconductor layer is poly-3-hexylthiophene (P3 HT). The synaptic transistor device of the invention has the advantages of high sensitivity, low power consumption, wide working voltage range and the like.
Description
Technical Field
The invention belongs to the field of semiconductor devices, and particularly relates to a synaptic transistor electronic device.
Background
Computing systems based on von neumann structures have not been able to achieve rapid, accurate and intelligent processing of massive information due to separation of storage and computing modules, and particularly many short boards are exposed in pattern recognition and deep learning. Meanwhile, the high intelligence and the powerful computing and processing capacity of the human brain make the intelligent brain-like computing more and more widely focused.
The human brain is a complex and bulky neural network system that is capable of processing large amounts of nonlinear data in parallel while consuming very low amounts of energy. The human brain is composed of nearly trillion neurons, with thousands of synapses between each neuron. The most basic information transmission, processing and storage unit of the neural computing system based on the neural network is synapse, which provides a direct research model and basis for brain-like research. Therefore, the design and manufacture of novel artificial synapse devices with small size, low energy consumption and high sensitivity are the most critical tasks at present for realizing multiple complex functions of memory, calculation, cognition and the like of human brain on the hardware level. The novel artificial synapse device is a basic functional unit in a human brain-imitating computer, is used in the emerging fields of intelligent robots, medical diagnosis of difficult and complicated diseases and the like, and has important significance for promoting the development of new generation artificial intelligence.
Disclosure of Invention
The invention aims to solve the problems of larger power consumption, smaller working voltage range and the like of an organic polymer synaptic transistor device, and provides a synaptic transistor device based on a novel polyimide gate insulating layer and a preparation method thereof. The device takes polyimide doped with ionic liquid 1-ethyl-3-methylimidazoline bis (trifluoromethylsulfonyl) imide ([ EMIM ] [ TFSI ]) as a gate insulating layer, and poly 3-hexylthiophene (P3 HT) as a semiconductor layer material; in the preparation, ionic liquid [ EMIM ] [ TFSI ] and PMDA-ODA type polyimide are used as insulating layer raw materials, and spin coating and evaporation processes are respectively utilized to prepare the three-terminal synaptic transistor device with the substrate/gate insulating layer/semiconductor layer/metal electrode structure on the indium tin oxide conductive glass substrate.
The technical scheme of the invention is as follows:
a novel gate insulating layer-based synaptic transistor device, the artificial synaptic device structure comprising: a part of gate insulating layer is distributed on the substrate, and a semiconductor layer and a metal layer are sequentially arranged on the gate insulating layer;
the substrate is made of glass;
the gate insulating layer is made of polyimide material doped with ionic liquid, and the mass of the ionic liquid is 5-20% of that of the gate insulating layer; the thickness is 2-20 micrometers;
the semiconductor layer is a thiophene polymer and has a thickness of 30-100 nanometers;
the metal layer is a left metal electrode and a right metal electrode on the surface of the semiconductor layer, and the metal layer is made of gold;
the area of the gate insulating layer is 70-90% of the area of the substrate.
The horizontal distance between the left electrode and the right electrode is 100-150 micrometers, and the thickness is 80-100 nanometers.
The substrate is quartz glass, silicon wafer or indium tin oxide conductive glass.
The polyimide material comprises, but is not limited to, one of BPEDA-ODA type polyimide, PMDA-ODA type polyimide or BPDA-ODA type polyimide;
the ionic liquid comprises but is not limited to one of 1-ethyl-3-methylimidazoline bis (trifluoromethylsulfonyl) imine ([ EMIM ] [ TFSI ]), 1-ethyl-3-methylimidazole tetrafluoroborate ([ EMIM ] BF 4) and 1-ethyl-3-methylimidazole hexafluorophosphate ([ EMIM ] PF 6).
The semiconductor layer is polythiophene, poly 3-hexyl thiophene or poly 3-bromohexyl thiophene.
The preparation method of the synaptic transistor device based on the polyimide novel gate insulating layer comprises the following steps:
(1) Sequentially ultrasonically cleaning a substrate by deionized water, acetone and isopropanol, drying the surface of the substrate by nitrogen, and putting the substrate into an ultraviolet cleaning machine for 15-20 minutes;
(2) Dropwise adding the polyimide precursor solution onto the substrate in the step (1) in a glove box, spin-coating for 20-40 seconds at a speed of 500-2000 revolutions per minute by using a spin coater, placing the substrate on a heating plate, and heating for 20-40 minutes at 150-250 ℃ to obtain a gate insulating layer;
wherein the polyimide precursor solution is prepared from ionic liquid and 10-20% by mass of polyamic acid solution; mixing according to the mass ratio of 1 to 10-20. The polyamic acid solution is specifically one of poly (biphenyl di-ether dianhydride-co-4, 4' -diaminodiphenyl ether) (BPEDA-ODA) polyamic acid solution, poly (pyromellitic dianhydride-co-4, 4' -diaminodiphenyl ether) (PMDA-ODA) polyamic acid solution or poly (biphenyl tetracarboxylic dianhydride-co-4, 4' -diaminodiphenyl ether) (BPDA-ODA) polyamic acid solution; wherein the solvent in the BPEDA-ODA acid solution is N, N' -dimethylacetamide (DMAc), the solvent in the PMDA-ODA acid solution is formed by mixing N-methylpyrrolidone (NMP) and xylene (xylene) according to a volume ratio of 4 to 1, and the solvent in the BPDA-ODA acid solution is N-methylpyrrolidone (NMP); dripping 200-400 microlitres of polyimide precursor solution into each 2-4 square centimeter of substrate;
(3) Dropwise adding the P3HT precursor solution onto the gate insulating layer in the step (2), spin-coating for 20-40 seconds at a speed of 1000-2000 revolutions per minute by using a spin coater, then placing the substrate on a heating plate, and heating for 5-20 minutes at 50-100 ℃ to obtain a hole transport layer;
wherein, the P3HT precursor solution is obtained by adding chlorobenzene solvent into poly 3 hexyl thiophene (P3 HT) and then stirring, and the concentration is 5-10 milligrams per milliliter; dripping 60-100 microlitres of P3HT precursor solution into each 2-4 square cm of gate insulating layer;
(4) Obtaining left and right source-drain electrodes on the surface of a semiconductor through a thermal evaporation technology, removing the gate insulating layer and the semiconductor layer which cover part of the area of the upper surface of the substrate, exposing part of the substrate as the gate electrode, and finally obtaining a complete synaptic transistor device based on the polyimide novel gate insulating layer;
wherein the thermal evaporation parameter is that the temperature is controlled to be 40-50 ℃ and the vacuum degree is 10 -3 -10 -4 The deposition rate is 0.8-1 angstrom/second, and the evaporation time is 30-40 minutes.
The invention has the substantial characteristics that:
in the prior art, a pure polyimide gate insulating layer contains only a single ion: protons. Such a gate insulating layer has a small specific capacitance and is liable to cause a leakage phenomenon; in the invention, PMDA-ODA polyimide doped with ionic liquid [ EMIM ] [ TFSI ] is used as a gate insulating layer, and a certain amount of ionic liquid [ EMIM ] [ TFSI ] is doped into polyimide to form multiple ions in the polyimide, so that the specific capacitance of the gate insulating layer is improved, the range of working voltage intervals is enlarged, and the electrical performance of a device is improved. The novel gate dielectric layer with the multiple ion conductor films is prepared, has larger specific capacitance and smaller leakage current, and is uniform, compact and uniform in whole. The three-terminal (namely, three ports of the grid, the source and the drain of the thin film transistor) synaptic transistor based on P3HT prepared on the basis adopts a bottom grid top contact structure, and good interface contact can be formed between the grid insulating layer and the P3HT semiconductor.
The beneficial effects of the invention are as follows:
traditional three-terminal synaptic transistor based on ion glue type gate insulating layer adopts device structure of top gate top contact, gate insulating layer adopts laminating mode to contact with semiconductor layer, laminating degree is poor, and gap is formed between the two easily. And the dielectric constant of the ion gel type gate insulating layer is smaller, so that the leakage phenomenon is easy to occur under the stimulation of large voltage. According to the invention, the ionic liquid [ EMIM ] [ TFSI ] and the PMDA-ODA amic acid solution are mixed, and a spin coating process is utilized to prepare the novel gate dielectric layer with the multiple ion conductor films, so that the novel gate dielectric layer has larger specific capacitance and smaller leakage current. The whole gate insulating layer is average, compact and uniform, and the synaptic transistor device with the bottom gate top contact structure prepared on the basis has the advantages of high sensitivity, low power consumption, large working voltage range and the like.
As shown in fig. 3, the specific capacitance per unit area of the novel gate insulating layer can exceed 7 microfarads per square centimeter at a frequency of 1000 hertz; the working voltage can reach-50V (shown in figure 4); the minimum energy consumption is lower than 1 femtojoule (shown in fig. 5).
Drawings
Fig. 1 is a schematic diagram of a structure of a synaptic transistor device based on a polyimide-based novel gate insulating layer;
fig. 2 is a scanning electron microscope image of the novel gate insulating layer of polyimide obtained in example 1.
Fig. 3 is a voltage-capacitance graph of the polyimide novel gate insulating layer obtained in example 1.
Fig. 4 is a transfer graph of the novel polyimide-based gate insulating layer-based synaptic transistor device obtained in example 1.
Fig. 5 is a current response at-0.1V to-1V voltage of the novel polyimide-based gate insulating layer-based synaptic transistor device obtained in example 1.
The specific embodiment is as follows:
the present invention will now be described in detail with reference to the following examples, which are intended to aid persons of ordinary skill in the art in studying and thinking the same, but are not intended to limit the same in any way.
The BPEDA-ODA polyimide, PMDA-ODA polyimide and BPDA-ODA polyimide materials related by the invention are all known materials. Specifically, the polyimide is poly (biphenyl dianhydride-co-4, 4' -diaminodiphenyl ether) (BPEDA-ODA) polyimide, poly (pyromellitic dianhydride-co-4, 4' -diaminodiphenyl ether) (PMDA-ODA) polyimide and poly (biphenyl tetracarboxylic dianhydride-co-4, 4' -diaminodiphenyl ether) (BPDA-ODA) polyimide.
The ionic liquid [ EMIM ] [ TFSI ] is specifically 1-ethyl-3-methylimidazoline bis (trifluoromethyl sulfonyl) imine.
Example 1:
a preparation method of a synaptic transistor device based on a novel polyimide gate insulating layer comprises the following steps:
(1) Ultrasonically cleaning a conductive glass substrate with the size of 2 multiplied by 2 cm and the thickness of 2 mm by deionized water, acetone and isopropanol in sequence, drying the surface of the substrate by nitrogen, and putting the substrate into an ultraviolet cleaner for processing for 15 minutes;
(2) Mixing and uniformly stirring an ionic liquid [ EMIM ] [ TFSI ] and a PMDA-ODA polyamic acid solution with the mass fraction of 12% (the solvent of the solution is formed by mixing N-methylpyrrolidone (NMP) and xylene (xylene) according to the volume ratio of 4 to 1) according to the mass ratio of 1 to 20, so as to obtain a light yellow and clear mixed solution of PMDA-ODA polyimide and the ionic liquid [ EMIM ] [ TFSI ].
(3) In a glove box, 200 microliters of the mixed solution of PMDA-ODA type polyimide and ionic liquid [ EMIM ] [ TFSI ] in the step (2) was dropped on the substrate of the step (1) of 4 square centimeters, then spin-coated at a speed of 1500 revolutions per minute for 30 seconds by using a spin coater, and then the substrate was placed on a heating plate and heated at 150 degrees for 30 minutes to obtain a gate insulating layer of 5 micrometers thickness.
(4) Chlorobenzene solvent was added to P3HT and then stirred well to obtain a P3HT precursor solution at a concentration of 5 mg P3HT per ml chlorobenzene.
(5) And (3) dripping 100 microliters of the P3HT precursor solution obtained in the step (4) onto the gate insulating layer in the step (3), spin-coating for 30 seconds at a speed of 1500 revolutions per minute by using a spin coater, placing the substrate on a heating plate, and heating for 10 minutes at 60 ℃ to obtain a high-quality hole transport layer with a thickness of 50 nanometers.
(6) Covering the upper surface of the semiconductor layer obtained in the step (5) with a mask (the area of the left and right grooves of the mask is 1.5 mm 1 mm, the total area of the mask is 5*5 mm, and the distance between the two grooves is 100 μm), and performing thermal evaporation (the temperature of the chamber is controlled at 40-50 ℃ and the vacuum degree is 4 x 10) -4 -5*10 -4 Pa, deposition rate of 1 angstrom/second, vapor deposition time of 30 min), depositing gold electrode with thickness of 100 nm and spacing of about 150 μm on the film surface of the groove part, removing gate insulating layer and semiconductor layer in the partial region of the upper surface of the substrate by blade, removing rectangle with the size of 1 x 1 cm in the region of the lower left corner edge of the upper surface of the substrateThe exposed region serves as a gate electrode, thereby obtaining a complete synaptic transistor device based on a novel gate insulating layer of polyimide.
Performance testing and experimental result analysis:
the electrical performance test and analysis of the two-terminal artificial synapse in (6) was performed using a semiconductor analyzer Keithley 4200A-SCS and gave the following important results (test environment in nitrogen-closed glove box, nitrogen purity greater than 99%, ambient temperature 20-25 ℃):
the synaptic transistor device based on the polyimide novel gate insulating layer in example 1 has good electrical properties and ultra-low power consumption. As shown in fig. 2, the novel polyimide gate insulating layer prepared by the spin coating process shows a uniform and flat surface morphology in SEM pictures of 30 ten thousand times, and can form good interface contact with the P3HT semiconductor layer. The unit specific capacitance exceeds 7 microfarads per square centimeter at a frequency of 1000 hertz (shown in fig. 3); the operating voltage of the bottom-gate top-contact three-terminal synaptic transistor prepared by the novel gate insulating layer can be widened to-50V, which is far higher than that of the traditional ionic gum type synaptic transistor (shown in figure 4); the minimum power consumption of the synaptic transistor based on the polyimide novel gate insulating layer is only 0.84 femtojoule, and the minimum power consumption reaches the biological level.
Example 2:
a preparation method of a synaptic transistor device based on a novel polyimide gate insulating layer comprises the following steps:
(1) Ultrasonically cleaning a conductive glass substrate with the size of 2 multiplied by 2 cm and the thickness of 2 mm by deionized water, acetone and isopropanol in sequence, drying the surface of the substrate by nitrogen, and putting the substrate into an ultraviolet cleaner for processing for 15 minutes;
(2) Mixing and uniformly stirring an ionic liquid [ EMIM ] [ TFSI ] and a PMDA-ODA polyamic acid solution with the mass fraction of 12% (the solvent of the solution is formed by mixing N-methylpyrrolidone (NMP) and xylene (xylene) according to the volume ratio of 4 to 1) according to the mass ratio of 1 to 10, so as to obtain a light yellow and clear mixed solution of PMDA-ODA polyimide and the ionic liquid [ EMIM ] [ TFSI ].
(3) In a glove box, 350 microliters of the mixed solution of PMDA-ODA type polyimide and ionic liquid [ EMIM ] [ TFSI ] in step (2) was dropped on a substrate of step (1) of 4 square centimeters, then spin-coated at a speed of 1000 revolutions per minute for 30 seconds using a spin coater, and then the substrate was placed on a heating plate and heated at 150 degrees for 20 minutes to obtain a gate insulating layer of 10 micrometers thickness.
(4) Chlorobenzene solvent was added to P3HT and then stirred well to obtain a P3HT precursor solution at a concentration of 5 mg P3HT per ml chlorobenzene.
(5) And (3) dripping 70 microliters of the P3HT precursor solution obtained in the step (4) onto the gate insulating layer in the step (3), spin-coating for 30 seconds at a speed of 1000 revolutions per minute by using a spin coater, placing the substrate on a heating plate, and heating for 10 minutes at 60 ℃ to obtain the high-quality hole transport layer with the thickness of 70 nanometers.
(6) Covering the upper surface of the semiconductor layer obtained in the step (5) with a mask (the area of the left and right grooves of the mask is 1.5 mm 1 mm, the total area of the mask is 5*5 mm, and the distance between the two grooves is 100 μm), and performing thermal evaporation (the temperature of the chamber is controlled at 40-50 ℃ and the vacuum degree is 4 x 10) -4 -5*10 -4 The deposition rate is 1 angstrom/second, the vapor deposition time is 30 minutes), gold electrodes with the thickness of 80 nanometers and the spacing of about 100 micrometers are deposited on the film surface of the groove part, a blade is utilized to remove the gate insulating layer and the semiconductor layer of the partial area of the upper surface of the substrate, the removed area is a rectangle with the size of 1 multiplied by 1 cm, the position is at the left lower corner edge of the upper surface of the substrate, and the exposed area is used as the gate electrode, so that a complete synaptic transistor device based on the polyimide novel gate insulating layer is obtained.
Example 3:
the other steps are the same as in example 1 except that the polyamic acid solution in step (2) is replaced with a BPDA-ODA polyamic acid solution in which the solvent is N-methylpyrrolidone (NMP).
The above embodiments and test results are intended to provide a research basis for researchers in the relevant arts. Any other simple experimental condition changes, including modification, simplification, replacement, etc., without any substantial research changes are to be considered as being within the scope of the present invention.
The invention is not a matter of the known technology.
Claims (6)
1. The utility model provides a synaptic transistor device based on novel gate insulation layer of polyimide which characterized in that the synaptic transistor device structure includes: a part of gate insulating layer is distributed on the substrate, and a semiconductor layer and a metal layer are sequentially arranged on the gate insulating layer;
the gate insulating layer is made of polyimide material doped with ionic liquid, and the mass of the ionic liquid is 5-20% of that of the gate insulating layer; the semiconductor layer is a thiophene polymer;
the area of the gate insulating layer is 70-90% of the area of the substrate.
2. The novel polyimide-based gate insulating layer-based synaptic transistor device as claimed in claim 1, wherein the gate insulating layer has a thickness of 2-20 μm;
the thickness of the semiconductor layer is 30-100 nanometers;
the metal layer is a left metal electrode and a right metal electrode on the surface of the semiconductor layer, and the metal layer is made of gold;
the horizontal distance between the left metal electrode and the right metal electrode is 100-150 micrometers, and the thickness is 80-100 nanometers.
3. The novel gate insulating layer-based synaptic transistor device of claim 1, wherein the polyimide-based material comprises, but is not limited to, one of a BPEDA-ODA type polyimide, a PMDA-ODA type polyimide or a BPDA-ODA type polyimide;
the ionic liquid comprises but is not limited to one of 1-ethyl-3-methylimidazoline bis (trifluoromethylsulfonyl) imine ([ EMIM ] [ TFSI ]), 1-ethyl-3-methylimidazole tetrafluoroborate ([ EMIM ] BF 4) and 1-ethyl-3-methylimidazole hexafluorophosphate ([ EMIM ] PF 6);
the semiconductor layer is polythiophene, poly 3-hexyl thiophene or poly 3-bromohexyl thiophene.
4. The novel gate insulating layer-based synaptic transistor device of claim 1, wherein the substrate is quartz glass, silicon wafer or indium tin oxide conductive glass.
5. The method for manufacturing a synaptic transistor device based on a novel gate insulating layer of polyimide as claimed in claim 1, comprising the steps of:
(1) Sequentially ultrasonically cleaning a substrate by deionized water, acetone and isopropanol, drying the surface of the substrate by nitrogen, and putting the substrate into an ultraviolet cleaning machine for 15-20 minutes;
(2) Dropwise adding the polyimide precursor solution onto the substrate in the step (1) in a glove box, spin-coating for 20-40 seconds at a speed of 500-2000 revolutions per minute by using a spin coater, placing the substrate on a heating plate, and heating for 20-40 minutes at 150-250 ℃ to obtain a gate insulating layer;
wherein the polyimide precursor solution is prepared from ionic liquid and 10-20% by mass of polyamic acid solution; mixing according to the mass ratio of 1 to 10-20;
(3) Dropwise adding the P3HT precursor solution onto the gate insulating layer in the step (2), spin-coating for 20-40 seconds at a speed of 1000-2000 revolutions per minute by using a spin coater, and then placing the substrate on a heating plate and heating for 5-20 minutes at 50-100 ℃ to obtain a semiconductor layer;
wherein, the P3HT precursor solution is obtained by adding chlorobenzene solvent into poly 3 hexyl thiophene (P3 HT) and then stirring, and the concentration is 5-10 milligrams per milliliter; dripping 60-100 microlitres of P3HT precursor solution into each 2-4 square cm of gate insulating layer;
(4) Obtaining left and right source-drain electrodes on the surface of a semiconductor through a thermal evaporation technology, removing the gate insulating layer and the semiconductor layer which cover part of the area of the upper surface of the substrate, exposing part of the substrate as the gate electrode, and finally obtaining a complete synaptic transistor device based on the polyimide novel gate insulating layer;
wherein the thermal evaporation parameter is that the temperature is controlled to be 40-50 ℃ and the vacuum degree is 10 -3 -10 -4 The deposition rate is 0.8-1 angstrom/second, and the evaporation time is 30-40 minutes.
6. The method for manufacturing a novel gate insulating layer-based synaptic transistor device according to claim 5, wherein the polyamic acid solution is specifically a poly (biphenyl di-ether dianhydride-co-4, 4' -diaminodiphenyl ether) polyamic acid solution, a poly (pyromellitic dianhydride-co-4, 4' -diaminodiphenyl ether) polyamic acid solution, or a poly (biphenyl tetracarboxylic dianhydride-co-4, 4' -diaminodiphenyl ether) polyamic acid solution;
wherein the solvent in the poly (biphenyl dianhydride-co-4, 4 '-diaminodiphenyl ether) acid solution is N, N' -dimethylacetamide (DMAc), the solvent in the poly (pyromellitic dianhydride-co-4, 4 '-diaminodiphenyl ether) acid solution is mixed by N-methylpyrrolidone (NMP) and xylene (xylene) according to the volume ratio of 4 to 1, and the solvent in the poly (biphenyl tetracarboxylic dianhydride-co-4, 4' -diaminodiphenyl ether) acid solution is N-methylpyrrolidone (NMP); 200-400 microliters of polyimide precursor solution is added dropwise to every 2-4 square centimeters of substrate.
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| CN104882541A (en) * | 2015-05-28 | 2015-09-02 | 福州大学 | Metal quantum dot/organic semiconductor composite conductive channel film transistor preparation method |
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