CN113644178A - GaAs substrate mini-LED chip and manufacturing method thereof - Google Patents
GaAs substrate mini-LED chip and manufacturing method thereof Download PDFInfo
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- H01L33/10—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
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Abstract
The invention relates to the technical field of semiconductor LEDs, in particular to a GaAs substrate mini-LED chip and a manufacturing method thereof. The chip comprises an insulating layer, a GaAs substrate layer, an N-type semiconductor layer, a quantum well layer and a P-type semiconductor layer which are sequentially arranged from bottom to top; an N electrode and a P electrode are arranged on the surface of one side, away from the GaAs substrate layer, of the insulating layer; and a through hole penetrating through the insulating layer, the GaAs substrate layer, the N-type semiconductor layer and the quantum well layer is formed in the surface of one side, away from the GaAs substrate layer, of the insulating layer, and a metal material is filled in the through hole to enable the P electrode to be electrically connected with the P-type semiconductor layer. Because the epitaxial wafer is not required to be bonded with other substrates and then the GaAs substrate is not required to be removed in the process of manufacturing the mini-LED, the chip manufacturing flow is greatly simplified, the product yield is improved, and the production cost is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor LEDs, in particular to a GaAs substrate mini-LED chip and a manufacturing method thereof.
Background
The Mini LED is also a Mini LED. Compared with the common LED display screen, the Mini LED display screen has higher unit area density and smaller unit size of a light source, thereby bringing higher brightness and controllable color gamut. The mini LED chip structure is that a P electrode and an N electrode are arranged on the same side of an epitaxial layer, so that downstream manufacturers can directly package the mini LED chip, and a light emitting surface is usually arranged on one side of a substrate. When the AlGaInP red LED grows in an epitaxial mode, GaAs is generally used as a growth substrate, the GaAs substrate is used as a light emitting surface and can absorb a large amount of light emitted by an active layer, a common processing method when the mini LED is manufactured is to bond an epitaxial wafer and a sapphire substrate which does not absorb light, then the GaAs growth substrate is removed by chemical solution corrosion, and the sapphire substrate is used for replacing the GaAs substrate to serve as the light emitting surface. Although the processing method can enable the light emitted by the active region to successfully emit to the outside of the chip, the bonding of the new substrate and the removal process of the original substrate are complicated, the manufacturing process of the chip is prolonged, the production cost of the chip is increased, the epitaxial layer is lost in the bonding and GaAs substrate removal processes of the sapphire substrate, and the yield of the chip is greatly influenced.
Disclosure of Invention
Based on the design, the mini-LED chip is redesigned, the GaAs substrate and the epitaxial layer are dug, the P electrode and the N electrode are arranged on one side of the back face of the GaAs substrate at the same time, and the light emergent face is arranged on the side away from the substrate, so that light can be emitted to the outside of the chip without substrate replacement. Because the epitaxial wafer is not required to be bonded with other substrates and then the GaAs substrate is not required to be removed in the process of manufacturing the mini-LED, the chip manufacturing flow is greatly simplified, the product yield is improved, and the production cost is reduced.
In order to solve the technical problem, the first aspect of the invention provides a GaAs substrate mini-LED chip, which comprises an insulating layer, a GaAs substrate layer, an N-type semiconductor layer, a quantum well layer and a P-type semiconductor layer which are sequentially arranged from bottom to top;
an N electrode and a P electrode are arranged on the surface of one side, away from the GaAs substrate layer, of the insulating layer;
a through hole penetrating through the insulating layer, the GaAs substrate layer, the N-type semiconductor layer and the quantum well layer is formed in the surface of one side, away from the GaAs substrate layer, of the insulating layer, and a metal material is filled in the through hole to enable the P electrode to be electrically connected with the P-type semiconductor layer;
removing the insulating material at the contact position of the N electrode and the insulating layer to enable the N electrode to be electrically connected with the GaAs substrate layer;
and the mini-LED chip emits light at the side deviating from the GaAs substrate layer.
In a further technical scheme of the invention, an N-DBR layer is also arranged between the GaAs substrate layer and the N-type semiconductor layer;
and through holes penetrating through the insulating layer, the GaAs substrate layer, the N-DBR layer, the N-type semiconductor layer and the quantum well layer are formed in the surface of one side, away from the GaAs substrate layer, of the insulating layer, and metal materials are filled in the through holes to enable the P electrode to be electrically connected with the P-type semiconductor layer.
In a further technical scheme of the invention, a GaP coarsening layer is further arranged on the surface of one side of the P-type semiconductor layer, which is far away from the GaAs substrate layer, and the surface of one side of the GaP coarsening layer, which is far away from the GaAs substrate layer, is a rough surface.
In a further technical scheme of the invention, the thickness of the GaP coarsening layer is 2-3 μm, and the coarsening depth of the GaP coarsening layer is 0.5-1.5 μm.
In a further technical scheme of the invention, the N-DBR layer is formed by alternately growing 15-30 pairs of AlAs/AlGaAl, and the total thickness is 1.5-2.5 μm.
In a further technical scheme of the invention, the quantum well layer is composed of undoped AlGaInP and has the thickness of 250-350 nm.
In a further technical scheme of the invention, the insulating layer is made of a material with the thickness of 1.5-2.5 mu mSiO2And (4) forming.
A manufacturing method of a GaAs substrate mini-LED chip comprises the following steps:
s1, providing a GaAs substrate, and epitaxially growing an N-DBR layer, an N-type semiconductor layer, a quantum well layer, a P-type semiconductor layer and a GaP layer in sequence;
s2, roughening the surface of the GaP layer by using an iodic acid solution to obtain a GaP roughened layer;
s3, evaporating SiO on the surface of the side of the epitaxial layer, which is far away from the GaAs substrate2Then, thinning the thickness of the GaAs substrate to obtain a GaAs substrate layer;
s4, manufacturing a mask pattern on the back of the substrate, and etching the substrate into holes by using a chemical solution;
s5, continuously etching the epitaxial layer along the holes of the substrate through ICP until the P-type semiconductor layer is exposed, and stopping obtaining through holes;
s6, removing the mask pattern on the back of the substrate and the SiO on the surface of the epitaxial layer2；
S7, depositing SiO on the back of the substrate2Insulating layer, via hole also made of SiO2Filling;
s8, making a mask pattern on the surface of the insulating layer, and etching off SiO below the N electrode and in the hole2SiO remains on the side wall of the hole2；
S9, simultaneously evaporating and plating metal materials required by manufacturing the P electrode and the N electrode to manufacture the P electrode and the N electrode;
and S10, dividing the epitaxial wafer into mini-LED chips.
In a further technical scheme of the invention, the thickness of the GaAs substrate layer of S1 is 300-400 μm; the thickness of the GaAs substrate layer after thinning in the S3 is 110-210 mu m.
In a further technical scheme of the invention, the diameter of the through hole is 20-30 μm.
Compared with the prior art, the invention has the following beneficial effects: the mini-LED chip is redesigned, holes are dug in the GaAs substrate and the epitaxial layer, the P electrode and the N electrode are arranged on one side of the back face of the GaAs substrate, the light emitting face is arranged on the side away from the substrate, the N-DBR layer and the GaP coarsening layer are arranged to increase light emitting, and light can be emitted to the outside of the chip without substrate replacement. Because the epitaxial wafer is not required to be bonded with other substrates and then the GaAs substrate is not required to be removed in the process of manufacturing the mini-LED, the chip manufacturing flow is greatly simplified, the yield in the preparation process is improved from 75.81% to 84.32%, the product yield is obviously improved, the performance of the obtained mini-LED chip is equivalent to that of the existing process, and the production cost is reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a schematic structural diagram of a GaAs substrate mini-LED chip provided in an embodiment of the present application;
FIG. 2 is a schematic structural diagram of another GaAs substrate mini-LED chip provided in the embodiments of the present application;
reference numerals: GaAs substrate layer 1, N-DBR layer 2, N-type semiconductor layer 3, quantum well layer 4, P-type semiconductor layer 5, GaP coarsening layer 6, insulating layer 7, P electrode 8, N electrode 9 and through hole 10.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the application, its application, or uses. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present application unless specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description. Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
In the description of the present application, it should be understood that the terms "first", "second", etc. are used to define the components, and are used only for the convenience of distinguishing the corresponding components, and if not otherwise stated, the terms have no special meaning, and thus, should not be construed as limiting the scope of the present application.
In the description of the present application, it is to be understood that the orientation or positional relationship indicated by the directional terms such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal" and "top, bottom", etc., are generally based on the orientation or positional relationship shown in the drawings, and are used for convenience of description and simplicity of description only, and in the case of not making a reverse description, these directional terms do not indicate and imply that the device or element being referred to must have a particular orientation or be constructed and operated in a particular orientation, and therefore, should not be considered as limiting the scope of the present application; the terms "inner and outer" refer to the inner and outer relative to the profile of the respective component itself.
A GaAs substrate mini-LED chip of the present application is described in detail below with reference to fig. 1-2, and fig. 1 is a schematic structural diagram of a GaAs substrate mini-LED chip according to an embodiment of the present invention; fig. 2 is a schematic structural diagram of another GaAs substrate mini-LED chip according to an embodiment of the present invention. According to the GaAs substrate mini-LED chip provided by the embodiment of the invention, the electrode assembly is arranged on one side of the substrate, and the light emergent surface is arranged on the side away from the substrate.
As shown in fig. 1, an embodiment of the present invention provides a GaAs substrate mini-LED chip, which includes an insulating layer 7, a GaAs substrate layer 1, an N-type semiconductor layer 3, a quantum well layer 4, and a P-type semiconductor layer 5, which are sequentially disposed from bottom to top; an N electrode 9 and a P electrode 8 are arranged on the surface of one side, away from the GaAs substrate layer 1, of the insulating layer 7; a through hole 10 penetrating through the insulating layer 7, the GaAs substrate layer 1, the N-type semiconductor layer 3 and the quantum well layer 4 is formed in the surface of the insulating layer 7 on the side far away from the GaAs substrate layer 1, and a metal material is filled in the through hole 10 to enable the P electrode 8 and the P-type semiconductor layer 5 to be electrically connected; the insulating material at the contact position of the N electrode 9 and the insulating layer 7 is removed, so that the N electrode 9 is electrically connected with the GaAs substrate layer 1; and the mini-LED chip emits light at the side departing from the GaAs substrate layer 1. In the design mode of the invention, the N electrode 9 and the P electrode 8 of the mini-LED chip can be arranged on one side of the GaAs substrate layer 1 through the design mode of the through hole 10, the GaAs substrate layer 1 does not need to be removed or replaced, the preparation steps of the mini-LED chip are greatly shortened, and the product yield is high.
In some embodiments of the present invention, as shown in fig. 2, an N-DBR layer 2 is further disposed between the GaAs substrate layer 1 and the N-type semiconductor layer 3; the surface of the insulating layer 7, which is far away from the GaAs substrate layer 1, is provided with a through hole 10 which penetrates through the insulating layer 7, the GaAs substrate layer 1, the N-DBR layer 2, the N-type semiconductor layer 3 and the quantum well layer 4, and the through hole 10 is filled with a metal material so that the P electrode 8 is electrically connected with the P-type semiconductor layer 5. The surface of the P-type semiconductor layer 5, which is far away from the GaAs substrate layer 1, is also provided with a GaP coarsening layer 6, and the surface of the GaP coarsening layer 6, which is far away from the GaAs substrate layer 1, is a rough surface.
In some embodiments of the present invention, the thickness of the GaP coarsening layer 6 is 2 to 3 μm, and the coarsening depth of the GaP coarsening layer 6 is 0.5 to 1.5 μm. The GaP coarsening layer 6 can effectively diffuse current, and meanwhile, the GaP surface is coarsened to form diffuse reflection at the interface, so that the light emergence is increased.
In some embodiments of the present invention, the N-DBR layer 2 is composed of 15 to 30 pairs of AlAs/AlGaAl alternately grown, and has a total thickness of 1.5 μm to 2.5 μm. The N-DBR layer 2 is disposed to reflect light emitted downward from the active region, thereby increasing light extraction efficiency.
In some embodiments of the invention, the quantum well layer 4 is comprised of undoped AlGaInP and has a thickness of 250nm to 350 nm.
In some embodiments of the invention, the insulating layer 7 is made of SiO with a thickness of 1.5 μm to 2.5 μm2And (4) forming.
In some preferred embodiments of the present invention, the method for manufacturing the GaAs substrate mini-LED chip comprises the following steps:
s1, providing a GaAs substrate, and epitaxially growing an N-DBR layer 2, an N-type semiconductor layer 3, a quantum well layer 4, a P-type semiconductor layer 5 and a GaP layer in sequence;
s2, roughening the surface of the GaP layer by using an iodic acid solution to obtain a GaP roughened layer 6;
s3, evaporating SiO on the surface of the side of the epitaxial layer, which is far away from the GaAs substrate2Then, thinning the thickness of the GaAs substrate to obtain a GaAs substrate layer 1;
s4, manufacturing a mask pattern on the back of the substrate, and etching the substrate into holes by using a chemical solution;
s5, continuously etching the epitaxial layer along the holes of the substrate through ICP until the P-type semiconductor layer 5 is exposed, and stopping obtaining the through hole 10;
s6, removing the mask pattern on the back of the substrate and the SiO on the surface of the epitaxial layer2；
S7, depositing SiO on the back of the substrate2The insulating layer 7 and the via 10 are also SiO2Filling;
s8, making a mask pattern on the surface of the insulating layer 7, and etching off SiO below the N electrode 9 and in the hole2SiO remains on the side wall of the hole2；
S9, simultaneously evaporating and plating metal materials required for manufacturing the P electrode 8 and the N electrode 9 to manufacture the P electrode 8 and the N electrode 9;
and S10, dividing the epitaxial wafer into mini-LED chips.
In some embodiments of the invention, the thickness of the GaAs substrate layer 1 of S1 is 300 μm-400 μm; the thickness of the GaAs substrate layer 1 after thinning in the S3 is 110-210 μm.
In some embodiments of the present invention, the diameter of the through-hole 10 is 20 μm to 30 μm.
Other embodiments of the invention provide a GaAs substrate mini-LED chip, and the preparation method comprises the following steps:
1) providing a GaAs substrate with the thickness of 350 mu m, putting the substrate into an MOCVD machine, introducing carrier gas required by epitaxial growth, and sequentially epitaxially growing an N-DBR layer 2, an N-type semiconductor layer 3, a quantum well layer 4, a P-type semiconductor layer 5 and a GaP layer; wherein, the N-DBR layer 2 is composed of AlGaAs/AlAs alternately, 23 pairs in total, and the total thickness is 2 μm; the quantum well layer 4 is made of undoped AlGaInP and has the thickness of 300 nm; the thickness of the GaP layer is 3 μm;
2) soaking the epitaxial wafer in an iodic acid solution for 2min, taking out the epitaxial wafer, flushing the epitaxial wafer, and spin-drying the epitaxial wafer to finish roughening the surface of the GaP layer to obtain a GaP roughened layer 6, wherein the roughening depth is about 1 mu m;
3) evaporating a layer of SiO on the surface of the epitaxial layer2Protecting the epitaxial layer, putting the epitaxial wafer into a grinding machine, and grinding the thickness of the GaAs substrate to 150 μm to obtain a GaAs substrate layer 1;
4) washing the ground epitaxial wafer, spin-coating a positive photoresist on the back of the substrate to prepare a mask pattern, and etching a hole in the substrate by using a mixed solution of ammonia water and hydrogen peroxide, wherein the diameter of the hole is 25 micrometers;
5) placing the epitaxial wafer into an ICP machine, sequentially etching the N-DBR layer 2, the N-type semiconductor layer 3 and the quantum well layer 4 along holes in the substrate through plasma, and exposing the P-type semiconductor layer 5 to obtain a through hole 10;
6) removing the mask pattern on the back surface of the substrate by using a photoresist solution, and removing SiO on the surface of the epitaxial layer by using an ammonium fluoride solution2；
7) Evaporating a layer of SiO with the thickness of 2 mu m on the back surface of the substrate2An insulating layer is formed, the entire back surface of the substrate and the through-hole 10 are SiO2Covering;
8) spin-coating a positive photoresist on the surface of the insulating layer 7 to prepare a mask pattern, wherein the photoresist protection is not provided right below the region where the N electrode 9 needs to be prepared, the photoresist protection is not provided right above the through hole 10, the exposed area is smaller than the area of the through hole 10, and removing the SiO of the part without the photoresist protection by using an ammonium fluoride solution2Because the photoresist is not protected right above the through hole 10 and the exposed area is smaller than the area of the through hole 10, SiO is remained on the side wall of the through hole 102；
9) Simultaneously, metal materials required for manufacturing the P electrode 8 and the N electrode 9 are evaporated, the N electrode 9 is directly contacted with the GaAs substrate layer 1, and the P electrode 8 is connected with the P type semiconductor layer 5 through a through hole 10 penetrating through the GaAs substrate layer 1, the N-DBR layer 2, the N type semiconductor layer 3 and the quantum well layer 4;
10) and cutting the epitaxial wafer into a mini-LED chip by an automatic cutting machine.
The yield of the mini-LED chip prepared by the preparation method is 84.32%, and the performance test of the obtained mini-LED chip shows that the working Voltage (VF) is 2.25V, the dominant Wavelength (WLD) is 621.5nm, and the chip brightness (LOP) is 390.6 mcd.
What is not described in this embodiment may be referred to in the relevant description of the rest of the application.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solutions of the present application and not to limit them; although the present application has been described in detail with reference to preferred embodiments, those of ordinary skill in the art will understand that: modifications to the embodiments of the present application or equivalent replacements of some technical features may still be made, which should all be covered by the scope of the technical solution claimed in the present application.
Claims (10)
1. A GaAs substrate mini-LED chip is characterized by comprising an insulating layer, a GaAs substrate layer, an N-type semiconductor layer, a quantum well layer and a P-type semiconductor layer which are sequentially arranged from bottom to top;
an N electrode and a P electrode are arranged on the surface of one side, away from the GaAs substrate layer, of the insulating layer;
a through hole penetrating through the insulating layer, the GaAs substrate layer, the N-type semiconductor layer and the quantum well layer is formed in the surface of one side, away from the GaAs substrate layer, of the insulating layer, and a metal material is filled in the through hole to enable the P electrode to be electrically connected with the P-type semiconductor layer;
removing the insulating material at the contact position of the N electrode and the insulating layer to enable the N electrode to be electrically connected with the GaAs substrate layer;
and the mini-LED chip emits light at the side deviating from the GaAs substrate layer.
2. The GaAs substrate mini-LED chip of claim 1, wherein an N-DBR layer is further disposed between the GaAs substrate layer and the N-type semiconductor layer;
and through holes penetrating through the insulating layer, the GaAs substrate layer, the N-DBR layer, the N-type semiconductor layer and the quantum well layer are formed in the surface of one side, away from the GaAs substrate layer, of the insulating layer, and metal materials are filled in the through holes to enable the P electrode to be electrically connected with the P-type semiconductor layer.
3. A GaAs substrate mini-LED chip according to claim 1 or 2, wherein the surface of the P-type semiconductor layer on the side away from the GaAs substrate layer is further provided with a GaP roughening layer, and the surface of the GaP roughening layer on the side away from the GaAs substrate layer is a roughened surface.
4. The GaAs substrate mini-LED chip of claim 3, wherein the thickness of the GaP coarsening layer is 2-3 μm, and the coarsening depth of the GaP coarsening layer is 0.5-1.5 μm.
5. The GaAs substrate mini-LED chip as claimed in claim 2, wherein the N-DBR layer is composed of 15-30 pairs of AlAs/AlGaAl alternately grown, and has a total thickness of 1.5 μm-2.5 μm.
6. The GaAs-substrate mini-LED chip of claim 1, wherein the quantum well layer is comprised of undoped AlGaInP with a thickness of 250nm to 350 nm.
7. The GaAs substrate mini-LED chip as claimed in claim 1, wherein said insulating layer is made of SiO with a thickness of 1.5 μm to 2.5 μm2And (4) forming.
8. A method for manufacturing a GaAs substrate mini-LED chip, which is characterized by comprising the following steps of:
s1, providing a GaAs substrate, and epitaxially growing an N-DBR layer, an N-type semiconductor layer, a quantum well layer, a P-type semiconductor layer and a GaP layer in sequence;
s2, roughening the surface of the GaP layer by using an iodic acid solution to obtain a GaP roughened layer;
s3, evaporating SiO on the surface of the side of the epitaxial layer, which is far away from the GaAs substrate2Then, thinning the thickness of the GaAs substrate to obtain a GaAs substrate layer;
s4, manufacturing a mask pattern on the back of the substrate, and etching the substrate into holes by using a chemical solution;
s5, continuously etching the epitaxial layer along the holes of the substrate through ICP until the P-type semiconductor layer is exposed, and stopping obtaining through holes;
s6, removing the mask pattern on the back of the substrate and the SiO on the surface of the epitaxial layer2；
S7, depositing SiO on the back of the substrate2Insulating layer, via hole also made of SiO2Filling;
s8, making a mask pattern on the surface of the insulating layer, and etching off SiO below the N electrode and in the hole2SiO remains on the side wall of the hole2；
S9, simultaneously evaporating and plating metal materials required by manufacturing the P electrode and the N electrode to manufacture the P electrode and the N electrode;
and S10, dividing the epitaxial wafer into mini-LED chips.
9. The method for manufacturing a GaAs substrate mini-LED chip as claimed in claim 8, wherein the thickness of the GaAs substrate layer of S1 is 300 μm-400 μm; the thickness of the GaAs substrate layer after thinning in the S3 is 110-210 mu m.
10. The method for manufacturing a GaAs substrate mini-LED chip as claimed in claim 8, wherein the diameter of the through hole is 20 μm to 30 μm.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111189547.7A CN113644178A (en) | 2021-10-13 | 2021-10-13 | GaAs substrate mini-LED chip and manufacturing method thereof |
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| CN202111189547.7A CN113644178A (en) | 2021-10-13 | 2021-10-13 | GaAs substrate mini-LED chip and manufacturing method thereof |
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| CN202111189547.7A Pending CN113644178A (en) | 2021-10-13 | 2021-10-13 | GaAs substrate mini-LED chip and manufacturing method thereof |
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Cited By (2)
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| CN114335268A (en) * | 2022-03-17 | 2022-04-12 | 南昌凯捷半导体科技有限公司 | Method for improving mini LED bonding yield |
| CN114975708A (en) * | 2022-08-02 | 2022-08-30 | 江西兆驰半导体有限公司 | Front-mounted red and yellow light LED chip and preparation method thereof |
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| CN109309152A (en) * | 2018-11-12 | 2019-02-05 | 扬州乾照光电有限公司 | A kind of quaternary crystal covering type LED structure and production method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114335268A (en) * | 2022-03-17 | 2022-04-12 | 南昌凯捷半导体科技有限公司 | Method for improving mini LED bonding yield |
| CN114975708A (en) * | 2022-08-02 | 2022-08-30 | 江西兆驰半导体有限公司 | Front-mounted red and yellow light LED chip and preparation method thereof |
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Application publication date: 20211112 |