CN113644132A - Double-gate DMOS device based on SOI wafer and manufacturing method thereof - Google Patents
Double-gate DMOS device based on SOI wafer and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000009792 diffusion process Methods 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 12
- 230000000694 effects Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
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- 239000004065 semiconductor Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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Abstract
The invention provides a double-gate DMOS device based on an SOI wafer and a manufacturing method thereof, wherein the device comprises a substrate, a buried oxide layer, a gate oxide layer and a gate oxide layer, wherein the buried oxide layer is positioned on the substrate; a P well on the buried oxide layer; the N-type diffusion region is positioned on one side of the P well; the first N-type heavily doped region and the second N-type heavily doped region are respectively positioned on two sides of the P well and the N-type diffusion region; the arrangement direction of the first N-type heavily doped region, the P well, the N-type diffusion region and the second N-type heavily doped region is transverse; the direction perpendicular to the transverse direction is a longitudinal direction; and the longitudinal two sides of the P trap are respectively provided with a first grid and a second grid. The invention utilizes the double-gate to control the channel, can increase the channel opening amplitude and reduce the opening voltage. By combining the advantages of the SOI wafer, the electric leakage between the device and the substrate can be reduced, and the performance of the device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a double-gate DMOS device based on an SOI wafer and a manufacturing method thereof.
Background
For a conventional DMOS (double diffused metal oxide semiconductor) structure, as shown in fig. 1, fig. 1 is a schematic longitudinal sectional view of a DMOS in the prior art. The structure comprises a P well (Pwell) positioned on a substrate, an N-type diffusion region (N drift) positioned on one side of the P well, N-type heavily doped regions (N +) respectively positioned on two sides of the P well and the N-type diffusion region, a gate oxide layer is further arranged on the upper surface of the substrate, and a gate structure is arranged on the upper surface of the gate oxide layer. In such a conventional DMOS structure, the gate structure has a weak capability of controlling the channel, and there is leakage between the device and the substrate.
Therefore, a new DMOS device and a method for manufacturing the same are needed to solve the above problems.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a DMOS device based on SOI wafer dual-gate and a method for manufacturing the same, which are used to solve the problems of the prior art that the DMOS structure has a weak gate-to-channel control capability and there is leakage between the device and the substrate.
To achieve the above and other related objects, the present invention provides a double-gate DMOS device based on SOI wafer, comprising:
the substrate is provided with a buried oxide layer; a P well on the buried oxide layer; the N-type diffusion region is positioned on one side of the P well; the first N-type heavily doped region and the second N-type heavily doped region are respectively positioned on two sides of the P well and the N-type diffusion region; the arrangement direction of the first N-type heavily doped region, the P well, the N-type diffusion region and the second N-type heavily doped region is transverse; the direction perpendicular to the transverse direction is a longitudinal direction; and the longitudinal two sides of the P trap are respectively provided with a first grid and a second grid.
Preferably, one side of the first and second gates is longitudinally aligned with one side of the P-well.
Preferably, the length of the first and second gates in the lateral direction is greater than the length of the P-well in the lateral direction.
Preferably, the width of the N-type diffusion region in the longitudinal direction is greater than the width of the P-well in the longitudinal direction.
Preferably, the first and second gates are made of polysilicon.
The invention also provides a manufacturing method of the double-gate DMOS device based on the SOI wafer, which at least comprises the following steps:
providing a substrate, and forming a buried oxide layer in a shallow region of the substrate;
forming a P well and an N-type diffusion region positioned on one lateral side of the P well on the buried oxide layer;
etching the substrate, and respectively forming grooves on two sides of the P type longitudinal direction;
forming a gate oxide layer covering the P well, the side wall and the bottom of the groove;
fifthly, forming a first grid and a second grid in the groove respectively;
and sixthly, etching the substrate, and forming a first N-type heavily doped region and a second N-type heavily doped region on two sides of the P well and the N-type diffusion region.
As described above, the SOI wafer dual-gate DMOS device and the method for manufacturing the same according to the present invention have the following advantageous effects: the invention utilizes the double-gate to control the channel, can increase the channel opening amplitude and reduce the opening voltage. By combining the advantages of the SOI wafer, the electric leakage between the device and the substrate can be reduced, and the performance of the device is improved.
Drawings
Fig. 1 is a schematic longitudinal cross-sectional view of a prior art DMOS;
fig. 2 is a schematic top view of a DMOS device of the present invention;
fig. 3 is a schematic diagram showing a lateral cross-sectional structure of a DMOS device of the present invention;
fig. 4 is a schematic diagram showing a vertical cross-sectional structure of a DMOS device of the present invention;
FIG. 5 is a schematic diagram showing a lateral cross-sectional structure of a buried oxide layer and P-well and N-type diffusion regions formed on a substrate according to the present invention;
FIG. 6 is a schematic cross-sectional view illustrating the formation of trenches on both sides of a P-type substrate;
FIG. 7 is a schematic diagram showing the vertical structure of the gate oxide layer formed on the sidewalls and bottom of the P well and the trench in the present invention;
FIG. 8 is a schematic diagram showing a longitudinal cross-sectional structure of a gate formed in a trench according to the present invention;
fig. 9 is a schematic diagram showing a lateral cross-sectional structure of forming P-well and N-type diffusion regions in the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 2 to fig. 9. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The invention provides a double-gate DMOS device based on SOI wafer, which at least comprises:
the substrate is provided with a buried oxide layer; a P well on the buried oxide layer; the N-type diffusion region is positioned on one side of the P well; the first N-type heavily doped region and the second N-type heavily doped region are respectively positioned on two sides of the P well and the N-type diffusion region; the arrangement direction of the first N-type heavily doped region, the P well, the N-type diffusion region and the second N-type heavily doped region is transverse; the direction perpendicular to the transverse direction is a longitudinal direction; and the longitudinal two sides of the P trap are respectively provided with a first grid and a second grid.
Fig. 2 is a schematic top view of a DMOS device of the present invention, as shown in fig. 2-4. Fig. 3 is a schematic diagram showing a lateral cross-sectional structure of the DMOS device of the present invention. Fig. 4 is a schematic diagram showing a vertical cross-sectional structure of the DMOS device of the present invention.
The double-gate DMOS device based on the SOI wafer comprises the following components: the buried oxide layer BOX structure comprises a substrate 01 and a buried oxide layer BOX positioned on the substrate 01; a P well (Pwell) located on the buried oxide layer BOX; an N-type diffusion region (N drift) located on one side of the P-well (Pwell); a first N-type heavily doped region (N +) and a second N-type heavily doped region (N +) respectively positioned at two sides of the P well (Pwell) and the N-type diffusion region (N drift); the arrangement direction of the first N-type heavily doped region (N +), the P well (Pwell), the N-type diffusion region (Ndrift) and the second N-type heavily doped region (N +) is the transverse direction (X direction); the direction perpendicular to the transverse direction is the longitudinal direction (Y direction); and a first gate (P1) and a second gate (P1) are respectively arranged on two sides of the P trap in the longitudinal direction (Y direction). Wherein the gate P1 above the P-well is the first gate, as shown in fig. 2; the gate P1 located under the P-well is the second gate. The first N-type heavily doped region (N +) is positioned on the left side of the P well; and the second N-type heavily doped region (N +) is positioned on the right side of the P well.
As shown in fig. 2, in the present embodiment, one side of the first and second gates is aligned with one side of the P-well in the longitudinal direction (Y direction).
Further, the length of the first and second gates in the lateral direction (X direction) of the present embodiment is greater than the length of the P-well in the lateral direction (X direction).
The width of the N-type diffusion region in the longitudinal direction (Y direction) is larger than the width of the P-well in the longitudinal direction (Y direction).
In the present invention, the first gate and the second gate are made of polysilicon.
The invention also provides a manufacturing method of the double-gate DMOS device based on the SOI wafer, which at least comprises the following steps:
providing a substrate, and forming a buried oxide layer in a shallow region of the substrate; as shown in fig. 5, fig. 5 is a schematic diagram showing a lateral cross-sectional structure of the present invention in which a buried oxide layer, a P-well, and an N-type diffusion region are formed on a substrate. In this step one, a buried oxide layer BOX is formed in a shallow region of the substrate 01.
Forming a P well and an N-type diffusion region positioned on one lateral side of the P well on the buried oxide layer; in the second step, a P well (Pwell) and an N-type diffusion region (N drift) located on one side of the P well (Pwell) in the transverse direction (X direction) are formed on the buried oxide layer BOX.
Further, in the present invention, in the second step of this embodiment, the width of the N-type diffusion region (N drift) in the longitudinal direction (Y direction) is greater than the width of the P-well (Pwell) in the longitudinal direction.
Etching the substrate, and respectively forming grooves on two sides of the P type longitudinal direction; as shown in fig. 6, fig. 6 is a schematic cross-sectional view illustrating a trench formed on each of two sides of the P-type substrate. As can be seen from fig. 6, two trenches are formed on both sides of the P-well in the longitudinal direction.
Forming a gate oxide layer covering the P well, the side wall and the bottom of the groove; as shown in fig. 7, fig. 7 is a schematic diagram showing a longitudinal structure of forming a gate oxide layer on the P-well and the trench sidewall and bottom in the present invention. And fourthly, forming a gate oxide layer 02 covering the P well, the side wall and the bottom of the groove.
Fifthly, forming a first grid and a second grid in the groove respectively; as shown in fig. 8, fig. 8 is a schematic diagram showing a longitudinal cross-sectional structure of a gate formed in a trench according to the present invention. In this step five, the first and second gates 03 are formed in the trenches, respectively.
Further, in step five of this embodiment, one side of the first and second gates is longitudinally aligned with one side of the P-well.
Further, in the present invention, in step five of this embodiment, the length of the first gate and the length of the second gate in the lateral direction are greater than the length of the P-well in the lateral direction.
In the present invention, in the fifth step, the first gate and the second gate are made of polysilicon.
And sixthly, etching the substrate, and forming a first N-type heavily doped region and a second N-type heavily doped region on two sides of the P well and the N-type diffusion region. As shown in fig. 9, fig. 9 is a schematic diagram showing a lateral cross-sectional structure of forming P-well and N-type diffusion regions in the present invention.
In summary, the present invention utilizes the dual-gate control of the channel to increase the channel turn-on amplitude and reduce the turn-on voltage. By combining the advantages of the SOI wafer, the electric leakage between the device and the substrate can be reduced, and the performance of the device is improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A double-gate DMOS device based on SOI wafer is characterized by at least comprising:
the substrate is provided with a buried oxide layer; a P well on the buried oxide layer; the N-type diffusion region is positioned on one side of the P well; the first N-type heavily doped region and the second N-type heavily doped region are respectively positioned on two sides of the P well and the N-type diffusion region; the arrangement direction of the first N-type heavily doped region, the P well, the N-type diffusion region and the second N-type heavily doped region is transverse; the direction perpendicular to the transverse direction is a longitudinal direction; and the longitudinal two sides of the P trap are respectively provided with a first grid and a second grid.
2. The SOI wafer-based dual-gate DMOS device of claim 1, wherein: one side of the first and second gates is longitudinally aligned with one side of the P well.
3. The SOI wafer-based dual-gate DMOS device of claim 1, wherein: the length of the first grid and the second grid in the transverse direction is larger than that of the P trap in the transverse direction.
4. The SOI wafer-based dual-gate DMOS device of claim 1, wherein: the width of the N-type diffusion region in the longitudinal direction is larger than that of the P-well in the longitudinal direction.
5. The SOI wafer-based dual-gate DMOS device of claim 1, wherein: the first grid and the second grid are made of polysilicon.
6. A method of fabricating an SOI wafer-based double-gate DMOS device according to any of claims 1 to 4, wherein the method comprises at least the following steps:
providing a substrate, and forming a buried oxide layer in a shallow region of the substrate;
forming a P well and an N-type diffusion region positioned on one lateral side of the P well on the buried oxide layer;
etching the substrate, and respectively forming grooves on two sides of the P type longitudinal direction;
forming a gate oxide layer covering the P well, the side wall and the bottom of the groove;
fifthly, forming a first grid and a second grid in the groove respectively;
and sixthly, etching the substrate, and forming a first N-type heavily doped region and a second N-type heavily doped region on two sides of the P well and the N-type diffusion region.
7. The method of manufacturing an SOI wafer-based double-gate DMOS device according to claim 5, wherein: and fifthly, one sides of the first and second gates are longitudinally aligned with one side of the P well.
8. The method of manufacturing an SOI wafer-based double gate DMOS device of claim 7 wherein: and in the fifth step, the length of the first gate and the second gate in the transverse direction is greater than that of the P well in the transverse direction.
9. The method of manufacturing an SOI wafer-based double-gate DMOS device according to claim 5, wherein: and the width of the N-type diffusion region in the longitudinal direction in the second step is larger than that of the P well in the longitudinal direction.
10. The method of manufacturing an SOI wafer-based double-gate DMOS device according to claim 5, wherein: and fifthly, the first grid electrode and the second grid electrode are made of polysilicon.
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| CN202110789825.6A CN113644132A (en) | 2021-07-13 | 2021-07-13 | Double-gate DMOS device based on SOI wafer and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1979893A (en) * | 2005-11-29 | 2007-06-13 | 旺宏电子股份有限公司 | Transverse double-diffusing metal dioxide semiconductor transistor and making method |
| CN102903748A (en) * | 2011-07-25 | 2013-01-30 | 中芯国际集成电路制造(上海)有限公司 | Lateral double-diffused metal oxide semiconductor (DMOS) and manufacturing method thereof |
| CN103594517A (en) * | 2013-10-24 | 2014-02-19 | 中国科学院上海微系统与信息技术研究所 | Multi-gate SOI-LDMOS device structure |
| CN103915506A (en) * | 2014-04-28 | 2014-07-09 | 重庆大学 | Double-gate LDMOS device with longitudinal NPN structure |
| CN104201204A (en) * | 2014-08-13 | 2014-12-10 | 四川广义微电子股份有限公司 | Transverse symmetrical DMOS (double diffusion metal-oxide-semiconductor) pipe and manufacture method thereof |
| US20170346477A1 (en) * | 2016-05-24 | 2017-11-30 | Maxim Integrated Products, Inc. | LDMOS Transistors And Associated Systems And Methods |
| CN110491945A (en) * | 2019-08-13 | 2019-11-22 | 上海华力集成电路制造有限公司 | Semiconductor devices and its manufacturing method |
-
2021
- 2021-07-13 CN CN202110789825.6A patent/CN113644132A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1979893A (en) * | 2005-11-29 | 2007-06-13 | 旺宏电子股份有限公司 | Transverse double-diffusing metal dioxide semiconductor transistor and making method |
| CN102903748A (en) * | 2011-07-25 | 2013-01-30 | 中芯国际集成电路制造(上海)有限公司 | Lateral double-diffused metal oxide semiconductor (DMOS) and manufacturing method thereof |
| CN103594517A (en) * | 2013-10-24 | 2014-02-19 | 中国科学院上海微系统与信息技术研究所 | Multi-gate SOI-LDMOS device structure |
| CN103915506A (en) * | 2014-04-28 | 2014-07-09 | 重庆大学 | Double-gate LDMOS device with longitudinal NPN structure |
| CN104201204A (en) * | 2014-08-13 | 2014-12-10 | 四川广义微电子股份有限公司 | Transverse symmetrical DMOS (double diffusion metal-oxide-semiconductor) pipe and manufacture method thereof |
| US20170346477A1 (en) * | 2016-05-24 | 2017-11-30 | Maxim Integrated Products, Inc. | LDMOS Transistors And Associated Systems And Methods |
| CN110491945A (en) * | 2019-08-13 | 2019-11-22 | 上海华力集成电路制造有限公司 | Semiconductor devices and its manufacturing method |
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