CN113644060B - Layout structure and method for regulating and controlling SRAM performance - Google Patents
Layout structure and method for regulating and controlling SRAM performance Download PDFInfo
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- CN113644060B CN113644060B CN202110819631.6A CN202110819631A CN113644060B CN 113644060 B CN113644060 B CN 113644060B CN 202110819631 A CN202110819631 A CN 202110819631A CN 113644060 B CN113644060 B CN 113644060B
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- 238000000034 method Methods 0.000 title claims abstract description 30
- 230000001105 regulatory effect Effects 0.000 title claims abstract description 26
- 230000001276 controlling effect Effects 0.000 title claims abstract description 20
- 230000005540 biological transmission Effects 0.000 claims abstract description 57
- 238000005520 cutting process Methods 0.000 claims abstract description 38
- 230000008569 process Effects 0.000 claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 claims abstract description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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Abstract
The invention provides a layout structure and a method for regulating and controlling SRAM performance, and provides the layout structure, wherein the longitudinal distance between a grid cutting pattern and an active region pattern of an N-type transmission tube is 10-40 nm; adjusting the longitudinal distance between the grid cutting pattern and the active region pattern of the N-type transmission tube to obtain a plurality of layout structures with different longitudinal distances; performing a CMOS process by using the obtained multiple layout structures with different longitudinal distances to finish device manufacturing and obtain multiple test devices; and respectively carrying out WAT test by using a plurality of test devices, and extracting the threshold voltage and saturation current parameters of the NPG of the transmission tube. The invention adjusts the performance of the MOSFET device by adjusting the distance between the gate cutting and the active region through the layout, changes the proportion relation among the transistors, and further achieves the purpose of controlling the performance of the SRAM. The invention can independently regulate and control the device performance including threshold voltage, saturation current and the like on the basis of not changing the process flow, thereby controlling the performance of the SRAM, and being simple and easy to implement.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a layout structure and a layout method for regulating and controlling SRAM performance.
Background
With the continued development of semiconductor technology, the improvement in integrated circuit performance has been achieved mainly by shrinking the device size to increase its speed. Currently, the fabrication of semiconductor devices is limited by various physical limitations as nanotechnology process nodes have been stepped into.
The performance of the SRAM is controlled by adjusting the proportional relation among MOSFETs, specifically, threshold voltage ion implantation, active area width (AA width), gate polysilicon length (Poly length), and the like. However, after threshold voltage ion implantation, a higher thermal budget, such as spike anneal (spike implant), will cause many of the dopants after threshold voltage ion implantation to be lost into the STI or out-diffused, which will reduce the sensitivity of the threshold voltage dopant, so to reach the target value of the threshold voltage VT, more dopant needs to be implanted, which will cause lattice damage and reduced carrier mobility, which in turn affects device performance; and ion implantation does not allow individual regulation of the MOSFETs in the SRAM, especially the N-pass transistor NPG and the N-pull-down transistor NPD in the SRAM.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a layout structure and method for regulating performance of an SRAM, so as to solve the problem of poor performance of the SRAM in the prior art.
To achieve the above and other related objects, the present invention provides a layout structure for regulating performance of an SRAM, including at least: active region patterns of a plurality of N-type transmission pipes longitudinally arranged at intervals; the length direction of the active region graph of the N-type transmission tube is transverse;
a plurality of gate patterns arranged at intervals in a lateral direction; the length direction of the plurality of gate patterns is along the longitudinal direction; the grid patterns are spanned on the active region patterns of the N-type transmission tubes;
a gate cut pattern located between the active region patterns of the N-type transmission tube; the grid electrode cutting patterns cross over two adjacent grid electrode patterns; the length direction of the grid electrode cutting pattern is along the transverse direction;
the longitudinal distance between the grid electrode cutting pattern and the active region pattern of the N-type transmission tube is 10-40 nm.
Preferably, the layout structure further comprises a pull-up tube active region, and the grid electrode is located between the pull-up tube active regions.
The invention also provides a method for regulating and controlling the performance of the SRAM by utilizing the layout structure, which at least comprises the following steps:
step one, providing the layout structure; adjusting the longitudinal distance between the grid cutting pattern and the active region pattern of the N-type transmission tube to obtain a plurality of layout structures with different longitudinal distances;
performing a CMOS process by using the obtained layout structures with different longitudinal distances to finish device manufacturing and obtain a plurality of test devices;
and thirdly, respectively performing WAT test by using the plurality of test devices, and extracting the threshold voltage and the saturation current parameters of the NPG of the transmission tube.
Preferably, in the first step, the longitudinal distance between the gate cutting pattern and the active region pattern of the N-type transmission tube is adjusted by changing the position of the cutting pattern between the active region patterns of the N-type transmission tube in the layout structure.
Preferably, in the first step, the longitudinal distance between the gate cutting pattern and the active region pattern of the N-type transmission tube is adjusted by changing the size of the cutting pattern in the layout structure.
Preferably, the test device in the second step includes an SRAM structure, where the SRAM structure includes at least a pull-up tube, a pull-down tube, an N-type transmission tube, and NMOS and PMOS.
Preferably, the third step further comprises extracting electrical parameters of the SRAM.
Preferably, the method further includes a fourth step of drawing threshold voltages of the transmission tube NPG corresponding to different longitudinal distances and saturation currents of the transmission tube NPG corresponding to different longitudinal distances, and selecting an optimal longitudinal distance between the gate cutting pattern and the active region pattern of the N-type transmission tube.
As described above, the layout structure and method for regulating and controlling SRAM performance of the invention have the following beneficial effects: the invention relates to a method for regulating and controlling the performance of a deep submicron CMOS integrated circuit MOSFET and an SRAM, which aims at regulating and controlling the performance of MOSFET devices by regulating and controlling the distance between gate cutting and an active interval through a layout, changing the proportional relation among transistors and further achieving the purpose of controlling the performance of the SRAM. Silicon oxide, silicon nitride and the like filling the groove after the gate line tail etching process can exert stress on the groove, and influence the performance threshold voltage of the MOSFET device; the stress applied to the channel is adjusted by changing the distance between the gate cutting and the active region, so that the device performance is changed to different degrees. The invention can independently regulate and control the device performance including threshold voltage, saturation current and the like on the basis of not changing the process flow, thereby controlling the performance of the SRAM, and being simple and easy to implement.
Drawings
FIG. 1 is a schematic diagram of an SRAM structure according to the present invention;
FIG. 2 is a schematic diagram of layout structure for regulating SRAM performance according to the present invention;
FIG. 3 is a graph showing the variation of the threshold voltage of NPG according to the longitudinal distance between the gate cut pattern and the active region pattern of the N-type transmission tube according to the present invention;
fig. 4 is a graph showing the variation of the saturation current of the NPG according to the longitudinal distance between the gate cut pattern and the active region pattern of the N-type transmission tube according to the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 4. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The invention provides a layout structure for regulating and controlling SRAM performance, which at least comprises:
active region patterns of a plurality of N-type transmission pipes longitudinally arranged at intervals; the length direction of the active region graph of the N-type transmission tube is transverse;
a plurality of gate patterns arranged at intervals in a lateral direction; the length direction of the plurality of gate patterns is along the longitudinal direction; the grid patterns are spanned on the active region patterns of the N-type transmission tubes;
a gate cut pattern located between the active region patterns of the N-type transmission tube; the gate cutting patterns 300 cross over adjacent two of the gate patterns; the length direction of the grid electrode cutting pattern is along the transverse direction;
the longitudinal distance between the grid electrode cutting pattern and the active region pattern of the N-type transmission tube is 10-40 nm.
As shown in FIG. 2, FIG. 2 is a schematic diagram of a layout structure for regulating and controlling SRAM performance according to the present invention. In the layout structure of the present invention, active Area (AA) patterns 200 of a plurality of N-type transmission pipes (NPGs) are longitudinally arranged at intervals; the length direction of the Active Area (AA) graph of the N-type transmission tube (NPG) is transverse; the present invention defines the left-right direction in fig. 2 as the lateral direction; the vertical direction in fig. 2 is defined as the vertical direction.
As shown in fig. 2, a plurality of gate patterns 100 are arranged at intervals in a lateral direction; the length direction of the plurality of gate patterns 100 is along the longitudinal direction; the plurality of gate patterns straddle the active region patterns 200 of the plurality of N-type transmission tubes;
as shown in fig. 2, a gate cut pattern 300 is located between the active region patterns 200 of the N-type transmission pipe; the gate cutting patterns 300 cross over adjacent two of the gate patterns 100; the length direction of the gate cutting pattern 300 is along the lateral direction;
as shown in fig. 2, a longitudinal distance 400 between the gate cut pattern and the active region pattern 200 of the N-type transmission tube is 10 to 40nm. As shown in fig. 1, fig. 1 shows a schematic structure of an SRAM according to the present invention. The device comprises a P-type pull-up tube (PPU), an N-type transmission tube (NPG), an N-type pull-down tube (NPD) and a Bit line (Bit line) connected with the drain electrode of the NPG; a word line connected to the NPG gate, wherein the connection of the various pipes is described with reference to fig. 1.
The layout structure of the embodiment further comprises a pull-up tube active region, and the grid electrode is positioned between the pull-up tube active regions.
The invention also provides a method for regulating and controlling the performance of the SRAM by utilizing the layout structure, which at least comprises the following steps:
step one, providing the layout structure; adjusting a longitudinal distance 400 between the gate cutting pattern and an Active Area (AA) pattern 200 of the N-type transmission tube (NPG) to obtain a plurality of layout structures comprising different longitudinal distances 400; wherein the longitudinal distance is adjusted in the range of 10-40 nm.
In a first step of the present embodiment, the longitudinal distance between the gate cutting pattern and the active region pattern 200 of the N-type transmission tube is adjusted by changing the position of the cutting pattern 300 between the active region patterns 200 of the N-type transmission tube in the layout structure.
Further, in other embodiments, in the first step, the longitudinal distance between the gate cutting pattern and the active region pattern 200 of the N-type transmission tube may also be adjusted by changing the size of the cutting pattern 300 in the layout structure.
Performing a CMOS process by using the obtained layout structures with different longitudinal distances to finish device manufacturing and obtain a plurality of test devices;
in the second embodiment, the test device includes an SRAM structure, where the SRAM structure includes at least a pull-up tube, a pull-down tube, an N-type transmission tube, and NMOS and PMOS.
And thirdly, respectively performing WAT test by using the plurality of test devices, and extracting the threshold voltage Vtsat and the saturation current parameters of the NPG of the transmission tube.
In the third step of the present embodiment, the method further includes extracting electrical parameters of the SRAM.
The method of this embodiment further includes a fourth step of drawing threshold voltages of the NPG of the transmission tube corresponding to different longitudinal distances and saturation currents of the NPG of the transmission tube corresponding to different longitudinal distances, and selecting an optimal longitudinal distance between the gate cutting pattern and the active region pattern 200 of the N-type transmission tube. As shown in fig. 3 and 4, fig. 3 is a schematic diagram showing the change of the threshold voltage of the NPG according to the longitudinal distance between the gate cut pattern and the active region pattern of the N-type transmission tube in the present invention; fig. 4 is a graph showing the variation of the saturation current of the NPG according to the longitudinal distance between the gate cut pattern and the active region pattern of the N-type transmission tube according to the present invention. With the change of the distance between the cutting pattern Poly-cut and the active area (NPG AA) of the N-type transmission tube, compared with the traditional structure, the threshold voltage of the NPG is reduced by 20.5mV, and the saturation current is improved by 14%.
In summary, the invention relates to a method for regulating performance of a deep submicron CMOS integrated circuit MOSFET and an SRAM, which aims at regulating performance of the MOSFET device by regulating and controlling distance between gate cutting and an active region through a layout, and changing the proportional relation among transistors so as to achieve the purpose of controlling performance of the SRAM. Silicon oxide, silicon nitride and the like filling the groove after the gate line tail etching process can exert stress on the groove, and influence the performance threshold voltage of the MOSFET device; the stress applied to the channel is adjusted by changing the distance between the gate cutting and the active region, so that the device performance is changed to different degrees. The invention can independently regulate and control the device performance including threshold voltage, saturation current and the like on the basis of not changing the process flow, thereby controlling the performance of the SRAM, and being simple and easy to implement. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (8)
1. A layout structure for regulating and controlling SRAM performance is characterized by at least comprising:
active region patterns of a plurality of N-type transmission pipes longitudinally arranged at intervals; the length direction of the active region graph of the N-type transmission tube is transverse;
a plurality of gate patterns arranged at intervals in a lateral direction; the length direction of the plurality of gate patterns is along the longitudinal direction; the grid patterns are spanned on the active region patterns of the N-type transmission tubes;
a gate cut pattern located between the active region patterns of the N-type transmission tube; the grid electrode cutting patterns cross over two adjacent grid electrode patterns; the length direction of the grid electrode cutting pattern is along the transverse direction;
the longitudinal distance between the grid cutting pattern and the active region pattern of the N-type transmission tube is 10-40 nm; and adjusting the distance between the grid cutting pattern and the active region pattern of the N-type transmission tube to regulate and control the performance of the SRAM.
2. The layout structure for regulating performance of SRAM according to claim 1, wherein: the layout structure further comprises pull-up tube active regions, and the grid electrode is located between the pull-up tube active regions.
3. A method for regulating performance of an SRAM by using the layout structure of any one of claims 1 to 2, the method comprising at least the steps of:
step one, providing the layout structure; adjusting the longitudinal distance between the grid cutting pattern and the active region pattern (200) of the N-type transmission tube to obtain a plurality of layout structures with different longitudinal distances;
performing a CMOS process by using the obtained layout structures with different longitudinal distances to finish device manufacturing and obtain a plurality of test devices;
and thirdly, respectively performing WAT test by using the plurality of test devices, and extracting the threshold voltage and the saturation current parameters of the NPG of the transmission tube.
4. The method for regulating performance of an SRAM according to claim 3, wherein: in the first step, the longitudinal distance between the grid electrode cutting pattern and the active region pattern of the N-type transmission tube is adjusted by changing the position of the cutting pattern between the active region patterns of the N-type transmission tube in the layout structure.
5. The method for regulating performance of an SRAM according to claim 3, wherein: and in the first step, the longitudinal distance between the grid electrode cutting pattern and the active region pattern of the N-type transmission tube is adjusted by changing the size of the cutting pattern in the layout structure.
6. The method for regulating performance of an SRAM according to claim 3, wherein: the test device in the second step comprises an SRAM structure, wherein the SRAM structure at least comprises a pull-up tube, a pull-down tube, an N-type transmission tube, an NMOS and a PMOS.
7. The method for regulating performance of an SRAM according to claim 3, wherein: and step three, extracting electrical parameters of the SRAM.
8. A layout structure for regulating SRAM performance according to claim 3, wherein: the method further comprises the step four of drawing threshold voltages of the NPG of the transmission tube corresponding to different longitudinal distances and saturation currents of the NPG of the transmission tube corresponding to different longitudinal distances, and selecting the optimal longitudinal distance between the grid cutting pattern and the active region pattern of the N-type transmission tube.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107210297A (en) * | 2015-01-30 | 2017-09-26 | 高通股份有限公司 | Center deviation grid is cut |
| CN107408556A (en) * | 2015-03-25 | 2017-11-28 | 高通股份有限公司 | Fin FETs device for N/P tunings |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9537007B2 (en) * | 2015-04-07 | 2017-01-03 | Qualcomm Incorporated | FinFET with cut gate stressor |
| KR20210009503A (en) * | 2019-07-17 | 2021-01-27 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
| US11367479B2 (en) * | 2019-09-30 | 2022-06-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | SRAM structure and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107210297A (en) * | 2015-01-30 | 2017-09-26 | 高通股份有限公司 | Center deviation grid is cut |
| CN107408556A (en) * | 2015-03-25 | 2017-11-28 | 高通股份有限公司 | Fin FETs device for N/P tunings |
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