CN113644060B - Layout structure and method for regulating and controlling SRAM performance - Google Patents
Layout structure and method for regulating and controlling SRAM performance Download PDFInfo
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Abstract
本发明提供一种用于调控SRAM性能的版图结构及方法，提供版图结构，其中栅极切割图形与N型传输管的有源区图形之间的纵向距离为10～40nm；调节栅极切割图形与N型传输管的有源区图形之间的纵向距离，得到包含不同的纵向距离的多个版图结构；利用得到的包含不同的纵向距离的多个版图结构进行CMOS工艺，完成器件制造，得到多个测试器件；利用多个测试器件分别进行WAT测试，提取传输管NPG的阈值电压、饱和电流参数。本发明通过版图调控栅极切割与有源区间的距离来调节MOSFET器件性能，改变各晶体管间的比例关系，进而达到控制SRAM性能的目的。本发明在不改变工艺流程的基础上可以单独调控器件性能包括阈值电压、饱和电流等，进而可以控制SRAM的性能，简单易行。
The invention provides a layout structure and method for regulating SRAM performance. It provides a layout structure in which the longitudinal distance between the gate cutting pattern and the active area pattern of the N-type transfer tube is 10 to 40 nm; adjusting the gate cutting pattern and the longitudinal distance between the active area pattern of the N-type transmission tube to obtain multiple layout structures containing different longitudinal distances; use the obtained multiple layout structures containing different longitudinal distances to perform the CMOS process to complete device manufacturing, and obtain Multiple test devices; use multiple test devices to conduct WAT tests separately to extract the threshold voltage and saturation current parameters of the transmission tube NPG. The present invention adjusts the MOSFET device performance by adjusting the distance between the gate cutting and the active interval through the layout, changes the proportional relationship between each transistor, and thereby achieves the purpose of controlling the SRAM performance. The present invention can independently control device performance including threshold voltage, saturation current, etc. without changing the process flow, and thereby can control the performance of SRAM, which is simple and easy to implement.
Description
技术领域Technical field
本发明涉及半导体技术领域，特别是涉及一种用于调控SRAM性能的版图结构及方法。The present invention relates to the field of semiconductor technology, and in particular to a layout structure and method for regulating SRAM performance.
背景技术Background technique
随着半导体技术的不断发展，集成电路性能的提高主要是通过不断缩小器件尺寸以提高它的速度来实现的。目前，由于已经步入纳米技术工艺节点，半导体器件的制备受到各种物理极限的限制。With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of the device to increase its speed. At present, as we have entered the nanotechnology process node, the preparation of semiconductor devices is restricted by various physical limits.
SRAM的性能调控是通过调节各MOSFET间的比例关系来实现，具体为阈值电压离子注入，有源区宽度(AA width)，栅极多晶硅长度(Poly length)等。然而在阈值电压离子注入之后，较高的热预算，例如尖峰退火(spike anneal)等将导致阈值电压离子注入后的许多掺杂杂质损失到STI内或向外扩散，这将降低阈值电压掺杂杂质的灵敏度(sensitivity)，因此为了达到阈值电压VT的目标值，需要注入更多的掺杂杂质，这将导致晶格损伤和载流子迁移率降低，进而影响器件性能；而且离子注入无法实现SRAM中各MOSFET，尤其是SRAM中N型传输晶体管NPG和N型下拉晶体管NPD的单独调控。The performance control of SRAM is achieved by adjusting the proportional relationship between each MOSFET, specifically the threshold voltage ion implantation, active area width (AA width), gate polysilicon length (Poly length), etc. However, after the threshold voltage ion implantation, a higher thermal budget, such as spike anneal, etc. will cause many doping impurities after the threshold voltage ion implantation to be lost into the STI or diffuse out, which will reduce the threshold voltage doping. Sensitivity of impurities, so in order to achieve the target value of threshold voltage VT, more doping impurities need to be injected, which will cause lattice damage and reduced carrier mobility, thereby affecting device performance; and ion injection cannot be achieved Individual control of each MOSFET in SRAM, especially the N-type pass transistor NPG and N-type pull-down transistor NPD in SRAM.
发明内容Contents of the invention
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种用于调控SRAM性能的版图结构及方法，用于解决现有技术中SRAM性能不良的问题。In view of the above shortcomings of the prior art, the purpose of the present invention is to provide a layout structure and method for regulating SRAM performance to solve the problem of poor SRAM performance in the prior art.
为实现上述目的及其他相关目的，本发明提供用于调控SRAM性能的版图结构，至少包括：纵向间隔排列的多个N型传输管的有源区图形；所述N型传输管的有源区图形的长度方向沿横向；In order to achieve the above objects and other related objects, the present invention provides a layout structure for regulating SRAM performance, which at least includes: an active area pattern of a plurality of N-type transmission tubes arranged at longitudinal intervals; an active area of the N-type transmission tube The length of the graphic is along the transverse direction;
沿横向间隔排列的多个栅极图形；所述多个栅极图形的长度方向沿纵向；所述多个栅极图形跨在所述多个N型传输管的有源区图形上；A plurality of gate patterns arranged at intervals along the transverse direction; the length direction of the plurality of gate patterns is along the longitudinal direction; the plurality of gate patterns span the active area patterns of the plurality of N-type transmission tubes;
位于所述N型传输管的有源区图形之间的栅极切割图形；所述栅极切割图形横跨于相邻两个所述栅极图形上；所述栅极切割图形的长度方向沿所述横向；A gate cutting pattern located between the active area patterns of the N-type transfer tube; the gate cutting pattern spans two adjacent gate patterns; the length direction of the gate cutting pattern is along the transverse direction;
所述栅极切割图形与所述N型传输管的有源区图形之间的纵向距离为10～40nm。The longitudinal distance between the gate cutting pattern and the active area pattern of the N-type transfer tube is 10 to 40 nm.
优选地，所述版图结构还包括上拉管有源区，所述栅极位于所述上拉管有源区之间。Preferably, the layout structure further includes a pull-up tube active area, and the gate is located between the pull-up tube active areas.
本发明还提供一种利用所述版图结构调控SRAM性能的方法，该方法至少包括以下步骤：The present invention also provides a method for controlling SRAM performance using the layout structure, which method at least includes the following steps:
步骤一、提供所述版图结构；调节所述栅极切割图形与所述N型传输管的有源区图形之间的纵向距离，得到包含不同的所述纵向距离的多个所述版图结构；Step 1: Provide the layout structure; adjust the longitudinal distance between the gate cutting pattern and the active area pattern of the N-type transmission tube to obtain multiple layout structures including different longitudinal distances;
步骤二、利用得到的包含不同的所述纵向距离的多个所述版图结构进行CMOS工艺，完成器件制造，得到多个测试器件；Step 2: Use the obtained multiple layout structures containing different longitudinal distances to perform a CMOS process to complete device manufacturing and obtain multiple test devices;
步骤三、利用所述多个测试器件分别进行WAT测试，提取传输管NPG的阈值电压、饱和电流参数。Step 3: Use the multiple test devices to conduct WAT tests respectively, and extract the threshold voltage and saturation current parameters of the transmission tube NPG.
优选地，步骤一中通过改变所述版图结构中所述切割图形在所述N型传输管的有源区图形之间的位置，来调节所述栅极切割图形与所述N型传输管的有源区图形之间的纵向距离。Preferably, in step one, the position of the cutting pattern between the active area patterns of the N-type transmission tube in the layout structure is adjusted to adjust the relationship between the gate cutting pattern and the N-type transmission tube. The vertical distance between active area patterns.
优选地，步骤一中通过改变所述版图结构中所述切割图形的尺寸，来调节所述栅极切割图形与所述N型传输管的有源区图形之间的纵向距离。Preferably, in step one, the longitudinal distance between the gate cutting pattern and the active area pattern of the N-type transfer tube is adjusted by changing the size of the cutting pattern in the layout structure.
优选地，步骤二中的所述测试器件中包含SRAM结构，所述SRAM结构中至少包括上拉管、下拉管、N型传输管以及NMOS和PMOS。Preferably, the test device in step two includes an SRAM structure, and the SRAM structure at least includes a pull-up tube, a pull-down tube, an N-type transfer tube, NMOS and PMOS.
优选地，步骤三中还包括提取SRAM的电性参数。Preferably, step three also includes extracting the electrical parameters of the SRAM.
优选地，该方法还包括步骤四、绘制不同所述纵向距离对应的所述传输管NPG的阈值电压以及不同所述纵向距离对应的所述传输管NPG的饱和电流，选择最优的所述栅极切割图形与所述N型传输管的有源区图形之间的纵向距离。Preferably, the method further includes step 4: plotting the threshold voltage of the transmission tube NPG corresponding to different longitudinal distances and the saturation current of the transmission tube NPG corresponding to different longitudinal distances, and selecting the optimal gate. The longitudinal distance between the pole cutting pattern and the active area pattern of the N-type transmission tube.
如上所述，本发明的用于调控SRAM性能的版图结构及方法，具有以下有益效果：本发明涉及深亚微米CMOS集成电路MOSFET及SRAM性能调控的方法，本发明在于通过版图调控栅极切割与有源区间的距离来调节MOSFET器件性能，改变各晶体管间的比例关系，进而达到控制SRAM性能的目的。栅极线尾刻蚀工艺后填充沟槽的氧化硅、氮化硅等会对沟道施加应力，对MOSFET器件性能阈值电压造成影响；通过改变栅极切割与有源区间的距离，从而调节对沟道施加应力的大小，对器件性能带来不同程度的变化。本发明在不改变工艺流程的基础上可以单独调控器件性能包括阈值电压、饱和电流等，进而可以控制SRAM的性能，简单易行。As mentioned above, the layout structure and method for regulating SRAM performance of the present invention have the following beneficial effects: The present invention relates to a method for regulating the performance of deep submicron CMOS integrated circuit MOSFET and SRAM. The present invention is to control gate cutting and The distance between active intervals adjusts the performance of MOSFET devices and changes the proportional relationship between transistors, thereby achieving the purpose of controlling SRAM performance. Silicon oxide, silicon nitride, etc. that fill the trench after the gate line tail etching process will exert stress on the channel and affect the performance threshold voltage of the MOSFET device. By changing the distance between the gate cutting and the active area, the stress on the channel can be adjusted. The amount of stress exerted on the channel brings varying degrees of changes to device performance. The present invention can independently control device performance including threshold voltage, saturation current, etc. without changing the process flow, and thereby can control the performance of SRAM, which is simple and easy to implement.
附图说明Description of the drawings
图1显示为本发明的SRAM结构示意图；Figure 1 shows a schematic structural diagram of the SRAM of the present invention;
图2显示为本发明的用于调控SRAM性能的版图结构示意图；Figure 2 shows a schematic diagram of the layout structure for regulating SRAM performance according to the present invention;
图3显示为本发明中NPG的阈值电压随栅极切割图形与N型传输管的有源区图形之间的纵向距离变化示意图；Figure 3 shows a schematic diagram of the variation of the threshold voltage of the NPG with the longitudinal distance between the gate cutting pattern and the active area pattern of the N-type transfer tube in the present invention;
图4显示为本发明中NPG的饱和电流随栅极切割图形与N型传输管的有源区图形之间的纵向距离变化示意图。FIG. 4 is a schematic diagram showing the variation of the saturation current of the NPG with the longitudinal distance between the gate cutting pattern and the active area pattern of the N-type transfer tube in the present invention.
具体实施方式Detailed ways
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
请参阅图1至图4。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。See Figure 1 to Figure 4. It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. The drawings only show the components related to the present invention and do not follow the actual implementation of the component numbers, shapes and components. Dimension drawing, in actual implementation, the type, quantity and proportion of each component can be arbitrarily changed, and the component layout type may also be more complex.
本发明提供一种用于调控SRAM性能的版图结构，至少包括：The present invention provides a layout structure for regulating SRAM performance, which at least includes:
纵向间隔排列的多个N型传输管的有源区图形；所述N型传输管的有源区图形的长度方向沿横向；The active area pattern of a plurality of N-type transmission tubes arranged at longitudinal intervals; the length direction of the active area pattern of the N-type transmission tube is along the transverse direction;
沿横向间隔排列的多个栅极图形；所述多个栅极图形的长度方向沿纵向；所述多个栅极图形跨在所述多个N型传输管的有源区图形上；A plurality of gate patterns arranged at intervals along the transverse direction; the length direction of the plurality of gate patterns is along the longitudinal direction; the plurality of gate patterns span the active area patterns of the plurality of N-type transmission tubes;
位于所述N型传输管的有源区图形之间的栅极切割图形；所述栅极切割图形300横跨于相邻两个所述栅极图形上；所述栅极切割图形的长度方向沿所述横向；The gate cutting pattern located between the active area patterns of the N-type transfer tube; the gate cutting pattern 300 spans two adjacent gate patterns; the length direction of the gate cutting pattern along said transverse direction;
所述栅极切割图形与所述N型传输管的有源区图形之间的纵向距离为10～40nm。The longitudinal distance between the gate cutting pattern and the active area pattern of the N-type transfer tube is 10 to 40 nm.
如图2所示，图2显示为本发明的用于调控SRAM性能的版图结构示意图。本发明的所述版图结构中，纵向间隔排列的多个N型传输管(NPG)的有源区(AA)图形200；所述N型传输管(NPG)的有源区(AA)图形的长度方向沿横向；本发明将图2中的左右方向规定为所述横向；将图2中的上下反向规定为所述纵向。As shown in Figure 2, Figure 2 shows a schematic diagram of the layout structure for regulating SRAM performance according to the present invention. In the layout structure of the present invention, the active area (AA) pattern 200 of a plurality of N-type transmission tubes (NPG) arranged longitudinally at intervals; the active area (AA) pattern 200 of the N-type transmission tube (NPG) The length direction is along the transverse direction; in the present invention, the left and right directions in Figure 2 are defined as the transverse direction; the up and down directions in Figure 2 are defined as the longitudinal direction.
如图2所示，沿横向间隔排列的多个栅极图形100；所述多个栅极图形100的长度方向沿纵向；所述多个栅极图形跨在所述多个N型传输管的有源区图形200上；As shown in Figure 2, a plurality of gate patterns 100 are arranged at intervals along the transverse direction; the length direction of the plurality of gate patterns 100 is in the longitudinal direction; the plurality of gate patterns span across the plurality of N-type transmission tubes. On the active area graphic 200;
如图2所示，位于所述N型传输管的有源区图形200之间的栅极切割图形300；所述栅极切割图形300横跨于相邻两个所述栅极图形100上；所述栅极切割图形300的长度方向沿所述横向；As shown in Figure 2, the gate cutting pattern 300 is located between the active area patterns 200 of the N-type transfer tube; the gate cutting pattern 300 spans two adjacent gate patterns 100; The length direction of the gate cutting pattern 300 is along the transverse direction;
如图2所示，所述栅极切割图形与所述N型传输管的有源区图形200之间的纵向距离400为10～40nm。如图1所示，图1显示为本发明的SRAM结构示意图。其中包含P型上拉管(PPU)、N型传输管(NPG)、N型下拉管(NPD)以及与NPG漏极连接的位线(Bit line)；与NPG栅极连接的字线(word line)，其中各个管子的连接方式参阅图1。As shown in FIG. 2 , the longitudinal distance 400 between the gate cutting pattern and the active area pattern 200 of the N-type transfer tube is 10 to 40 nm. As shown in Figure 1, Figure 1 shows a schematic structural diagram of the SRAM of the present invention. It includes a P-type pull-up transistor (PPU), an N-type pass transistor (NPG), an N-type pull-down transistor (NPD), and a bit line connected to the NPG drain; a word line connected to the NPG gate line), please refer to Figure 1 for the connection method of each tube.
本发明进一步地，本实施例的所述版图结构还包括上拉管有源区，所述栅极位于所述上拉管有源区之间。Furthermore, the layout structure of this embodiment further includes an active area of a pull-up tube, and the gate is located between the active areas of the pull-up tube.
本发明还提供一种利用所述版图结构调控SRAM性能的方法，该方法至少包括以下步骤：The present invention also provides a method for controlling SRAM performance using the layout structure, which method at least includes the following steps:
步骤一、提供所述版图结构；调节所述栅极切割图形与所述N型传输管(NPG)的有源区(AA)图形200之间的纵向距离400，得到包含不同的所述纵向距离400的多个所述版图结构；其中该纵向距离的调节范围在10～40nm之间。Step 1: Provide the layout structure; adjust the longitudinal distance 400 between the gate cutting pattern and the active area (AA) pattern 200 of the N-type transmission tube (NPG) to obtain different longitudinal distances. A plurality of the layout structures of 400; wherein the adjustment range of the longitudinal distance is between 10 and 40 nm.
本发明进一步地，本实施例的步骤一中通过改变所述版图结构中所述切割图形300在所述N型传输管的有源区图形200之间的位置，来调节所述栅极切割图形与所述N型传输管的有源区图形200之间的纵向距离。Furthermore, in step 1 of this embodiment, the gate cutting pattern is adjusted by changing the position of the cutting pattern 300 between the active area patterns 200 of the N-type transmission tube in the layout structure. and the longitudinal distance between the active area pattern 200 of the N-type transmission tube.
进一步地，在其他实施例中，步骤一中也可以通过改变所述版图结构中所述切割图形300的尺寸，来调节所述栅极切割图形与所述N型传输管的有源区图形200之间的纵向距离。Further, in other embodiments, in step one, the gate cutting pattern and the active area pattern 200 of the N-type transfer tube can also be adjusted by changing the size of the cutting pattern 300 in the layout structure. the vertical distance between them.
步骤二、利用得到的包含不同的所述纵向距离的多个所述版图结构进行CMOS工艺，完成器件制造，得到多个测试器件；Step 2: Use the obtained multiple layout structures containing different longitudinal distances to perform a CMOS process to complete device manufacturing and obtain multiple test devices;
本发明进一步地，本实施例的步骤二中的所述测试器件中包含SRAM结构，所述SRAM结构中至少包括上拉管、下拉管、N型传输管以及NMOS和PMOS。Furthermore, the test device in step 2 of this embodiment includes an SRAM structure, and the SRAM structure at least includes a pull-up tube, a pull-down tube, an N-type transfer tube, an NMOS and a PMOS.
步骤三、利用所述多个测试器件分别进行WAT测试，提取传输管NPG的阈值电压Vtsat、饱和电流参数。Step 3: Use the multiple test devices to conduct WAT tests respectively, and extract the threshold voltage Vtsat and saturation current parameters of the transmission tube NPG.
本发明进一步地，本实施例的步骤三中还包括提取SRAM的电性参数。Furthermore, step three of this embodiment further includes extracting the electrical parameters of the SRAM.
本发明进一步地，本实施例的该方法还包括步骤四、绘制不同所述纵向距离对应的所述传输管NPG的阈值电压以及不同所述纵向距离对应的所述传输管NPG的饱和电流，选择最优的所述栅极切割图形与所述N型传输管的有源区图形200之间的纵向距离。如图3和图4所示，图3显示为本发明中NPG的阈值电压随栅极切割图形与N型传输管的有源区图形之间的纵向距离变化示意图；图4显示为本发明中NPG的饱和电流随栅极切割图形与N型传输管的有源区图形之间的纵向距离变化示意图。随切割图形Poly-cut和N型传输管的有源区(NPG AA)间距离变化，与传统结构相比，NPG的阈值电压减小了20.5mV，饱和电流提升了14％。Furthermore, the method of this embodiment further includes step 4: drawing the threshold voltage of the transmission tube NPG corresponding to different longitudinal distances and the saturation current of the transmission tube NPG corresponding to different longitudinal distances, and selecting The optimal longitudinal distance between the gate cutting pattern and the active area pattern 200 of the N-type transfer tube. As shown in Figures 3 and 4, Figure 3 shows a schematic diagram of the variation of the threshold voltage of the NPG with the longitudinal distance between the gate cutting pattern and the active area pattern of the N-type transfer tube in the present invention; Figure 4 shows a schematic diagram of the NPG threshold voltage in the present invention. Schematic diagram of the variation of NPG saturation current with the longitudinal distance between the gate cutting pattern and the active area pattern of the N-type transfer tube. As the distance between the cutting pattern Poly-cut and the active area (NPG AA) of the N-type transmission tube changes, compared with the traditional structure, the threshold voltage of the NPG is reduced by 20.5mV, and the saturation current is increased by 14%.
综上所述，本发明涉及深亚微米CMOS集成电路MOSFET及SRAM性能调控的方法，本发明在于通过版图调控栅极切割与有源区间的距离来调节MOSFET器件性能，改变各晶体管间的比例关系，进而达到控制SRAM性能的目的。栅极线尾刻蚀工艺后填充沟槽的氧化硅、氮化硅等会对沟道施加应力，对MOSFET器件性能阈值电压造成影响；通过改变栅极切割与有源区间的距离，从而调节对沟道施加应力的大小，对器件性能带来不同程度的变化。本发明在不改变工艺流程的基础上可以单独调控器件性能包括阈值电压、饱和电流等，进而可以控制SRAM的性能，简单易行。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。In summary, the present invention relates to a method for controlling the performance of MOSFET and SRAM in deep submicron CMOS integrated circuits. The present invention is to adjust the performance of the MOSFET device by controlling the distance between the gate cutting and the active interval through the layout, and change the proportional relationship between the transistors. , and then achieve the purpose of controlling SRAM performance. Silicon oxide, silicon nitride, etc. that fill the trench after the gate line tail etching process will exert stress on the channel and affect the performance threshold voltage of the MOSFET device. By changing the distance between the gate cutting and the active area, the stress on the channel can be adjusted. The amount of stress exerted on the channel brings varying degrees of changes to device performance. The present invention can independently control device performance including threshold voltage, saturation current, etc. without changing the process flow, and thereby can control the performance of SRAM, which is simple and easy to implement. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。The above embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.
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