CN113641616A - COMe module based on bilateral connector - Google Patents
COMe module based on bilateral connector Download PDFInfo
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- CN113641616A CN113641616A CN202110902283.9A CN202110902283A CN113641616A CN 113641616 A CN113641616 A CN 113641616A CN 202110902283 A CN202110902283 A CN 202110902283A CN 113641616 A CN113641616 A CN 113641616A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention provides a COMe module based on a double-edge connector, wherein the COMe module is installed on a buckle plate and is inserted into a backplane customized for an application, the COMe module comprises a CPU, a CPLD and the double-edge connector, the double-edge connector comprises a first double-edge connector, a second double-edge connector and a third double-edge connector, the first double-edge connector comprises a first edge connector A and a first edge connector B, the first edge connector A comprises a 60-bit interface A1-A60, and the first edge connector B comprises a 60-bit interface B1-B60; the second dual edge connector includes a second edge connector C and a second edge connector D. The COMe module based on the double-edge connector obviously reduces the cost of the connector, solves the problem of unmatched impedance of the COMe connector, can be upgraded to 25Gbps with packaging, has strong PCB expansion capability and strong signal definition expansibility, and can meet the requirement of product upgrading.
Description
Technical Field
The invention belongs to the technical field of COMe modules, and particularly relates to a COMe module based on a double-edge connector.
Background
The COM Express standard was first released in 2005 and provided a standardized module interface by the PCI industrial computer manufacturers association (PICMG) and its search for several different target applications. COM Express is the form factor of a modular Computer (COM), a highly integrated and compact PC, and can be used in design applications like integrated circuit packages. Each COM Express module integrates core CPU and memory functions, general purpose I/O, USB, audio, graphics (PEG) and Ethernet. All I/O signals are mapped to two high density low profile connectors at the bottom of the module. The COMe module plugs into a backplane that is typically customized for the application. COM Express mezzanine modules can be upgraded over time to newer, backwards-compatible versions. COM Express is commonly used in industrial, military/aerospace, medical, transportation, internet of things, and dual edge connector general purpose computing embedded applications.
The COMe connector is expensive to define, and in actual test, due to the fact that the impedance of the connector itself is discontinuous, the impedance of the whole high-speed signal link is not matched, and the insertion loss of the high-speed signal is large. The highest rate can only be supported up to 10Gbps, while the signal definition cannot meet the new requirements.
Disclosure of Invention
The present invention is directed to solve the above technical problems, and provides a COMe module based on a dual-edge connector.
In order to achieve the purpose, the invention adopts the following technical scheme:
a COMe module based on a double-edge connector is installed on a buckle plate and is inserted into a backplane customized for an application, the COMe module comprises a CPU, a CPLD and the double-edge connector, and the double-edge connector comprises a first double-edge connector; the first dual edge connector comprises a first edge connector A comprising a 60-bit interface A1-A60 and a first edge connector B comprising a 60-bit interface B1-B60;
the interfaces A1-A4 are power supply interfaces, each interface is connected with 12V input voltage, and the current of each pin is 0.5A; interfaces A5, a11, a17, a20, a21, a24, a25, a28, a29, a32, a33, a36, a37, a40, a41, a44, a45, a48, a49, a52, a53, a56, a57 and a60 are power ground interfaces; the interface A6 is an RSV interface, the interface A6 is connected out from the logic circuit and is used as a general interface, and high or low is written by software; the interfaces A7 and A9 are serial port sending interfaces, are respectively connected with two serial port sending pins of the CPU, and are then connected to the bottom plate through a logic circuit; the interfaces A8 and A10 are serial port receiving interfaces and are respectively connected with two serial port receiving pins of the CPU; the interface A12 is a data signal line SDA interface of an I2C bus and is connected with an SMB _ HOST data pin of a CPU; interface A13 is the data signal line SCL interface of I2C bus, SMB _ HOST clock pin of connecting CPU; the interface A14 is a universal interface of MDC, or a serial gigabit media independent interface of MDC, or a local area network interface of data signal line SCL of I2C bus, the universal interface of MDC is connected out from a logic circuit and is used for configuring a port physical layer PHY and a switch which cannot be managed by a CPU, and the serial gigabit media independent interface of MDC is connected out from the port physical layer PHY and is used by matching with the serial gigabit media independent interface of the port physical layer PHY; the interface A15 is a universal interface of the MDIO, or a serial gigabit media independent interface of the MDIO, or a local area network interface of a data signal line SDA of an I2C bus, the universal interface of the MDIO is connected out from a logic circuit and is used for configuring a port physical layer PHY and a switch which cannot be managed by a CPU, and the serial gigabit media independent interface of the MDIO is connected out from the port physical layer PHY and is used by matching with the serial gigabit media independent interface of the port physical layer PHY; interface A16 is a reset interface, which is connected from the logic circuit to make the pinch plate give the global reset signal to the bottom plate; interfaces A18 and A19 are PCIE clock positive interface and PCIE clock negative interface, and are used for outputting a PCIE homologous clock from a CPU to a bottom plate, a pinch plate is in direct current coupling without capacitance, and HCSL level is adopted; the interfaces A22, A23, interfaces A26, A27, interfaces A30 and A31 are three groups of USB positive data interfaces and USB negative data interfaces, wherein the interfaces A22 and A23 are used for receiving USB2.0 signals, and the interfaces A26, A27, A30 and A31 are used for receiving USB3.0 signals; interfaces A34 and A35 are SATA positive electrode receiving interfaces and SATA negative electrode receiving interfaces and are used for receiving SATA signals; the interfaces A38, A39, interfaces A42, A43, interfaces A46, A47, interfaces A50 and A51 are 4 groups of PCIe positive pole receiving interfaces and PCIe negative pole receiving interfaces and are used for receiving PCIe signals; the interfaces A38 and A38 can also be used as an RP end and an RN end of a serial gigabit media independent interface, and the serial gigabit media independent interface is connected out of the PHY; the interfaces A54, A55, A58 and A59 are two groups of local area network receiving positive interfaces and local area network receiving negative interfaces;
the interfaces B1-B4 are power supply interfaces, each interface is connected with 12V input voltage, and the current of each pin is 0.5B; interfaces B5, B9, B14, B18, B19, B22, B23, B26, B27, B30, B31, B34, B35, B38, B39, B42, B43, B46, B47, B50, B51, B54, B55, B58, and B59 are power ground interfaces; interface B6 is SPI clock interface, interface B7 is SPI MOSI interface, interface B8 is SPI MISO interface, interfaces B10, B11, B12 are SPI chip select interfaces; interfaces B11, B12 may also be generic interfaces; interface B12 may also be used as a lan LED lamp data interface; b13 is a reset circuit direct current input interface, the bottom plate gives a buckle plate reset signal, and the buckle plate is pulled up by default; the interfaces B15 and B16 are MDC interfaces and MDIO interfaces, the MDC interfaces are connected from a local area network controller of the CPU and are used for managing a port physical layer PHY or a switch on a CPU local area network bus, or the interfaces B15 and B16 are local area network interfaces of the MDC and the MDIO, or the interfaces B15 and B16 are local area network interfaces of a data signal line SCL of an I2C bus and a data signal line SDA of an I2C bus; the interface B17 is PG signal enable interface, bottom plate power OK and pinch plate power-on enable signal; the interfaces B20, B21, B24, B25, B28 and B29 are three groups of USB positive data interfaces and USB negative data interfaces, wherein the interfaces B20 and B21 send USB2.0 signals, and the interfaces B24, B25, B28 and B29 send USB3.0 signals; interfaces B32 and B33 are SATA positive electrode sending interfaces and SATA negative electrode sending interfaces and are used for SATA signals; the interfaces B36, B37, interfaces B40, B41, interfaces B44, B45, interfaces B48 and B49 are 4 groups of PCIe positive interfaces and PCIe negative interfaces and are used for PCIe sending signals; the interfaces B36 and B37 can also be used as TP end and TN end of the serial gigabit media independent interface; the interfaces B52, B53, B56 and B57 are positive interfaces for LAN transmission and negative interfaces for LAN transmission.
Preferably, the dual edge connector further comprises a second dual edge connector comprising a second edge connector C and a second edge connector D; the second edge connector C comprises 60-bit interfaces C1-C60, and the second edge connector D comprises 60-bit interfaces D1-D60;
the interfaces C1-C5 are power supply interfaces, each interface is connected with 12V input voltage, and the current of each pin is 0.5A; interfaces C6, C10, C13, C16, C17, C20, C21, C24, C25, C28, C29, C32, C33, C36, C37, C40, C41, C44, C45, C48, C49, C52, C53, C56, C57 and C60 are power ground interfaces; the interface C7 is a BAT power supply interface and is used for supplying power to an RTC (real time clock) in the CPU, or the interface C7 is used as a general interface; interfaces C8 and C11 are local area network interfaces of MDC, or interfaces C8 and C11 are local area network interfaces of a data signal line SCL of an I2C bus, or interfaces C8 and C11 are universal interfaces; interfaces C9 and C12 are local area network interfaces of MDIO, or interfaces C9 and C12 are local area network interfaces of a data signal line SDA of an I2C bus, or interfaces C9 and C12 are universal interfaces; the interfaces C14 and C15 are a group of USB positive data interfaces and USB negative data interfaces and are used for receiving USB2.0 signals; interfaces C18 and C19 are SATA positive electrode receiving interfaces and SATA negative electrode receiving interfaces and are used for receiving SATA signals; the interfaces C22, C23, interfaces C26, C27, interfaces C30, C31, interfaces C34, C35, interfaces C38, C39, interfaces C42, C43, interfaces C46, C47, interfaces C50 and C51 are 8 sets of PCIe positive pole receiving interfaces and PCIe negative pole receiving interfaces and are used for receiving PCIe signals; the interfaces C54, C55, C58 and C59 are two groups of local area network receiving positive interfaces and local area network receiving negative interfaces;
the interfaces D1-D5 are power supply interfaces, each interface is connected with 12V input voltage, and the current of each pin is 0.5A; interfaces D6, D10, D14, D15, D18, D19, D22, D23, D26, D27, D30, D31, D34, D35, D38, D39, D42, D43, D46, D47, D50, D51, D54, D55, D58 and D59 are power supply ground interfaces; the interface D7 is an RSV interface, or D7 is used as a low device reset signal PLTRST interface of the CPU; the interfaces D8, D9, D11 and D12 are BMC serial peripheral interfaces which are respectively a BMC serial peripheral clock interface, a BMC serial peripheral chip selection signal interface, a BMC serial peripheral MISO interface and a BMC serial peripheral MOSI interface; the interface D13 is a power button interface, or D13 is used as a universal interface; the interfaces D16 and D17 are SATA positive electrode sending interfaces and SATA sending and receiving interfaces and are used for SATA signals; the interfaces D20, D21, interfaces D24, D25, interfaces D28, D29, interfaces D32, D33, interfaces D36, D37, interfaces D40, D41, interfaces D44, D45, interfaces D48 and D49 are 8 groups of PCIe positive interfaces and PCIe negative interfaces and are used for PCIe sending signals; the interfaces D52, D53, D56 and D57 are a local area network sending positive electrode interface and a local area network sending negative electrode interface; the interface D60 is an SUS clock interface used by an m.2 hard disk, or the interface D60 is a general-purpose interface.
Preferably, the dual edge connector further comprises a third dual edge connector comprising a third edge connector E and a third edge connector F; the third edge connector E comprises 60-bit interfaces E1-E60, and the third edge connector F comprises 60-bit interfaces F1-F60;
the interfaces E1-E7 are power supply interfaces, each interface is connected with 12V input voltage, and the current of each pin is 0.5A; interfaces E8, E9, E12, E16, E20, E21, E24, E25, E28, E29, E32, E33, E36, E37, E40, E41, E44, E45, E48, E49, E52, E53, E56, E57, E60 are power ground interfaces; interfaces E10 and E11 are serial peripheral interfaces of BMC upgrade bios, namely a serial peripheral MOSI interface of the BMC upgrade bios and a serial peripheral clock interface of the BMC upgrade bios, wherein the BMC is used as a master and the spifly is used as a slave; the interfaces E13 and E14 are a BMC data signal line SCL interface of the I2C bus and a BMC data signal line SDA interface of the I2C bus; the interface E15 is a BMC data signal line reminding interface of the I2C bus, or the interface E15 is used as a universal interface, or the interface E15 is used as a BMC input interface; the interface E17 is a SERIRQ serial interrupt interface of an LPC bus, the LPC bus is used for connecting a CPU and a CPLD, or the interface E17 is used as a chip selection signal interface of EPSI; the interface E18 is used as a reset interface of EPSI or a general interface; the interface E19 is used as a clock interface of an LPC bus or an EPSI; the interfaces E22, E23, E26 and E27 are RSV interfaces, or the interface E22 is used as a power supply interface of 1V 05; the interfaces E30, E31, interfaces E34, E35, interfaces E38, E39, interfaces E42, E43, interfaces E46, E47, interfaces E50, E51, interfaces E54, E55, interfaces E58 and E59 are 8 groups of SERDES receiving positive interfaces and SERDES receiving negative interfaces;
the interfaces F1-F7 are power supply interfaces, each interface is connected with 12V input voltage, and the current of each pin is 0.5A; interfaces F8, F9, F12, F19, F22, F23, F26, F27, F30, F31, F34, F35, F38, F39, F42, F43, F46, F47, F50, F51, F54, F55, F58, F59 are power ground interfaces; interfaces F10 and F11 are serial peripheral MISO interfaces of BMC upgrade bios and serial peripheral chip select signal interfaces of BMC upgrade bios, BMC is the master, spiflash is the slave; interfaces F13, F14, F15 and F16 are AD interfaces of LPC buses, or interfaces F13, F14, F15 and F16 are IO interfaces of ESPI; interface F17 is the data frame interface of LPC bus, or interface F17 is the chip selection interface of ESPI; the interface F18 is a universal interface of the BMC; the interfaces F20 and F21 are the ME interface of the CPU of the data signal line SCL of the I2C bus and the ME interface of the CPU of the data signal line SDA of the I2C bus; interfaces F24 and F25 are RSV interfaces; interfaces F28, F29, interfaces F32, F33, interfaces F36, F37, interfaces F40, F41, interfaces F44, F45, interfaces F48, F49, interfaces F52, F53, interfaces F56 and F57 are 8 groups of SERDES positive sending interfaces and SERDES negative sending interfaces; the interface F60 is a PECI interface, or the interface F60 is a general interface.
After the technical scheme is adopted, the invention has the following advantages:
according to the invention, through the arrangement of the double-edge connector, a distributed open platform fusing network, calculation, storage and application core capabilities is arranged on the network edge side close to a data source, so that edge intelligent service is provided nearby, and the key requirements of industry digitization on aspects of agile connection, real-time service, data optimization, application intelligence, safety, privacy protection and the like are met. It can be used as a bridge to connect physical and digital worlds, enabling intelligent assets, intelligent gateways, intelligent systems and intelligent services.
Secondly, the dual-edge connector provides a BMC interface, and BMC needs to be realized on a bottom plate; providing 8XPCIe 1 or 4X PCIe 2 or 2XPCIe 4 or 1XPCIe 8 interfaces and supporting PCIe V3.1 protocol; providing 4 paths of SGMII/KR interfaces, and supporting 10G at most; providing 2 paths of UART interfaces; providing 2 paths of SATA 3.0 interfaces; providing 3 paths of USB2.0 interfaces and 2 paths of USB3.0 interfaces; providing a path of LPC interface to a bottom plate; providing a 1-path SPI interface and accessing a bottom plate logic register; providing a 1-way I2C interface to a backplane; providing a path of MDC/MDIO interface to a backplane; the bottom plate reports an interrupt signal to the pinch plate through the serial interrupt signal; providing a 1-way 100M PCIE clock to a backplane; providing a single board running state and voltage state monitoring function; the single board supports ICT test; the single board supports JTAG testing.
Therefore, the COMe module based on the double-edge connector obviously reduces the cost of the connector, solves the problem of impedance mismatching of the COMe connector, can be upgraded to 25Gbps with the package, has strong PCB expansion capability and strong signal definition expansibility, and can meet the requirement of product upgrading.
Drawings
FIG. 1 is a schematic diagram of a COMe module.
Detailed Description
The present invention will be described in further detail with reference to the following drawings and specific examples.
A COMe module based on a double-edge connector is installed on a buckle plate and is inserted into a backplane customized for an application, the COMe module comprises a CPU, a CPLD and the double-edge connector, and the double-edge connector comprises a first double-edge connector, a second double-edge connector and a third double-edge connector.
The first dual edge connector comprises a first edge connector A comprising a 60-bit interface A1-A60 and a first edge connector B comprising a 60-bit interface B1-B60; the second dual edge connector comprises a second edge connector C comprising a 60-bit interface C1-C60 and a second edge connector D comprising a 60-bit interface D1-D60; the third dual edge connector comprises a third edge connector E and a third edge connector F, wherein the third edge connector E comprises a 60-bit interface E1-E60, and the third edge connector F comprises a 60-bit interface F1-F60.
The interfaces A1-A4 are power supply interfaces, each interface is connected with 12V input voltage, and the current of each pin is 0.5A; interfaces A5, a11, a17, a20, a21, a24, a25, a28, a29, a32, a33, a36, a37, a40, a41, a44, a45, a48, a49, a52, a53, a56, a57 and a60 are power ground interfaces; interface A6 is an RSV interface, which is a reserved interface called by a specific program/thread, and interface A6 is connected out from a logic circuit and used as a general interface, and is written high or low by software; the interfaces A7 and A9 are serial port sending interfaces, are respectively connected with two serial port sending pins of the CPU, and are then connected to the bottom plate through a logic circuit; the interfaces A8 and A10 are serial port receiving interfaces and are respectively connected with two serial port receiving pins of the CPU; the interface A12 is a data signal line SDA interface of an I2C bus and is connected with an SMB _ HOST data pin of a CPU; interface A13 is the data signal line SCL interface of I2C bus, SMB _ HOST clock pin of connecting CPU; the interface A14 is a universal interface of MDC, or a serial gigabit media independent interface of MDC, or a local area network interface of data signal line SCL of I2C bus, the universal interface of MDC is connected out from a logic circuit and is used for configuring a port physical layer PHY and a switch which cannot be managed by a CPU, and the serial gigabit media independent interface of MDC is connected out from the port physical layer PHY and is used by matching with the serial gigabit media independent interface of the port physical layer PHY; the interface A15 is a universal interface of the MDIO, or a serial gigabit media independent interface of the MDIO, or a local area network interface of a data signal line SDA of an I2C bus, the universal interface of the MDIO is connected out from a logic circuit and is used for configuring a port physical layer PHY and a switch which cannot be managed by a CPU, and the serial gigabit media independent interface of the MDIO is connected out from the port physical layer PHY and is used by matching with the serial gigabit media independent interface of the port physical layer PHY; interface A16 is a reset interface, which is connected from the logic circuit to make the pinch plate give the global reset signal to the bottom plate; interfaces A18 and A19 are PCIE clock positive interface and PCIE clock negative interface, and are used for outputting a PCIE homologous clock from a CPU to a bottom plate, a pinch plate is in direct current coupling without capacitance, and HCSL level is adopted; the interfaces A22, A23, interfaces A26, A27, interfaces A30 and A31 are three groups of USB positive data interfaces and USB negative data interfaces, wherein the interfaces A22 and A23 are used for receiving USB2.0 signals, and the interfaces A26, A27, A30 and A31 are used for receiving USB3.0 signals; interfaces A34 and A35 are SATA positive electrode receiving interfaces and SATA negative electrode receiving interfaces and are used for receiving SATA signals; the interfaces A38, A39, interfaces A42, A43, interfaces A46, A47, interfaces A50 and A51 are 4 groups of PCIe positive pole receiving interfaces and PCIe negative pole receiving interfaces and are used for receiving PCIe signals; the interfaces A38 and A38 can also be used as an RP end and an RN end of a serial gigabit media independent interface, and the serial gigabit media independent interface is connected out of the PHY; the interfaces A54, A55, A58 and A59 are two groups of local area network receiving positive interfaces and local area network receiving negative interfaces;
the interfaces B1-B4 are power supply interfaces, each interface is connected with 12V input voltage, and the current of each pin is 0.5B; interfaces B5, B9, B14, B18, B19, B22, B23, B26, B27, B30, B31, B34, B35, B38, B39, B42, B43, B46, B47, B50, B51, B54, B55, B58, and B59 are power ground interfaces; interface B6 is SPI clock interface, interface B7 is SPI MOSI interface, interface B8 is SPI MISO interface, interfaces B10, B11, B12 are SPI chip select interfaces; interfaces B11, B12 may also be generic interfaces; interface B12 may also be used as a lan LED lamp data interface; b13 is a reset circuit direct current input interface, the bottom plate gives a buckle plate reset signal, and the buckle plate is pulled up by default; the interfaces B15 and B16 are MDC interfaces and MDIO interfaces, the MDC interfaces are connected from a local area network controller of the CPU and are used for managing a port physical layer PHY or a switch on a CPU local area network bus, or the interfaces B15 and B16 are local area network interfaces of the MDC and the MDIO, or the interfaces B15 and B16 are local area network interfaces of a data signal line SCL of an I2C bus and a data signal line SDA of an I2C bus; the interface B17 is PG signal enable interface, bottom plate power OK and pinch plate power-on enable signal; the interfaces B20, B21, B24, B25, B28 and B29 are three groups of USB positive data interfaces and USB negative data interfaces, wherein the interfaces B20 and B21 send USB2.0 signals, and the interfaces B24, B25, B28 and B29 send USB3.0 signals; interfaces B32 and B33 are SATA positive electrode sending interfaces and SATA negative electrode sending interfaces and are used for SATA signals; the interfaces B36, B37, interfaces B40, B41, interfaces B44, B45, interfaces B48 and B49 are 4 groups of PCIe positive interfaces and PCIe negative interfaces and are used for PCIe sending signals; the interfaces B36 and B37 can also be used as TP end and TN end of the serial gigabit media independent interface; the interfaces B52, B53, B56 and B57 are positive interfaces for LAN transmission and negative interfaces for LAN transmission.
The interfaces C1-C5 are power supply interfaces, each interface is connected with 12V input voltage, and the current of each pin is 0.5A; interfaces C6, C10, C13, C16, C17, C20, C21, C24, C25, C28, C29, C32, C33, C36, C37, C40, C41, C44, C45, C48, C49, C52, C53, C56, C57 and C60 are power ground interfaces; the interface C7 is a BAT power supply interface and is used for supplying power to an RTC (real time clock) in the CPU, or the interface C7 is used as a general interface; interfaces C8 and C11 are local area network interfaces of MDC, or interfaces C8 and C11 are local area network interfaces of a data signal line SCL of an I2C bus, or interfaces C8 and C11 are universal interfaces; interfaces C9 and C12 are local area network interfaces of MDIO, or interfaces C9 and C12 are local area network interfaces of a data signal line SDA of an I2C bus, or interfaces C9 and C12 are universal interfaces; the interfaces C14 and C15 are a group of USB positive data interfaces and USB negative data interfaces and are used for receiving USB2.0 signals; interfaces C18 and C19 are SATA positive electrode receiving interfaces and SATA negative electrode receiving interfaces and are used for receiving SATA signals; the interfaces C22, C23, interfaces C26, C27, interfaces C30, C31, interfaces C34, C35, interfaces C38, C39, interfaces C42, C43, interfaces C46, C47, interfaces C50 and C51 are 8 sets of PCIe positive pole receiving interfaces and PCIe negative pole receiving interfaces and are used for receiving PCIe signals; the interfaces C54, C55, C58 and C59 are two groups of local area network receiving positive interfaces and local area network receiving negative interfaces;
the interfaces D1-D5 are power supply interfaces, each interface is connected with 12V input voltage, and the current of each pin is 0.5A; interfaces D6, D10, D14, D15, D18, D19, D22, D23, D26, D27, D30, D31, D34, D35, D38, D39, D42, D43, D46, D47, D50, D51, D54, D55, D58 and D59 are power supply ground interfaces; the interface D7 is an RSV interface, or D7 is used as a low device reset signal PLTRST interface of the CPU; the interfaces D8, D9, D11 and D12 are BMC serial peripheral interfaces which are respectively a BMC serial peripheral clock interface, a BMC serial peripheral chip selection signal interface, a BMC serial peripheral MISO interface and a BMC serial peripheral MOSI interface; the interface D13 is a power button interface, or D13 is used as a universal interface; the interfaces D16 and D17 are SATA positive electrode sending interfaces and SATA sending and receiving interfaces and are used for SATA signals; the interfaces D20, D21, interfaces D24, D25, interfaces D28, D29, interfaces D32, D33, interfaces D36, D37, interfaces D40, D41, interfaces D44, D45, interfaces D48 and D49 are 8 groups of PCIe positive interfaces and PCIe negative interfaces and are used for PCIe sending signals; the interfaces D52, D53, D56 and D57 are a local area network sending positive electrode interface and a local area network sending negative electrode interface; the interface D60 is an SUS clock interface used by an m.2 hard disk, or the interface D60 is a general-purpose interface.
The interfaces E1-E7 are power supply interfaces, each interface is connected with 12V input voltage, and the current of each pin is 0.5A; interfaces E8, E9, E12, E16, E20, E21, E24, E25, E28, E29, E32, E33, E36, E37, E40, E41, E44, E45, E48, E49, E52, E53, E56, E57, E60 are power ground interfaces; interfaces E10 and E11 are serial peripheral interfaces of BMC upgrade bios, namely a serial peripheral MOSI interface of the BMC upgrade bios and a serial peripheral clock interface of the BMC upgrade bios, wherein the BMC is used as a master and the spifly is used as a slave; the interfaces E13 and E14 are a BMC data signal line SCL interface of the I2C bus and a BMC data signal line SDA interface of the I2C bus; the interface E15 is a BMC data signal line reminding interface of the I2C bus, or the interface E15 is used as a universal interface, or the interface E15 is used as a BMC input interface; the interface E17 is a SERIRQ serial interrupt interface of an LPC bus, the LPC bus is used for connecting a CPU and a CPLD, or the interface E17 is used as a chip selection signal interface of EPSI; the interface E18 is used as a reset interface of EPSI or a general interface; the interface E19 is used as a clock interface of an LPC bus or an EPSI; the interfaces E22, E23, E26 and E27 are RSV interfaces, or the interface E22 is used as a power supply interface of 1V 05; the interfaces E30, E31, interfaces E34, E35, interfaces E38, E39, interfaces E42, E43, interfaces E46, E47, interfaces E50, E51, interfaces E54, E55, interfaces E58 and E59 are 8 groups of SERDES receiving positive interfaces and SERDES receiving negative interfaces;
the interfaces F1-F7 are power supply interfaces, each interface is connected with 12V input voltage, and the current of each pin is 0.5A; interfaces F8, F9, F12, F19, F22, F23, F26, F27, F30, F31, F34, F35, F38, F39, F42, F43, F46, F47, F50, F51, F54, F55, F58, F59 are power ground interfaces; interfaces F10 and F11 are serial peripheral MISO interfaces of BMC upgrade bios and serial peripheral chip select signal interfaces of BMC upgrade bios, BMC is the master, spiflash is the slave; interfaces F13, F14, F15 and F16 are AD interfaces of LPC buses, or interfaces F13, F14, F15 and F16 are IO interfaces of ESPI; interface F17 is the data frame interface of LPC bus, or interface F17 is the chip selection interface of ESPI; the interface F18 is a universal interface of the BMC; the interfaces F20 and F21 are the ME interface of the CPU of the data signal line SCL of the I2C bus and the ME interface of the CPU of the data signal line SDA of the I2C bus; interfaces F24 and F25 are RSV interfaces; interfaces F28, F29, interfaces F32, F33, interfaces F36, F37, interfaces F40, F41, interfaces F44, F45, interfaces F48, F49, interfaces F52, F53, interfaces F56 and F57 are 8 groups of SERDES positive sending interfaces and SERDES negative sending interfaces; the interface F60 is a PECI interface, or the interface F60 is a general interface.
As shown in fig. 1, the COMe module uses a schematic structural diagram of a first dual-edge connector; alternatively, the COMe module may use a first dual edge connector and a second dual edge connector; alternatively, the COMe module may use a first dual edge connector, a second dual edge connector, and a third dual edge connector. The maximum current support using the first dual-edge connector is 4A, the maximum current support using the first dual-edge connector and the second dual-edge connector is 9A, and the maximum current support using the first dual-edge connector, the second dual-edge connector and the third dual-edge connector is 14A.
The universal interface module of the dual edge connector must be designed strictly according to hardware to ensure compatibility of the new buckle plate with each product base plate and replaceability between each universal buckle plate.
The dual-edge connector provides a BMC interface, and BMC needs to be realized on a bottom plate; providing 8XPCIe 1 or 4X PCIe 2 or 2XPCIe 4 or 1XPCIe 8 interfaces and supporting PCIe V3.1 protocol; providing 4 paths of SGMII/KR interfaces, and supporting 10G at most; providing 2 paths of UART interfaces; providing 2 paths of SATA 3.0 interfaces; providing 3 paths of USB2.0 interfaces and 2 paths of USB3.0 interfaces; providing a path of LPC interface to a bottom plate; providing a 1-path SPI interface and accessing a bottom plate logic register; providing a 1-way I2C interface to a backplane; providing a path of MDC/MDIO interface to a backplane; the bottom plate reports an interrupt signal to the pinch plate through the serial interrupt signal; providing a 1-way 100M PCIE clock to a backplane; providing a single board running state and voltage state monitoring function; the single board supports ICT test; the single board supports JTAG testing.
Other embodiments of the present invention than the preferred embodiments described above will be apparent to those skilled in the art from the present invention, and various changes and modifications can be made therein without departing from the spirit of the present invention as defined in the appended claims.
Claims (3)
1. A COMe module based on a double-edge connector, the COMe module is arranged on a buckle plate and is inserted into a bottom plate customized for an application,
the COMe module comprises a CPU, a CPLD and a double-edge connector, wherein the double-edge connector comprises a first double-edge connector; the first dual edge connector comprises a first edge connector A comprising a 60-bit interface A1-A60 and a first edge connector B comprising a 60-bit interface B1-B60;
the interfaces A1-A4 are power supply interfaces, each interface is connected with 12V input voltage, and the current of each pin is 0.5A; interfaces A5, a11, a17, a20, a21, a24, a25, a28, a29, a32, a33, a36, a37, a40, a41, a44, a45, a48, a49, a52, a53, a56, a57 and a60 are power ground interfaces; the interface A6 is an RSV interface, the interface A6 is connected out from the logic circuit and is used as a general interface, and high or low is written by software; the interfaces A7 and A9 are serial port sending interfaces, are respectively connected with two serial port sending pins of the CPU, and are then connected to the bottom plate through a logic circuit; the interfaces A8 and A10 are serial port receiving interfaces and are respectively connected with two serial port receiving pins of the CPU; the interface A12 is a data signal line SDA interface of an I2C bus and is connected with an SMB _ HOST data pin of a CPU; interface A13 is the data signal line SCL interface of I2C bus, SMB _ HOST clock pin of connecting CPU; the interface A14 is a universal interface of MDC, or a serial gigabit media independent interface of MDC, or a local area network interface of data signal line SCL of I2C bus, the universal interface of MDC is connected out from a logic circuit and is used for configuring a port physical layer PHY and a switch which cannot be managed by a CPU, and the serial gigabit media independent interface of MDC is connected out from the port physical layer PHY and is used by matching with the serial gigabit media independent interface of the port physical layer PHY; the interface A15 is a universal interface of the MDIO, or a serial gigabit media independent interface of the MDIO, or a local area network interface of a data signal line SDA of an I2C bus, the universal interface of the MDIO is connected out from a logic circuit and is used for configuring a port physical layer PHY and a switch which cannot be managed by a CPU, and the serial gigabit media independent interface of the MDIO is connected out from the port physical layer PHY and is used by matching with the serial gigabit media independent interface of the port physical layer PHY; interface A16 is a reset interface, which is connected from the logic circuit to make the pinch plate give the global reset signal to the bottom plate; interfaces A18 and A19 are PCIE clock positive interface and PCIE clock negative interface, and are used for outputting a PCIE homologous clock from a CPU to a bottom plate, a pinch plate is in direct current coupling without capacitance, and HCSL level is adopted; the interfaces A22, A23, interfaces A26, A27, interfaces A30 and A31 are three groups of USB positive data interfaces and USB negative data interfaces, wherein the interfaces A22 and A23 are used for receiving USB2.0 signals, and the interfaces A26, A27, A30 and A31 are used for receiving USB3.0 signals; interfaces A34 and A35 are SATA positive electrode receiving interfaces and SATA negative electrode receiving interfaces and are used for receiving SATA signals; the interfaces A38, A39, interfaces A42, A43, interfaces A46, A47, interfaces A50 and A51 are 4 groups of PCIe positive pole receiving interfaces and PCIe negative pole receiving interfaces and are used for receiving PCIe signals; the interfaces A38 and A38 can also be used as an RP end and an RN end of a serial gigabit media independent interface, and the serial gigabit media independent interface is connected out of the PHY; the interfaces A54, A55, A58 and A59 are two groups of local area network receiving positive interfaces and local area network receiving negative interfaces;
the interfaces B1-B4 are power supply interfaces, each interface is connected with 12V input voltage, and the current of each pin is 0.5B; interfaces B5, B9, B14, B18, B19, B22, B23, B26, B27, B30, B31, B34, B35, B38, B39, B42, B43, B46, B47, B50, B51, B54, B55, B58, and B59 are power ground interfaces; interface B6 is SPI clock interface, interface B7 is SPI MOSI interface, interface B8 is SPI MISO interface, interfaces B10, B11, B12 are SPI chip select interfaces; interfaces B11, B12 may also be generic interfaces; interface B12 may also be used as a lan LED lamp data interface; b13 is a reset circuit direct current input interface, the bottom plate gives a buckle plate reset signal, and the buckle plate is pulled up by default; the interfaces B15 and B16 are MDC interfaces and MDIO interfaces, the MDC interfaces are connected from a local area network controller of the CPU and are used for managing a port physical layer PHY or a switch on a CPU local area network bus, or the interfaces B15 and B16 are local area network interfaces of the MDC and the MDIO, or the interfaces B15 and B16 are local area network interfaces of a data signal line SCL of an I2C bus and a data signal line SDA of an I2C bus; the interface B17 is PG signal enable interface, bottom plate power OK and pinch plate power-on enable signal; the interfaces B20, B21, B24, B25, B28 and B29 are three groups of USB positive data interfaces and USB negative data interfaces, wherein the interfaces B20 and B21 send USB2.0 signals, and the interfaces B24, B25, B28 and B29 send USB3.0 signals; interfaces B32 and B33 are SATA positive electrode sending interfaces and SATA negative electrode sending interfaces and are used for SATA signals; the interfaces B36, B37, interfaces B40, B41, interfaces B44, B45, interfaces B48 and B49 are 4 groups of PCIe positive interfaces and PCIe negative interfaces and are used for PCIe sending signals; the interfaces B36 and B37 can also be used as TP end and TN end of the serial gigabit media independent interface; the interfaces B52, B53, B56 and B57 are positive interfaces for LAN transmission and negative interfaces for LAN transmission.
2. The dual edge connector based COMe module of claim 1, wherein said dual edge connector further comprises a second dual edge connector comprising a second edge connector C and a second edge connector D; the second edge connector C comprises 60-bit interfaces C1-C60, and the second edge connector D comprises 60-bit interfaces D1-D60;
the interfaces C1-C5 are power supply interfaces, each interface is connected with 12V input voltage, and the current of each pin is 0.5A; interfaces C6, C10, C13, C16, C17, C20, C21, C24, C25, C28, C29, C32, C33, C36, C37, C40, C41, C44, C45, C48, C49, C52, C53, C56, C57 and C60 are power ground interfaces; the interface C7 is a BAT power supply interface and is used for supplying power to an RTC (real time clock) in the CPU, or the interface C7 is used as a general interface; interfaces C8 and C11 are local area network interfaces of MDC, or interfaces C8 and C11 are local area network interfaces of a data signal line SCL of an I2C bus, or interfaces C8 and C11 are universal interfaces; interfaces C9 and C12 are local area network interfaces of MDIO, or interfaces C9 and C12 are local area network interfaces of a data signal line SDA of an I2C bus, or interfaces C9 and C12 are universal interfaces; the interfaces C14 and C15 are a group of USB positive data interfaces and USB negative data interfaces and are used for receiving USB2.0 signals; interfaces C18 and C19 are SATA positive electrode receiving interfaces and SATA negative electrode receiving interfaces and are used for receiving SATA signals; the interfaces C22, C23, interfaces C26, C27, interfaces C30, C31, interfaces C34, C35, interfaces C38, C39, interfaces C42, C43, interfaces C46, C47, interfaces C50 and C51 are 8 sets of PCIe positive pole receiving interfaces and PCIe negative pole receiving interfaces and are used for receiving PCIe signals; the interfaces C54, C55, C58 and C59 are two groups of local area network receiving positive interfaces and local area network receiving negative interfaces;
the interfaces D1-D5 are power supply interfaces, each interface is connected with 12V input voltage, and the current of each pin is 0.5A; interfaces D6, D10, D14, D15, D18, D19, D22, D23, D26, D27, D30, D31, D34, D35, D38, D39, D42, D43, D46, D47, D50, D51, D54, D55, D58 and D59 are power supply ground interfaces; the interface D7 is an RSV interface, or D7 is used as a low device reset signal PLTRST interface of the CPU; the interfaces D8, D9, D11 and D12 are BMC serial peripheral interfaces which are respectively a BMC serial peripheral clock interface, a BMC serial peripheral chip selection signal interface, a BMC serial peripheral MISO interface and a BMC serial peripheral MOSI interface; the interface D13 is a power button interface, or D13 is used as a universal interface; the interfaces D16 and D17 are SATA positive electrode sending interfaces and SATA sending and receiving interfaces and are used for SATA signals; the interfaces D20, D21, interfaces D24, D25, interfaces D28, D29, interfaces D32, D33, interfaces D36, D37, interfaces D40, D41, interfaces D44, D45, interfaces D48 and D49 are 8 groups of PCIe positive interfaces and PCIe negative interfaces and are used for PCIe sending signals; the interfaces D52, D53, D56 and D57 are a local area network sending positive electrode interface and a local area network sending negative electrode interface; the interface D60 is an SUS clock interface used by an m.2 hard disk, or the interface D60 is a general-purpose interface.
3. The dual edge connector based COMe module of claim 2, wherein said dual edge connector further comprises a third dual edge connector comprising a third edge connector E and a third edge connector F; the third edge connector E comprises 60-bit interfaces E1-E60, and the third edge connector F comprises 60-bit interfaces F1-F60;
the interfaces E1-E7 are power supply interfaces, each interface is connected with 12V input voltage, and the current of each pin is 0.5A; interfaces E8, E9, E12, E16, E20, E21, E24, E25, E28, E29, E32, E33, E36, E37, E40, E41, E44, E45, E48, E49, E52, E53, E56, E57, E60 are power ground interfaces; interfaces E10 and E11 are serial peripheral interfaces of BMC upgrade bios, namely a serial peripheral MOSI interface of the BMC upgrade bios and a serial peripheral clock interface of the BMC upgrade bios, wherein the BMC is used as a master and the spifly is used as a slave; the interfaces E13 and E14 are a BMC data signal line SCL interface of the I2C bus and a BMC data signal line SDA interface of the I2C bus; the interface E15 is a BMC data signal line reminding interface of the I2C bus, or the interface E15 is used as a universal interface, or the interface E15 is used as a BMC input interface; the interface E17 is a SERIRQ serial interrupt interface of an LPC bus, the LPC bus is used for connecting a CPU and a CPLD, or the interface E17 is used as a chip selection signal interface of EPSI; the interface E18 is used as a reset interface of EPSI or a general interface; the interface E19 is used as a clock interface of an LPC bus or an EPSI; the interfaces E22, E23, E26 and E27 are RSV interfaces, or the interface E22 is used as a power supply interface of 1V 05; the interfaces E30, E31, interfaces E34, E35, interfaces E38, E39, interfaces E42, E43, interfaces E46, E47, interfaces E50, E51, interfaces E54, E55, interfaces E58 and E59 are 8 groups of SERDES receiving positive interfaces and SERDES receiving negative interfaces;
the interfaces F1-F7 are power supply interfaces, each interface is connected with 12V input voltage, and the current of each pin is 0.5A; interfaces F8, F9, F12, F19, F22, F23, F26, F27, F30, F31, F34, F35, F38, F39, F42, F43, F46, F47, F50, F51, F54, F55, F58, F59 are power ground interfaces; interfaces F10 and F11 are serial peripheral MISO interfaces of BMC upgrade bios and serial peripheral chip select signal interfaces of BMC upgrade bios, BMC is the master, spiflash is the slave; interfaces F13, F14, F15 and F16 are AD interfaces of LPC buses, or interfaces F13, F14, F15 and F16 are IO interfaces of ESPI; interface F17 is the data frame interface of LPC bus, or interface F17 is the chip selection interface of ESPI; the interface F18 is a universal interface of the BMC; the interfaces F20 and F21 are the ME interface of the CPU of the data signal line SCL of the I2C bus and the ME interface of the CPU of the data signal line SDA of the I2C bus; interfaces F24 and F25 are RSV interfaces; interfaces F28, F29, interfaces F32, F33, interfaces F36, F37, interfaces F40, F41, interfaces F44, F45, interfaces F48, F49, interfaces F52, F53, interfaces F56 and F57 are 8 groups of SERDES positive sending interfaces and SERDES negative sending interfaces; the interface F60 is a PECI interface, or the interface F60 is a general interface.
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