CN113641468B - Inter-board multi-operation chip computing force balance system applied to electric power instrument - Google Patents
Inter-board multi-operation chip computing force balance system applied to electric power instrument Download PDFInfo
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- CN113641468B CN113641468B CN202110698608.6A CN202110698608A CN113641468B CN 113641468 B CN113641468 B CN 113641468B CN 202110698608 A CN202110698608 A CN 202110698608A CN 113641468 B CN113641468 B CN 113641468B
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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Abstract
The invention discloses an inter-board multi-operation chip computing force balancing system applied to electric power instrument equipment, which is characterized by comprising an execution layer, a perception layer, a communication layer, a task scheduling layer and a control layer. The invention is applied to the application scene that a plurality of operation circuit boards exist in the system row of the electric power instrument, the operation task content of each operation circuit board has larger difference, and the calculation task content is allocated for overall under the application scene that the calculation force demand has larger difference, and the operation content executed in each operation chip is balanced so as to achieve the effects of balancing the calculation force of each operation circuit board and improving the overall operation efficiency of the system. Meanwhile, a series of low-performance operation chips can be replaced by high-performance operation chips required by the system architecture, so that the system cost is greatly reduced.
Description
Technical Field
The invention relates to the technical field of electric power instruments and equipment, in particular to an inter-board multi-operation chip calculation force balance system applied to electric power instruments and equipment.
Background
The chip calculation force among the plates of the existing electric power instrument is unevenly distributed, so that a program blocking phenomenon occurs in a part of operation circuit boards in the process of completing calculation tasks, and the part of operation circuit boards are in a long-term idle state, so that the overall cost of the system is greatly increased, and the overall running condition of the system is slowed down.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a multi-operation chip computing force balance system applied to the board of the electric instrument aiming at the defects existing in the prior art.
In order to achieve the above object, the present invention adopts the following technical scheme:
an inter-board multi-operation chip computing force balance system applied to electric power instrument equipment comprises an execution layer, a perception layer, a communication layer, a task scheduling layer and a control layer, wherein:
the execution layer is the bottommost layer, exists in each operation circuit board and each operation chip, and comprises a subdivision task execution module for receiving and executing subdivision tasks transmitted by the communication layer;
the sensing layer is the upper layer of the execution layer and comprises an inter-board computing power monitoring module, a task process monitoring module, an inter-board weight module and an intra-board weight module; the inter-board calculation power monitoring module monitors the current calculation power running conditions of the circuit boards so as to obtain that the circuit boards are in a full-load state or an idle state at present, and the task scheduling layer is convenient for calculation power balance; the task process monitoring module monitors each process on the circuit board to acquire the code position operated by the current process, acquires the current code position for the process needing to perform calculation force balance through the task process monitoring module, and balances the residual calculation content to other calculation circuit boards; the inter-board weight module and the intra-board weight module are used for task distribution and stable running of the main business program of the packet core and finish weight distribution of each circuit board through preset;
the communication layer is the upper layer of the perception layer and is used for communication of each layer;
the task scheduling layer is the upper layer of the communication layer and is composed of a subdivision task database, a task splitting module, a calculation force balancing module, a task issuing module and a task summarizing module, calculation force monitoring and task progress monitoring information of each calculation circuit board are uploaded to the calculation force balancing module through the communication layer by the perception layer, redundant calculation force information of each circuit board exists in the calculation force balancing module, and the calculation force balancing module analyzes the redundant calculation force information to acquire calculation chips needing to reduce calculation force and calculation chips needing to increase calculation force by taking calculation force balancing and calculation task completion of each on-board calculation chip as targets; for an operation chip needing to reduce the calculation force, transmitting task process information of the operation chip to a task splitting module, wherein the task splitting module breaks down follow-up algorithm steps into a series of function number groups through a subdivision task database according to task process positions, and transmits the function number groups to the operation chip needing to increase the calculation force through a task issuing module, and after the operation of the operation chip is completed, the operation chip transmits an operation structure back to a task summarizing module through a communication layer, and the task summarizing module transmits the summarized follow-up steps back to an original task operation chip after summarizing and splicing the follow-up steps;
the control layer is the upper layer of the task scheduling layer to control whether the system operates, set a calculation force balance target and short-circuit the weight modules among the plates under special conditions, and directly set certain calculation chips with higher importance not to participate in the calculation force balance work so as to ensure the stable operation of core business.
In a preferred embodiment of the present invention, the execution layer includes a task subdivision execution module that accepts subdivision tasks delivered by the communication layer and executes them.
In a preferred embodiment of the present invention, the task subdivision executing module accepts subdivision tasks transferred by the communication layer and executes the following operation processes: receiving subdivision task information transmitted by a communication module, wherein the subdivision task information is divided into three parts: the task subdivision execution module extracts corresponding functions from the subdivision task database according to the subdivision task function serial numbers after receiving the subdivision task information, transmits the corresponding functions into the subdivision task function to perform function operation, combines operation results into subdivision task result information, returns the subdivision task result information to the communication layer, and transmits the subdivision task result information back to the task scheduling layer through the communication layer.
In a preferred embodiment of the present invention, the subdivision task result information is composed of subdivision task ID numbers and subdivision task operation results.
In a preferred embodiment of the present invention, the inter-board computing power monitoring module monitors computing power of each computing chip on a board to obtain remaining computing power data of each computing chip, and obtains redundant computing power of each board according to a weight multiplier in an intra-board weight module; according to the weight multiplier in the weight module between boards, the final redundant computing force of each single book is obtained, the information is uploaded to a computing force balancing module for task allocation execution, and the computing formula of the redundant computing force is as follows:
Sremain＝(ΣSavailable*l1)*l2
wherein Sremail is the final redundant calculation power, savailable is the residual calculation power of each chip, l1 is the weight value of each chip in the weight module in the board, the redundant calculation power of a single board is obtained through (Sigma Savailable) calculation, and l2 is the weight value of each single board in the weight module between boards; and obtaining the data of the internal redundant calculation force of the final system through the calculation.
In a preferred embodiment of the present invention, the redundant power information is power information that ensures that the system stability core service logic is not affected after the weight operation is completed.
Due to the adoption of the technical scheme, the system is applied to the application scene that a plurality of operation circuit boards exist in a system row of the electric instrument, the operation task content of each operation circuit board has larger difference, and the calculation force demand has larger difference, so that the task content is allocated for overall planning, the operation content executed in each operation chip is balanced, and the effects of balancing the calculation force of each operation circuit board and improving the overall operation efficiency of the system are achieved. Meanwhile, a series of low-performance operation chips can be replaced by high-performance operation chips required by the system architecture, so that the system cost is greatly reduced.
Drawings
Fig. 1 is a schematic diagram of an architecture of an inter-board multi-operation chip power balance system applied to an electrical instrument.
Detailed Description
The invention is further described below with reference to the drawings and detailed description.
The invention is applied to an inter-board multi-operation chip power balance system of electric power instrument equipment, and is mainly used in an application scene that a plurality of operation circuit boards exist on the system of the electric power instrument equipment, the operation task content of each operation circuit board has larger difference, and the power demand has larger difference.
The main function of the inter-board multi-operation chip computing force balancing system applied to the electric power instrument equipment is to comprehensively allocate task contents, and the operation contents executed in each operation chip are balanced so as to achieve the effects of balancing the computing force of each operation circuit board and improving the overall operation efficiency of the system. Meanwhile, the high-performance operation chip required by the system architecture can be replaced by a series of low-performance operation chips, so that the system cost is greatly reduced.
The structure diagram of the power balance system of the multi-operation chip between boards, which is applied to electric power instrument equipment, is shown in figure 1.
Before the invention is applied to the inter-board multi-operation chip power balance system of the electric power instrument, for each operation task running on each circuit board, the repeated function is placed into a subdivision task database after numbering is completed, and the numbering process result is divided into two parts: subdivision function sequence number, and specific code segment. The subdivision task database 41 in the task scheduling layer 40 exists in all the operation circuit boards in the inter-board multi-operation chip computing force balance system applied to the electric power instrument and equipment. For the repeated code segments, after the repeated code segments are packaged as functions, the above steps are stored in the subdivision task database 41.
The bottom-most layer is the executive layer 10. The execution layer 10 is mainly located in each arithmetic circuit board and also in each arithmetic chip, and the execution layer 10 mainly includes a subdivision task execution module 11, and the main task is to accept and execute subdivision tasks transferred by the communication module 21 in the communication layer 20. The operation process is as follows: the subdivided task information transmitted from the communication module 21 is received, and the subdivided task information is mainly composed of three parts: a subdivision task ID number, a subdivision task function sequence number, and a subdivision task parameter.
After receiving the above-mentioned subdivision task information, the subdivision task execution module 11 extracts a corresponding function from the subdivision task database 41 according to the subdivision task function sequence number, and transmits the function to the subdivision task parameter for performing a function operation. The calculation result is combined into subdivided task result information, which is returned to the communication module 31, and is transmitted back to the task scheduling layer 40 through the communication module 31. The subdivision task result information mainly comprises two parts, namely a subdivision task ID number and a subdivision task operation result.
The upper layer is the sense layer 20. The perception layer 20 mainly comprises an inter-board computing power monitoring module 21, a task progress monitoring module 22, an inter-board weight module 23 and an intra-board weight module 24. The inter-board power calculation monitoring module 21 mainly monitors the current power calculation operation condition of each circuit board, so as to learn that the circuit boards are currently in a full-load state or an idle state, and facilitate the power calculation balance of the task scheduling layer 40.
The task process monitoring module 22 mainly monitors each process on the circuit board to obtain the code position to which the current process operates. For the process requiring the calculation force balancing, the task process monitoring module 22 can balance the residual calculation content to other calculation circuit boards through the current code position.
The inter-board weight module 23 is mainly used for task allocation and stable operation of the main service program of the protection core, and is mainly used for completing weight allocation of each circuit board through preset. For a circuit board executing core business logic or important logic, the method can keep a larger computational redundancy and communication redundancy by reducing the weight of the additional computation task so as to ensure that the core logic is not influenced by the distributed computation task issued by the outside and ensure the stable operation of the core business logic. The intra-plate weight module 24 is vice versa.
The inter-board calculation force monitoring module 21 monitors the calculation force of each chip on the single board to obtain the remaining calculation force data of each chip, and meanwhile, obtains the redundant calculation force of each single board according to the weight multiplier in the weight module 24 in the board. The final redundant computation for each veneer is obtained from the weight multiplier in the inter-board weight module 24. And uploading the information to a calculation force balance module for task allocation execution.
The calculation formula of the redundancy calculation force is Sremail= (ΣSavailable 1) l2
Wherein sremail is the final redundant computing power, savailable is the residual computing power of each chip, l1 is the weight value of each chip in the weight module in the board, the redundant computing power of the single board is obtained through (Σsavailable x l 1) calculation, and l2 is the weight value of each single board in the weight module between boards. And obtaining the data of the internal redundant calculation force of the final system through the calculation.
The task scheduling layer 40 is the most core subdivision level of the system. The system mainly comprises five parts, namely a subdivision task database 41, a task splitting module 42, a calculation force balancing module 43, a task issuing module 44 and a task summarizing module 45. The calculation power monitoring and task process monitoring information of the sensing layer on each calculation circuit board is uploaded to the calculation power balancing module 43 through the communication module 21, and redundant calculation power information of each circuit board exists in the calculation power balancing module 43 (after weight calculation is completed, calculation power information that the stable operation core business logic of the system is not affected can be ensured). The calculation force balancing module 43 analyzes the information, and thereby obtains the calculation chip requiring a reduction in calculation force and the calculation chip requiring an increase in calculation force, with the objective of calculation force balancing and completion of calculation tasks of each chip on board. For the operation chip with the calculation force needing to be reduced, the task process information of the chip is forwarded to the task splitting module 42, and the task splitting module 42 splits the subsequent algorithm steps into a series of function number arrays through the subdivision task database 41 according to the task process positions. And transmitted to the operation chip needing to increase the calculation force through the task issuing module 44. After the operation is completed, the operation chip transmits the operation result back to the task summarizing module 45 through the communication module 31 of the communication layer 30, and the task summarizing module 45 transmits the summarized and spliced subsequent steps back to the original task operation chip.
The control layer 50 is mainly composed of a main control module 51. The main task of the main control module 51 is to control whether the system is running, set a calculation force balance target, and in special cases, directly set a weight module 23 between short circuit boards, and some chips with higher importance are not involved in the calculation force balance work so as to ensure the stable running of the core business logic.
Claims (6)
1. The power balance system of the multi-operation chip between boards applied to the electric power instrument equipment is characterized by comprising an execution layer, a perception layer, a communication layer, a task scheduling layer and a control layer, wherein:
the execution layer is the bottommost layer, exists in each operation circuit board and each operation chip, and comprises a subdivision task execution module for receiving and executing subdivision tasks transmitted by the communication layer;
the sensing layer is the upper layer of the execution layer and comprises an inter-board computing power monitoring module, a task process monitoring module, an inter-board weight module and an intra-board weight module; the inter-board calculation power monitoring module monitors the current calculation power running conditions of the circuit boards so as to obtain that the circuit boards are in a full-load state or an idle state at present, and the task scheduling layer is convenient for calculation power balance; the task process monitoring module monitors each process on the circuit board to acquire the code position operated by the current process, acquires the current code position for the process needing to perform calculation force balance through the task process monitoring module, and balances the residual calculation content to other calculation circuit boards; the inter-board weight module and the intra-board weight module are used for task distribution and stable running of the main business program of the packet core and finish weight distribution of each circuit board through preset;
the communication layer is the upper layer of the perception layer and is used for communication of each layer;
the task scheduling layer is the upper layer of the communication layer and is composed of a subdivision task database, a task splitting module, a calculation force balancing module, a task issuing module and a task summarizing module, calculation force monitoring and task progress monitoring information of each calculation circuit board are uploaded to the calculation force balancing module through the communication layer by the perception layer, redundant calculation force information of each circuit board exists in the calculation force balancing module, and the calculation force balancing module analyzes the redundant calculation force information to acquire calculation chips needing to reduce calculation force and calculation chips needing to increase calculation force by taking calculation force balancing and calculation task completion of each on-board calculation chip as targets; for an operation chip needing to reduce the calculation force, transmitting task process information of the operation chip to a task splitting module, wherein the task splitting module breaks down follow-up algorithm steps into a series of function number groups through a subdivision task database according to task process positions, and transmits the function number groups to the operation chip needing to increase the calculation force through a task issuing module, and after the operation of the operation chip is completed, the operation chip transmits an operation structure back to a task summarizing module through a communication layer, and the task summarizing module transmits the summarized follow-up steps back to an original task operation chip after summarizing and splicing the follow-up steps;
the control layer is the upper layer of the task scheduling layer to control whether the system operates, set a calculation force balance target and short-circuit the weight modules among the plates under special conditions, and directly set certain calculation chips with higher importance not to participate in the calculation force balance work so as to ensure the stable operation of core business.
2. The system of claim 1, wherein the execution layer comprises a task segment execution module that accepts segment tasks delivered by the communication layer and executes the segment tasks.
3. The system of claim 2, wherein the task subdivision execution module accepts subdivision tasks transferred by the communication layer and executes the following operation processes: receiving subdivision task information transmitted by a communication module, wherein the subdivision task information is divided into three parts: the task subdivision execution module extracts corresponding functions from the subdivision task database according to the subdivision task function serial numbers after receiving the subdivision task information, transmits the corresponding functions into the subdivision task function to perform function operation, combines operation results into subdivision task result information, returns the subdivision task result information to the communication layer, and transmits the subdivision task result information back to the task scheduling layer through the communication layer.
4. The system for balancing forces of multiple operation chips among boards applied to electric power equipment according to claim 3, wherein the information of the result of the subdivision task consists of an ID number of the subdivision task and an operation result of the subdivision task.
5. The system for balancing the computational power of multiple computing chips among boards applied to electric power instrument equipment according to claim 4, wherein the computational power monitoring module monitors the computational power of each computing chip on a single board to obtain the residual computational power data of each computing chip, and simultaneously obtains the redundant computational power of each single board according to the weight multiplier in the weight module in the board; according to the weight multiplier in the weight module between boards, the final redundant computing force of each single book is obtained, the information is uploaded to a computing force balancing module for task allocation execution, and the computing formula of the redundant computing force is as follows:
Sremain＝(ΣSavailable*l1)*l2
wherein Sremail is the final redundant calculation power, savailable is the residual calculation power of each chip, l1 is the weight value of each chip in the weight module in the board, the redundant calculation power of a single board is obtained through (Sigma Savailable) calculation, and l2 is the weight value of each single board in the weight module between boards; and obtaining the data of the internal redundant calculation force of the final system through the calculation.
6. The system of claim 5, wherein the redundant computing power information is computing power information which can ensure that the system stability core business logic is not affected after the weight operation is completed.
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