CN113641266A

CN113641266A - Touch display panel and touch display device

Info

Publication number: CN113641266A
Application number: CN202110938796.5A
Authority: CN
Inventors: 陈旭
Original assignee: Nanjing Boe Display Technology Co ltd; BOE Technology Group Co Ltd
Current assignee: Nanjing Boe Display Technology Co ltd; BOE Technology Group Co Ltd
Priority date: 2021-08-16
Filing date: 2021-08-16
Publication date: 2021-11-12

Abstract

The disclosure provides a display panel and a display device, and belongs to the technical field of display. The touch display panel of the present disclosure includes: a gate driving circuit and N gate lines; the gate driving circuit includes: n first shift registers and at least one group of second shift registers; each group of second shift registers includes: k second shift registers; any group of second shift registers is arranged between the nth first shift register and the (n + 1) th first shift register; the signal output end of the ith first shift register is connected with the signal input end of the (i + 1) th first shift register and the ith grid line; the signal output end of the kth second shift register is connected with the signal input end of the (k + 1) th second shift register; the signal input end of the 1 st second shift register is connected with the signal output end of the nth first shift register; and the signal output end of the Kth second shift register is connected with the signal input end of the (n + 1) th first shift register.

Description

Touch display panel and touch display device

Technical Field

The disclosure belongs to the technical field of display, and particularly relates to a touch display panel and a touch display device.

Background

With the continuous development of the display industry, liquid crystal display products have attracted more attention due to their advantages of low cost, narrow frame, light weight, and the like, and Gate Driver on Array (GOA) technology has come to work under this background. The GOA technology is that a grid driving circuit and a thin film transistor array are manufactured on an array substrate together, and pixel units are started line by line through a plurality of cascaded shift registers, so that a display product displays colorful pictures. Meanwhile, Touch operation is a friendly man-machine interface, and has developed at a remarkable speed in recent years, wherein Touch and Display Driver Integration (TDDI) is becoming a mainstream direction, and the TDDI can integrate Display function and Touch function on one chip, and the chip generally supports the driving of the GOA circuit.

Currently, in order to improve the touch sensitivity, TDDI generally inserts a touch signal for multiple times during the display time of a frame of a picture, and needs multiple pit stopping, which interrupts normal display, wherein several stages of shift registers store charges to pass through pits, which may cause the threshold voltage Vth of the thin film transistors in some shift registers to drift forward, and when the picture is displayed, the scanning signals generated by these shift registers and the scanning signals generated by other shift registers have a certain difference, which causes the occurrence of pit stopping and affecting the display effect.

Disclosure of Invention

The present disclosure is directed to at least one of the technical problems in the prior art, and provides a touch display panel and a touch display device.

In a first aspect, an embodiment of the present disclosure provides a touch display panel, including: a gate driving circuit and N gate lines; the gate driving circuit includes: n first shift registers and at least one group of second shift registers; each group of second shift registers includes: k second shift registers; any group of second shift registers is arranged between the nth first shift register and the (n + 1) th first shift register; n and K are integers which are more than or equal to 2, and N is an integer which is less than N;

the signal output end of the ith first shift register is connected with the signal input end of the (i + 1) th first shift register and the ith grid line; i is an integer less than n or greater than n + 1;

the signal output end of the kth second shift register is connected with the signal input end of the (k + 1) th second shift register; k is an integer less than K; the signal input end of the 1 st second shift register is connected with the signal output end of the nth first shift register; and the signal output end of the Kth second shift register is connected with the signal input end of the (n + 1) th first shift register.

Optionally, the gate driving circuit further includes: m first clock signal lines; m is an even number less than or equal to N and K;

every adjacent M first shift registers in the N first shift registers are respectively connected with M first clock signal lines;

every adjacent M second shift registers in the K second shift registers are respectively connected with M first clock signal lines.

Optionally, the first shift register and the second shift register each have a first clock signal terminal and a second clock signal terminal;

the first clock signal end of the first shift register is connected with the mth first clock signal line, and the second clock signal end of the first shift register is connected with the (m-1) th first clock signal line;

the first clock signal end of the second shift register is connected with the jth first clock signal line, and the second clock signal end is connected with the (j-1) th first clock signal line; m and j are each an integer less than or equal to M.

Optionally, the gate driving circuit further includes: m first clock signal lines and M second clock signal lines; m is an even number less than or equal to N and K;

every adjacent M second shift registers in the K second shift registers are respectively connected with the M second clock signal lines and the M second clock signal lines.

the first clock signal end of the second shift register is connected with the jth second clock signal line, and the second clock signal end is connected with the pth first clock signal line; m, j and p are integers less than or equal to M.

Optionally, during a period from when the signal output terminal of the nth first shift register outputs the scan signal to when the signal output terminal of the (n + 1) th first shift register outputs the scan signal, the absolute value of the voltage of the clock signal transmitted by the second clock signal line is equal to the absolute value of the voltage of the clock signal transmitted by the first clock signal line.

Optionally, the absolute value of the voltage of the clock signal transmitted by the second clock signal line is greater than the absolute value of the voltage of the clock signal transmitted by the second clock signal line except the time from the start of outputting the scan signal by the signal output terminal of the nth first shift register to the end of outputting the scan signal by the signal output terminal of the (n + 1) th first shift register.

Optionally, the first shift register and the second shift register each include: the circuit comprises an input sub-circuit, an output sub-circuit, a pull-down control sub-circuit, a pull-down sub-circuit, a first noise reduction sub-circuit and a second noise reduction sub-circuit;

the input sub-circuit is configured to write an input signal of the signal input terminal into the pull-up node in response to a clock signal input from the second clock signal terminal;

the output sub-circuit is configured to output a clock signal input from a first clock signal terminal through a signal output terminal in response to a potential of the pull-up node;

the pull-down control sub-circuit is configured to control a potential of the pull-down node by a first power supply voltage in response to the first power supply voltage input from the first power supply voltage terminal;

the pull-down sub-circuit is configured to pull down a potential of the pull-down node by a second power supply voltage in response to a potential of the pull-up node;

the first noise reduction sub-circuit is configured to reduce noise of a pull-up node by a second power supply voltage in response to a potential of the pull-down node;

the second noise reduction sub-circuit is configured to reduce noise of the signal output terminal by a second power supply voltage in response to a potential of the pull-down node.

Optionally, the input sub-circuit comprises: a first transistor; the output sub-circuit includes: a second transistor and a storage capacitor; the pull-down control sub-circuit includes: a third transistor; the pull-down sub-circuit comprises: a fourth transistor; the first noise reduction sub-circuit comprises: a fifth transistor; the second noise reduction sub-circuit comprises: a sixth transistor;

the grid electrode of the first transistor is connected with a second clock signal end, the first pole of the first transistor is connected with the signal input end, and the second pole of the first transistor is connected with a pull-up node;

the grid electrode of the second transistor is connected with the pull-up node, the first pole of the second transistor is connected with the first clock signal end, and the second pole of the second transistor is connected with the signal output end;

one end of the storage capacitor is connected with the pull-up node, and the other end of the storage capacitor is connected with the signal output end;

the grid electrode and the first electrode of the third transistor are both connected with a first power supply voltage end, and the second electrode of the third transistor is connected with a pull-down node;

the grid electrode of the fourth transistor is connected with the pull-up node, the first pole of the fourth transistor is connected with the second power voltage end, and the second pole of the fourth transistor is connected with the pull-down node;

a grid electrode of the fifth transistor is connected with the pull-down node, a first pole of the fifth transistor is connected with a second power supply voltage end, and a second pole of the fifth transistor is connected with the pull-up node;

and the grid electrode of the sixth transistor is connected with the pull-down node, the first pole of the sixth transistor is connected with the second power supply voltage end, and the second pole of the sixth transistor is connected with the signal output end.

In a second aspect, an embodiment of the present disclosure provides a touch display device, which includes the touch display panel described above.

Drawings

FIG. 1 is a schematic diagram of an exemplary shift register structure;

FIG. 2 is a schematic diagram of an exemplary gate driver circuit;

FIG. 3 is a timing diagram of signals in the gate driving circuit shown in FIG. 2;

fig. 4 is a state diagram of the second transistor M2 in the gate driving circuit shown in fig. 2;

fig. 5 is a schematic diagram of a gate driving circuit of a touch display panel according to an embodiment of the disclosure;

FIG. 6 is a timing diagram of signals in the gate driving circuit shown in FIG. 5;

fig. 7 is a schematic diagram of another gate driving circuit of a touch display panel according to an embodiment of the disclosure;

FIG. 8 is a timing diagram of signals in the gate driving circuit shown in FIG. 7;

fig. 9 is a state diagram of the second transistor M2 in the gate driving circuit shown in fig. 7.

Detailed Description

For a better understanding of the technical aspects of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics, and since the source and the drain of the transistors used are symmetrical, there is no difference between the source and the drain. In the embodiments of the present disclosure, to distinguish the source and the drain of the transistor, one of the poles is referred to as a first pole, and the other pole is referred to as a second pole. In addition, the transistors can be divided into N-type and P-type according to the characteristics of the transistors, and in the following embodiments, the N-type transistors are used for explanation, when the N-type transistors are used, the first electrode is the source electrode of the N-type transistor, the second electrode is the drain electrode of the N-type transistor, and when the gate electrode inputs a high level, the source electrode and the drain electrode are conducted, and the P-type is opposite. It is contemplated that implementation with P-type transistors will be readily apparent to those skilled in the art without inventive effort and, thus, are within the scope of the disclosed embodiments.

In the embodiment of the present disclosure, since the transistor is an N-type transistor, the working level signal in the embodiment of the present disclosure refers to a high level signal, and the non-working level signal refers to a low level signal.

Generally, a touch display panel includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines are arranged in a crossing manner to define a plurality of pixel regions, and each pixel region is provided with a pixel unit. The structure of the touch display panel will be described by taking the extending direction of each gate line as a row direction and the extending direction of each data line as a column direction as an example. When the touch display panel is driven to display, according to a picture to be displayed, a grid scanning signal can be written into the grid lines line by line, and a data voltage signal can be written into each data line simultaneously, so that pixel units in the touch display panel are lightened line by line.

The grid scanning signal is provided by a grid driving circuit, and the data voltage signal is provided by a source driving circuit; in the related art, the gate driving circuit may be integrated in the gate driving chip, and the source driving circuit may be integrated in the source driving chip; at present, in order to reduce the number of chips and realize narrow frames or no frames, a technology of integrating a Gate driving circuit On an Array substrate (Gate On Array; GOA) is provided; the grid driving circuit comprises a plurality of cascaded shift registers which are integrated on the array substrate, and each shift register is connected with the grid line in a one-to-one correspondence mode and used for providing scanning signals for the grid lines connected with the shift registers.

In order to more clearly describe how the gate driving circuit realizes the output of the scan signal, the following description is made in conjunction with a specific structural example of one shift register in the gate driving circuit.

Fig. 1 is a schematic structural diagram of an exemplary shift register, as shown in fig. 1, the shift register includes: an input sub-circuit 101, an output sub-circuit 102, a pull-down control sub-circuit 103, a pull-down sub-circuit 104, a first noise reduction sub-circuit 105, and a second noise reduction sub-circuit 106; the INPUT sub-circuit 101 is configured to write the INPUT signal of the signal INPUT terminal INPUT into the pull-up node PU in response to the clock signal INPUT from the second clock signal terminal CKm-1; the OUTPUT sub-circuit 102 is configured to OUTPUT the clock signal input from the first clock signal terminal CKm through the signal OUTPUT terminal OUTPUT in response to the potential of the pull-up node PU; the pull-down control sub-circuit 103 is configured to control the potential of the pull-down node PD by a first power supply voltage in response to the first power supply voltage input from the first power supply voltage terminal VDD; the pull-down sub-circuit 104 is configured to pull down the potential of the pull-down node PD by the second power supply voltage in response to the potential of the pull-up node PU; the first noise reduction sub-circuit 105 is configured to reduce noise of the pull-up node PU by the second power supply voltage in response to the potential of the pull-down node PD; the second noise reduction sub-circuit 106 is configured to reduce noise of the signal OUTPUT terminal OUTPUT by the second power supply voltage in response to the potential of the pull-down node PD.

Specifically, the input sub-circuit 101 includes: a first transistor M1; the output sub-circuit 102 includes: a second transistor M2 and a storage capacitor C; the pull-down control sub-circuit 103 includes: a third transistor M3; the pull-down sub-circuit 104 includes: a fourth transistor M4; the first noise reduction sub-circuit 105 includes: a fifth transistor M5; the second noise reduction sub-circuit 106 includes: a sixth transistor M6; the gate of the first transistor M is connected to the second clock signal terminal CKm-1, the source is connected to the signal INPUT terminal INPUT, and the second pole is connected to the pull-up node PU; the gate of the second transistor M2 is connected to the pull-up node PU, the source is connected to the first clock signal terminal CKm, and the drain is connected to the signal OUTPUT terminal OUTPUT; one end of the storage capacitor C is connected with the pull-up node PU, and the other end of the storage capacitor C is connected with the signal OUTPUT end OUTPUT; the gate and the source of the third transistor M3 are both connected to the first power voltage terminal VDD, and the drain is connected to the pull-down node PD; the gate of the fourth transistor M4 is connected to the pull-down node PU, the source is connected to the second power supply voltage terminal VSS, and the drain is connected to the pull-down node PU; the gate of the fifth transistor M5 is connected to the pull-down node PD, the source is connected to the second power supply voltage terminal VSS, and the drain is connected to the pull-up node PU; the sixth transistor M6 has a gate connected to the pull-down node PD, a source connected to the second power supply voltage terminal VSS, and a drain connected to the signal OUTPUT terminal OUTPUT.

In the INPUT stage, the second clock signal terminal CKm-1 INPUTs a high level signal, and the signal INPUT terminal INPUT writes a high level signal, and the first transistor M1 is turned on, so that the high level signal INPUT by the signal INPUT terminal INPUT is INPUT to the pull-up node PU, and the potential of the pull-up node PU is pulled up by the high level signal, and the storage capacitor C is charged.

In the OUTPUT stage, since the potential of the pull-up node PU is pulled up in the input stage, the second transistor M2 is turned on, and a high level signal input from the first clock signal terminal CKm is OUTPUT through the signal OUTPUT terminal OUTPUT.

In the noise reduction stage, when the potential of the pull-up node PU is at a high level, the fourth transistor M4 is turned on, and at this time, a low-level signal input from the second power voltage terminal VSS may be written into the pull-down node PD, so that the potential of the pull-down node PD maintains a low level. When the high level signal is input from the first power voltage terminal VDD, the third transistor M3 is turned on, the high level signal input from the first power voltage terminal VDD is written into the pull-down node PD, so that the potential of the pull-down node PD is pulled up, at this time, the fifth transistor M5 and the sixth transistor M6 are turned on, and the potentials of the pull-up node PU and the signal input terminal OUTPUT are reduced by the low level signal input from the second power voltage terminal VSS.

Fig. 2 is a schematic structural diagram of an exemplary gate driving circuit, as shown in fig. 2, the gate driving circuit includes N cascaded shift registers shown in fig. 1, where N is an integer greater than or equal to 2, a signal OUTPUT terminal OUTPUT of an ith shift register is connected to a signal INPUT terminal INPUT of an i +1 th shift register and an ith gate line in a touch display panel, and i is an integer less than N. The grid driving circuit further comprises M clock signal lines, and every adjacent M shift registers in the N shift registers are respectively connected with the M clock signal lines. Specifically, the shift register has a first clock signal terminal CKm and a second clock signal terminal CKm-1, wherein the first clock signal terminal CKm is connected to the mth clock signal line, and the second clock signal terminal CKm-1 is connected to the m-1 clock signal line. Each clock signal line can provide a clock signal for each cascaded shift register to realize a register function, so that scanning signals are input to grid lines in the touch display panel line by line. In the embodiment of the present disclosure, the number of clock signal lines is 4, and the detailed description will be given in conjunction with the timing diagram of signals in the gate driving circuit. Each of the clock signal lines may be denoted by CK1, CK2, CK3, and CK 4.

Fig. 3 is a timing diagram of signals in the gate driving circuit shown in fig. 2, and as shown in fig. 3, a pit stop time is inserted in the timing diagram, and the following analysis is performed in time nodes:

at time t0, the signal OUTPUT terminal OUTPUT of the n-3 th shift register is at a high level (not shown in the figure), and for the n-2 th shift register, the gate of the first transistor M1 connected to the 2 nd clock signal line CK2 is at a high level at this moment, and the source of the first transistor M1 connected to the signal OUTPUT terminal OUTPUT of the n-3 th shift register is also at a high level at this moment, so that the pull-up node PU of the n-2 shift register is pulled up from a low level to a high level, at this time, the second transistor M2 is in an on state, but at this time, the source of the second transistor M2 connected to the 3 rd clock signal line CK3, at this time, the 3 rd clock signal line CK3 is at a low level, so that the signal OUTPUT terminal OUTPUT of the n-2 th shift register still OUTPUTs a low level signal.

At time t1, the 3 rd clock signal line CK3 changes from low level to high level, and at this time, the second transistor M2 of the n-2 th shift register is still turned on, so that the signal OUTPUT terminal OUTPUT changes from low level to high level, and at the same time, the potential of the pull-up node PU of the n-1 th shift register is pulled up, so that the potential of the pull-up node PU of the n-1 th shift register is high level, and the second transistor M2 is turned on, but at this time, the signal OUTPUT terminal OUTPUT is also low level. It is to be noted that, for the n-2 th shift register, since the storage capacitor C stores a certain charge at the high level at the time t0, and the signal OUTPUT terminal OUTPUT changes from the low level to the high level at the time t1, which is equivalent to the lower plate potential of the storage capacitor C rising, the potential of the upper plate of the storage capacitor C, i.e. the pull-up node PU, is higher than that at the time t0, which is the bootstrap effect in the GOA circuit.

At time t2, the 4 th clock signal line CK4 changes from low to high, the signal OUTPUT terminal OUTPUT of the n-1 th shift register OUTPUTs high, and the potential of the pull-up node PU of the n-th shift register is pulled up to high, and at this time, it is worth noting that, for the n-2 th shift register, since the signal OUTPUT terminal OUTPUT of the lower plate of the storage capacitor C changes from high to low, the potential of the pull-up node PU, which is the upper plate of the storage capacitor C, decreases accordingly, and decreases to about the magnitude of the potential of the pull-up node PU at time P at time t0, but still stays at high.

At time t3, the 1 st clock signal line CK1 changes from low to high, the signal OUTPUT terminal OUTPUT of the nth shift register OUTPUTs high, and the potential of the pull-up node PU of the (n + 1) th shift register is pulled up to high.

At time t4, the 2 nd clock signal line CK2 changes from low level to high level, the signal OUTPUT terminal OUTPUT of the n +1 th shift register OUTPUTs high level, and the potential of the pull-up node PU of the n +2 th shift register is pulled up to high level.

It should be noted that, for the n-2 shift register, the gate of the first transistor M1 is connected to the 2 nd clock signal line CK2, at this moment, the 2 nd clock signal line CK2 is at a high level, the source of the first transistor M1 is connected to the signal OUTPUT terminal OUTPUT of the n-3 shift register, and at this moment, a low level (not shown) is OUTPUT, so that the potential of the pull-up node PU of the n-2 shift register is pulled down from the high level to the low level, and the second transistor M2 is in a turned-off state.

And then entering pit stopping time, enabling the GOA circuit to be in a pause state, and enabling the touch circuit to start working to collect touch signals. As shown in fig. 3, the pull-up node PU in the four shift registers, i.e., the (n-1) th shift register, the (n + 1) th shift register, and the (n + 2) th shift register, stores a certain charge, is still at a high level, and then enters the pit stop process, rather than passing through the pit with a low level as in most shift registers, e.g., the pull-up node PU node such as the (n-2) th shift register and the (n-3) th shift register.

At time t5, the 3 rd clock signal line CK3 is at a high level, the signal OUTPUT terminal OUTPUT of the n +2 th shift register OUTPUTs a high level, the potential of the pull-up node PU of the n +3 th shift register is pulled up to a high level, the pull-up node PU of the n-1 th shift register is pulled down to a low level, and the second transistor M2 is turned off.

At time t6, the 4 th clock signal line CK4 is at a high level, the signal OUTPUT terminal OUTPUT of the n +3 th shift register OUTPUTs a high level, the potential of the pull-up node PU of the n +4 th shift register is pulled up to a high level (not shown), and the pull-up node PU of the nth shift register is pulled down to a low level.

At time t7, the 1 st clock signal line CK1 is at a high level, the signal OUTPUT terminal OUTPUT of the (n + 4) th shift register OUTPUTs a high level (not shown), and the pull-up node PU of the (n + 1) th shift register is pulled down to a low level.

At time t8, the 2 nd clock signal line CK2 is high, and the pull-up node PU of the (n + 2) th shift register is pulled down to low.

At time t9, the 3 rd clock signal line CK3 is high, and the pull-up node PU of the (n + 3) th shift register is pulled down to low.

Fig. 4 is a schematic diagram illustrating a state of the second transistor M2 in the shift register shown in fig. 1, as shown in fig. 4, in the stop pit, all the clock signals in each clock signal line are set to low level, and the signals of the first power voltage terminal VDD and the second power voltage terminal VSS are kept in normal operation, i.e. they are still at constant voltage dc high voltage and constant voltage dc low voltage, respectively. When the second transistor M2 in the 4 shift registers storing the charge passing through the pits is analyzed, the gate potential of the second transistor M2 is at a high level when the pits are stopped, the clock signal connected to the source is at a low level when the pits are stopped, and the drain outputs the clock signal at a low level because the second transistor M2 is in an on state, so that the second transistor M2 is subjected to a positive stress, which causes the threshold voltage Vth of the second transistor M2 to drift forward. For most shift registers, the potential of the pull-up node PU is at a low level and the source clock signal is at a low level when the shift register crosses the pit, and meanwhile, since the potential of the pull-up node PU is at a low level, the fourth transistor M4 is in an off state and the fifth transistor M5 and the sixth transistor M6 are in an on state, the signal OUTPUT terminal OUTPUT, i.e., the drain of the second transistor M2, can also be at a low level. Thus, the source, drain and gate of the second transistor M2 are all in a low state, no stress is applied, and the threshold voltage Vth of the second transistor M2 does not drift. If there are several shift registers storing charges for a long time, the threshold voltage Vth of the second transistor M2 may be different from those of other shift registers, resulting in a difference in the generated scanning signals, which may easily cause a horizontal stripe, i.e., a stop pit stripe, to be formed in the display area of the touch display panel.

In order to solve at least one of the above technical problems, embodiments of the present disclosure provide a touch display panel and a display device, which will be described in further detail with reference to the accompanying drawings and detailed description.

Fig. 5 is a schematic diagram of a gate driving circuit of a touch display panel according to an embodiment of the disclosure, and as shown in fig. 5, the gate driving circuit includes: n first shift registers and at least one group of second shift registers; each group of second shift registers includes: k second shift registers; any group of second shift registers is arranged between the nth first shift register and the (n + 1) th first shift register; n and K are integers which are more than or equal to 2, and N is an integer which is less than N; the signal OUTPUT end OUTPUT of the ith first shift register is connected with the signal INPUT end INPUT of the (i + 1) th first shift register and the ith grid line; i is an integer less than n or greater than n + 1; the signal OUTPUT end OUTPUT of the kth second shift register is connected with the signal INPUT end INPUT of the (k + 1) th second shift register; k is an integer less than K; the signal INPUT end INPUT of the 1 st second shift register is connected with the signal OUTPUT end OUTPUT of the nth first shift register; and the signal OUTPUT end OUTPUT of the Kth second shift register is connected with the signal INPUT end INPUT of the (n + 1) th first shift register. The gate driving circuit further includes: m first clock signal lines; m is an even number less than or equal to N and K; every adjacent M first shift registers in the N first shift registers are respectively connected with M first clock signal lines; every adjacent M second shift registers in the K second shift registers are respectively connected with M first clock signal lines. Specifically, the first shift register and the second shift register each have a first clock signal terminal CKm and a second clock signal terminal CKm-1; the first clock signal end of the first shift register is connected with the mth first clock signal line, and the second clock signal end of the first shift register is connected with the (m-1) th first clock signal line; the first clock signal terminal CKm of the second shift register is connected to the j-th first clock signal line, and the second clock signal terminal CKm-1 is connected to the j-1-th first clock signal line; m and j are each an integer less than or equal to M.

It should be noted that, in the embodiment of the present disclosure, the number of the first clock signal lines is taken as an example to be 4, and the number of the corresponding second shift registers is also 4, where the first clock signal lines may be represented by CK1, CK2, CK3, and CK4 as the same as the clock signals shown in fig. 1, in order to distinguish the first shift register from the second shift register in fig. 5, the first shift register may be represented by GOAn and GOAn +1, and the second shift register may be represented by GOA1 ', GOA 2', GOA3 ', GOA 4', and the like. On the other hand, the circuit structures of the first shift register and the second shift register are the same, and the circuit structures of the first shift register and the second shift register are the same as the circuit structure of the shift register shown in fig. 1, which is not described herein again. It is to be understood that the circuit structures of the first shift register and the second shift register in the embodiments of the present disclosure may also be in other forms, and are not listed here.

Fig. 6 is a timing diagram of signals in the gate driving circuit shown in fig. 5, and as shown in fig. 6, a pit stop time is inserted in the timing diagram, and the following analysis is performed in time nodes:

at time t0, the 2 nd first clock signal line CK2 is at a high level, and the potential of the pull-up node PU of the nth stage first shift register is pulled up to a high level.

At time t1, the 3 rd first clock signal line CK3 is at a high level, the potential of the signal OUTPUT terminal OUTPUT of the nth first shift register changes from a low level to a high level, and the potential of the pull-up node PU of the 1 st second shift register is pulled up to a high level.

At time t2, the 4 th first clock signal line CK4 is at a high level, the signal OUTPUT terminal OUTPUT of the 1 st second shift register OUTPUTs a high level, and the potential of the pull-up node PU of the 2 nd second shift register is pulled up to a high level.

At time t3, the 1 st first clock signal line CK1 is at a high level, the signal OUTPUT terminal OUTPUT of the 2 nd second shift register OUTPUTs a high level, and the potential of the pull-up node PU of the 3 rd second shift register is pulled up to a high level.

At time t4, the 2 nd first clock signal line CK2 is at a high level, the signal OUTPUT terminal OUTPUT of the 3 rd second shift register OUTPUTs a high level, and the potential of the pull-up node PU of the 4 th second shift register is pulled up to a high level. It is to be noted that the potential of the pull-up node PU of the nth first shift register is pulled down to a low level, and the second transistor M2 is in an off state.

And entering pit stopping time, wherein pull-up nodes PU of the 1 st second shift register, the 2 nd second shift register, the 3 rd second shift register and the 4 th second shift register store certain level, and the high level is kept to pass through the pit.

At time t5, the 3 rd first clock signal line CK3 is at a high level, the signal OUTPUT terminal OUTPUT of the 4 th second shift register OUTPUTs a high level, the potential of the pull-up node PU of the n +1 th first shift register is pulled up to a high level, and the potential of the pull-up node PU of the 1 st second shift register is pulled down to a low level.

At time t6, the 4 th first clock signal line CK4 is at a high level, the signal OUTPUT terminal OUTPUT of the n +1 th first shift register OUTPUTs a high level, and the potential of the pull-up node PU of the 2 nd second shift register is pulled down to a low level.

At time t7, the 1 st clock signal line CK1 is at a high level, and the potential of the pull-up node PU of the 3 rd second shift register is pulled down to a low level.

At time t8, the 2 nd first clock signal line CK2 is at a high level, and the potential of the pull-up node PU of the 4 th second shift register is pulled down to a low level.

At time t9, the 3 rd first clock signal line CK3 is at a high level, and the potential of the pull-up node PU of the (n + 1) th first shift register is pulled down to a low level.

In the embodiment of the present disclosure, the signal OUTPUT terminal OUTPUT of each second shift register is only used in the gate driving circuit to cascade with other shift registers, and is not connected to the gate line in the display panel, and the second shift register is used to store charges to pass through the pits, so that the shift of the threshold voltage Vth of the second transistor M2 in the second shift register does not affect the display of the display panel, and the formation of the pit stopping pattern is avoided, thereby improving the display effect. In addition, the electric charges may not be fixedly stored in some of the second shift registers when the pits are stopped, and the pits may be alternately passed when the pits are stopped, thereby alleviating the threshold voltage Vth drift of the second transistor M2 in each of the second shift registers.

It should be noted that, in the embodiment of the present disclosure, the number of sets of the second shift registers in the gate driving circuit is related to the number of times of pit stopping, if pit stopping is required once in a frame of display screen, a set of the second shift registers is required at least, and at least two sets of the second shift registers are required at least for pit stopping twice, and so on. The number of the second shift registers in each group is determined by the number of the shift register circuits and the number of the first clock signal lines, and is not limited herein.

Fig. 7 is a schematic diagram of another gate driving circuit of a touch display panel according to an embodiment of the disclosure, where the gate driving circuit shown in fig. 7 is different from the gate driving circuit shown in fig. 5 in that M second clock signal lines are further disposed in the gate driving circuit shown in fig. 7 in addition to the structure shown in fig. 5, and each adjacent M first shift registers in the N first shift registers are respectively connected to the M first clock signal lines; every adjacent M second shift registers in the K second shift registers are respectively connected with the M second clock signal lines and the M second clock signal lines. Specifically, the first shift register and the second shift register each have a first clock signal terminal CKm and a second clock signal terminal CKm-1; the first clock signal terminal CKm of the first shift register is connected with the m-th first clock signal line, and the second clock signal terminal CKm-1 is connected with the m-1-th first clock signal line; the first clock signal terminal CKm of the second shift register is connected with the jth second clock signal line, and the second clock signal terminal CKm-1 is connected with the pth first clock signal line; m, j and p are integers less than or equal to M.

It should be noted that, in the embodiment of the present disclosure, the number of the first clock signal lines and the second clock signal lines is 4, and the number of the corresponding second shift registers is also 4, where the first clock signal lines may be represented by CK1, CK2, CK3, and CK4 as the clock signals shown in fig. 1, and the second clock signal lines are represented by CK1 ', CK 2', CK3 ', and CK 4'.

Fig. 8 is a timing diagram of signals in the gate driving circuit shown in fig. 7, where as shown in fig. 8, a pit-stop time is inserted in the timing diagram, and the following analysis is performed in time nodes:

At time t2, the 4 th first clock signal line CK4 and the 4 th second clock signal line CK 4' are both at a high level, the signal OUTPUT terminal OUTPUT of the 1 st second shift register OUTPUTs a high level, and the potential of the pull-up node PU of the 2 nd second shift register is pulled up to a high level.

At time t3, the 1 st first clock signal line CK1 and the 1 st second clock signal line CK 1' are both at a high level, the signal OUTPUT terminal OUTPUT of the 2 nd second shift register OUTPUTs a high level, and the potential of the pull-up node PU of the 3 rd second shift register is pulled up to a high level.

At time t4, the 2 nd first clock signal line CK2 and the 2 nd second clock signal line CK 2' are both at a high level, the signal OUTPUT terminal OUTPUT of the 3 rd second shift register OUTPUTs a high level, and the potential of the pull-up node PU of the 4 th second shift register is pulled up to a high level. It is to be noted that the potential of the pull-up node PU of the nth first shift register is pulled down to a low level, and the second transistor M2 is in an off state.

At time t5, the 3 rd first clock signal line CK3 and the 3 rd second clock signal line CK 3' are both at a high level, the signal OUTPUT terminal OUTPUT of the 4 th second shift register OUTPUTs a high level, the potential of the pull-up node PU of the n +1 th first shift register is pulled up to a high level, and at this time, the potential of the pull-up node PU of the 1 st second shift register is pulled down to a low level.

In some embodiments, as shown in fig. 8, during the time from when the signal OUTPUT terminal OUTPUT of the nth first shift register OUTPUTs the scan signal to when the signal OUTPUT terminal OUTPUT of the n +1 th first shift register OUTPUTs the scan signal, the absolute value of the voltage of the clock signal transmitted by the second clock signal line is equal to the absolute value of the voltage of the clock signal transmitted by the first clock signal line.

The time from when the signal OUTPUT terminal OUTPUT of the nth first shift register OUTPUTs the scan signal to when the signal OUTPUT terminal OUTPUT of the (n + 1) th first shift register OUTPUTs the scan signal may be referred to as a guard time (i.e., the time indicated by the two solid lines other than the pit-in time in fig. 8), during which the first clock signal line and the corresponding second clock signal line have the same signal timing and the same absolute voltage value, so that the gate driving circuit can be guaranteed to operate normally during the time.

In some embodiments, as shown in fig. 8, the absolute value of the voltage of the clock signal transmitted by the second clock signal line is greater than the absolute value of the voltage of the clock signal transmitted by the second clock signal line except the time from when the scan signal is output from the signal output terminal of the nth first shift register to when the scan signal is output from the signal output terminal of the (n + 1) th first shift register.

After the pit is passed, in the non-protection time, several pulse signals can be transmitted in every second clock signal line, and after said pulse signals are set according to the requirements, when the signal of the second clock signal line is at a high level, and the potential of the pull-up node PU, which is the gate of the second transistor M2 in the second shift register, is at a low level, the signal of the second clock signal line, which is the source, is at a high level, since the voltage level of the pull-up node PU in the second shift register is low, the voltage level of the pull-down node PD is high, the fifth transistor M5 and the sixth transistor M6 are in an open state, the drain of the second transistor M2, i.e., the signal OUTPUT terminal OUTPUT, is low, so that the second transistor M2 is stressed negatively (as shown in fig. 9), the threshold voltage Vth thereof shifts negatively, mitigating the threshold voltage Vth generated by the second transistor M2 from shifting positively when the pit is stopped. For the second transistor M2 in the first shift register, the source is connected to the first clock signal line, and the second clock signal line is only connected to the second shift register, so the normal operation of the circuit is not affected, and the threshold voltage Vth shift of the second transistor M2 in the first shift register is not caused additionally. The signal in the second clock signal line can adjust the degree of the negative shift of the threshold voltage Vth of the second transistor M2 by adjusting the peak width to reach the equilibrium with the positive shift of the threshold voltage Vth generated at the time of pit stopping.

When the pulse is set, the absolute value of the voltage of the signal in the second clock signal line may be greater than the absolute value of the voltage of the signal in the first clock signal line, for example, VGH/VGL of the signal in the first clock signal line is 20V/-10V, and the VGH level of the signal in the second clock signal line may be set higher in the non-protection time, for example, 25V, 30V, 35V, so that the second transistor M2 may be better stressed, which causes negative drift of the threshold voltage Vth of the second transistor M2, and the normal operation of the gate driving circuit may not be affected because the second transistor M2 is in the off state at this time.

The embodiment of the present disclosure further provides a touch display device, where the touch display device includes the touch display panel provided in any of the above embodiments, and the touch display device may be any product or component with a touch display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, and a navigator, and its implementation principle and beneficial effect are the same as those of the touch display panel, which are not described herein again.

It is to be understood that the above embodiments are merely exemplary embodiments that are employed to illustrate the principles of the present disclosure, and that the present disclosure is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure, and these are to be considered as the scope of the disclosure.

Claims

1. A touch display panel, comprising: a gate driving circuit and N gate lines; the gate driving circuit includes: n first shift registers and at least one group of second shift registers; each group of second shift registers includes: k second shift registers; any group of second shift registers is arranged between the nth first shift register and the (n + 1) th first shift register; n and K are integers which are more than or equal to 2, and N is an integer which is less than N;

2. The touch display panel of claim 1, wherein the gate driving circuit further comprises: m first clock signal lines; m is an even number less than or equal to N and K;

3. The touch display panel according to claim 2, wherein the first shift register and the second shift register each have a first clock signal terminal and a second clock signal terminal;

4. The touch display panel of claim 1, wherein the gate driving circuit further comprises: m first clock signal lines and M second clock signal lines; m is an even number less than or equal to N and K;

5. The touch display panel according to claim 4, wherein the first shift register and the second shift register each have a first clock signal terminal and a second clock signal terminal;

6. The touch display panel according to claim 4, wherein the absolute value of the voltage of the clock signal transmitted by the second clock signal line is equal to the absolute value of the voltage of the clock signal transmitted by the first clock signal line from the time when the signal output terminal of the nth first shift register outputs the scan signal to the time when the signal output terminal of the (n + 1) th first shift register outputs the scan signal.

7. The touch display panel according to claim 4, wherein the absolute value of the voltage of the clock signal transmitted by the second clock signal line is greater than the absolute value of the voltage of the clock signal transmitted by the second clock signal line from the time when the signal output terminal of the nth first shift register outputs the scan signal to the time when the signal output terminal of the (n + 1) th first shift register outputs the scan signal.

8. The touch display panel according to claim 1, wherein the first shift register and the second shift register each include: the circuit comprises an input sub-circuit, an output sub-circuit, a pull-down control sub-circuit, a pull-down sub-circuit, a first noise reduction sub-circuit and a second noise reduction sub-circuit;

9. The touch display panel of claim 8, wherein the input sub-circuit comprises: a first transistor; the output sub-circuit includes: a second transistor and a storage capacitor; the pull-down control sub-circuit includes: a third transistor; the pull-down sub-circuit comprises: a fourth transistor; the first noise reduction sub-circuit comprises: a fifth transistor; the second noise reduction sub-circuit comprises: a sixth transistor;

10. A touch display device, characterized in that the display device comprises a touch display panel according to any one of claims 1-9.