CN113630561A - Television splicing box circuit with intelligent control system - Google Patents
Television splicing box circuit with intelligent control system Download PDFInfo
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- CN113630561A CN113630561A CN202110926118.7A CN202110926118A CN113630561A CN 113630561 A CN113630561 A CN 113630561A CN 202110926118 A CN202110926118 A CN 202110926118A CN 113630561 A CN113630561 A CN 113630561A
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- 230000000087 stabilizing effect Effects 0.000 claims description 13
- 229910052799 carbon Inorganic materials 0.000 claims description 12
- 230000003287 optical effect Effects 0.000 claims description 10
- 230000005669 field effect Effects 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 5
- 230000005236 sound signal Effects 0.000 claims description 5
- 239000011324 bead Substances 0.000 claims description 4
- 102100024452 DNA-directed RNA polymerase III subunit RPC1 Human genes 0.000 claims description 3
- 101000689002 Homo sapiens DNA-directed RNA polymerase III subunit RPC1 Proteins 0.000 claims description 3
- 101100382264 Mus musculus Ca14 gene Proteins 0.000 claims description 3
- 101100382265 Mus musculus Ca15 gene Proteins 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 description 12
- 102100033133 D-dopachrome decarboxylase Human genes 0.000 description 8
- 101000927579 Homo sapiens D-dopachrome decarboxylase Proteins 0.000 description 8
- 230000007717 exclusion Effects 0.000 description 8
- 229910052757 nitrogen Inorganic materials 0.000 description 7
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 101100010316 Porphyromonas gingivalis (strain ATCC 33277 / DSM 20709 / CIP 103683 / JCM 12257 / NCTC 11834 / 2561) dpp7 gene Proteins 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/2624—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects for obtaining an image which is composed of whole input images, e.g. splitscreen
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/268—Signal distribution or switching
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
- H04N5/775—Interface circuits between an apparatus for recording and another apparatus between a recording apparatus and a television receiver
Abstract
The invention discloses a television splicing box circuit with an intelligent control system, which comprises a power supply circuit, a control circuit, an HDMI interface switching circuit, an HDMI interface data processing circuit, an audio processing circuit, a display control circuit, a projection light processing circuit and a projection lens interface circuit, the circuits form a projection unit circuit which can switch two paths of HDMI video sources, a mobile phone APP is wirelessly connected with the television splicing box circuit to switch the video sources, the television splicing box circuit can splice four projection pictures and can watch the four pictures simultaneously, a projection unit circuit is arranged in the circuit drawing, the other three projection unit circuits are the same as the first unit circuit, and the splicing form of the picture has larger projection area and the multi-channel video picture can be watched and switched simultaneously, so that the multi-channel video picture has certain application value.
Description
Technical Field
The invention belongs to the field of video playing equipment, and particularly relates to a television splicing box circuit with an intelligent control system.
Background
The video pictures are played on the equipment to be watched, so that the video pictures become necessary products in life and work, such as watching television programs, playing propaganda videos and monitoring on-site real-time pictures in partial industries, videos with large sizes and different channels are required to be spliced and displayed and watched at the same time for some specific industries due to requirements of use environments, multi-channel video sources can be flexibly switched, and some video playing equipment cannot meet the requirements easily.
Disclosure of Invention
In order to solve the problems, the circuit of the invention is matched with a projection lens to simultaneously put four pictures into the projection lens to display the pictures on a screen, the size of the pictures can be adjusted at will, the four pictures can be automatically corrected in the circuit to enable the four pictures to be spliced without overlapping and without gaps, the circuit drawing is a circuit of a projection unit, other three projection unit circuits are the same as the circuit of a first unit, the control system arranges the four projection unit circuits into a block to form a multi-channel spliced projection picture, each projection unit circuit can be connected with two-channel HDMI video signals, and the channel switching can be carried out by keys in the circuit and can also be carried out by connecting a wireless network and carrying out the channel switching through the wireless operation of a mobile phone APP.
The invention adopts the following technical scheme that the television splicing box circuit with the intelligent control system comprises a power supply circuit, a control circuit, an HDMI interface switching circuit, an HDMI interface data processing circuit, an audio processing circuit, a display control circuit, a projection light processing circuit and a projection lens interface circuit, wherein the power supply circuit adjusts the power supply voltage in a corresponding range to supply power to each unit circuit, the control circuit can adjust the volume, channel selection and picture geometric correction, the HDMI interface switching circuit is responsible for switching the video of an HDMI interface, the HDMI interface data processing circuit is responsible for converting the HDMI interface data into video decoding data, the audio processing circuit converts digital audio coding data into analog audio signals, the display control circuit is responsible for converting the video data into optical signals and outputting the optical signals to the projection lens interface circuit, the projection light processing circuit is responsible for providing red, green and blue light sources, and the projection lens interface circuit is connected with the projection lens.
The 1 st pin of a J13 interface in the power supply circuit is used for connecting an external 5V power supply, the power supply is filtered to the ground through C166 and C167 capacitors and then is connected with an R114 resistor in series to the anode of a D12 light-emitting diode, the cathode of the power supply is connected with the ground, the 1 st pin of a J13 interface is connected with the 4 th pin of a U20 voltage stabilizing block under the filtering of a C168 capacitor, the model of the U20 voltage stabilizing block is TPS71501DCK, the 2 nd pin of the U20 voltage stabilizing block is connected with the ground, the 5 th pin of the U20 voltage stabilizing block is connected with the 1 st pin of an R116 resistor under the filtering of a C169 capacitor, the 1 st pin of the U20 voltage stabilizing block is connected with an R119 resistor in series to the ground, and the 1 st pin of the U20 voltage stabilizing block is connected with an R118 resistor in series to the 5 th pin of the U20 voltage stabilizing block; the 2 nd pin of the J13 interface is connected with a power ground; the 1 st pin of the J13 interface is connected with the 1 st pin of a U21 voltage-stabilizing block under the filtering of a C170 capacitor, the 2 nd pin of the U21 voltage-stabilizing block is connected with a power ground, the 3 rd pin of the U21 voltage-stabilizing block is connected with the 1 st pin of an R120 resistor, the 2 nd pin of the U21 voltage-stabilizing block is connected with the 1 st pin of the J13 interface, the 5 th pin of the U21 voltage-stabilizing block is connected with the 1 st pin of an L7 inductor, the 2 nd pin of the U21 voltage-stabilizing block outputs a 1.8V power under the filtering of a C171 capacitor, the 4 th pin of the U21 voltage-stabilizing block is connected with a R122 resistor in series to the power ground, the 4 th pin of the U21 voltage-stabilizing block is connected with a R123 resistor in series to the 2 nd pin of the L7 inductor in series, and the model number of the U21 voltage-stabilizing block is TPS62260 DDCT; the 1 st pin of the J13 interface is connected with the 1 st pin of a U22 voltage-stabilizing block after being filtered by a C172 capacitor, the 2 nd pin of the U22 voltage-stabilizing block is connected with a power ground, the 3 rd pin of the U22 voltage-stabilizing block is connected with the 1 st pin of an R120 resistor, the 5 th pin of the U22 voltage-stabilizing block is connected with the 1 st pin of an L8 inductor, the 2 nd pin thereof outputs 1.2V power under the filtering of the C173 capacitor, the 4 th pin of the U22 voltage-stabilizing block is connected with a R124 resistor in series to the power ground, the 4 th pin of the U22 voltage-stabilizing block is connected with a R125 resistor in series to the 2 nd pin of the L8 inductor in series, and the model number of the U22 voltage-stabilizing block is TPS 35 62260 DDCT; the 1 st pin of the J13 interface is connected with the 1 st pin of a U23 voltage-stabilizing block after being filtered by a C174 capacitor, the 2 nd pin of the U23 voltage-stabilizing block is connected with a power ground, the 3 rd pin of the U23 voltage-stabilizing block is connected with the 1 st pin of an R120 resistor, the 5 th pin of the U23 voltage-stabilizing block is connected with the 1 st pin of an L9 inductor, the 2 nd pin thereof outputs a 3.3V power supply under the filtering of the C175 capacitor, the 4 th pin of the U23 voltage-stabilizing block is connected with a resistor in series to the power ground, the 4 th pin of the U23 voltage-stabilizing block is connected with a resistor in series to the 2 nd pin of the L9 inductor, and the model number of the U23 voltage-stabilizing block is TPS62260 DDCT; the 1 st pin of the J13 interface is connected with the 1 st pin of a U24 voltage-stabilizing block after filtering by a C176 capacitor, the 2 nd pin of the U24 voltage-stabilizing block is connected with a power ground, the 3 rd pin of the U24 voltage-stabilizing block is connected with the 1 st pin of an R120 resistor, the 5 th pin of the U24 voltage-stabilizing block is connected with the 1 st pin of an L10 inductor, the 2 nd pin thereof is connected with the 1 st pin of a C177 capacitor, the 4 th pin of the U24 voltage-stabilizing block is connected with an R128 resistor in series to the power ground, the 4 th pin of the U24 voltage-stabilizing block is connected with an R129 resistor in series to the 2 nd pin of the L10 inductor, the 1 st pin of the R120 resistor is connected with the 1 st pin of an R121 resistor, and the model number of the U24 voltage-stabilizing block is TPS62260 DDCT.
The core device of the control circuit is an MSP430F2274IDAR chip U13, the pins 2 and 16 of the U13 are connected in series with R77 resistor to the pin 2 of the R116 resistor in the power circuit under the filtering of C117 and C118 capacitors, the pins 4 and 15 of the U13 are connected to the ground, the pin 3 of the U13 is connected to the pin 2 of the U6 chip, the pin 6 of the U13 is connected to the pin 2 of the U9 chip, the pin 7 of the U13 is connected in series with R75 resistor to the pin 2 of the R77 resistor, the pin 7 of the U13 is connected in series with C128 capacitor to the ground, the pin 14 of the U13 is connected to the pin 1 of the SW1 switch, the pins 3 and 6 of the SW1 switch are connected in series with R90 resistor to the pin 2 of the R116 resistor in the power circuit, the pin 1 and 4 of the SW 29 is connected in series with R96 to the ground, the pin 3 and 6 of the SW1 is connected in series with the resistor to the pin 20 of the power circuit, the 25 th pin of the U13 is connected with the 2 nd pin of the U17, the 26 th pin of the U13 is connected with the 2 nd pin of the U16, and the 27 th pin of the U13 is connected with the 2 nd pin of the U14; the 3 rd pin of the U14 is connected with a power ground, the 5 th pin of the U14 is connected with the 2 nd pin of the R116 resistor in the power circuit, the 4 th pin of the U14 is connected with the R81 resistor in series to the cathode of a D7 light-emitting diode, the anode of the D7 light-emitting diode is connected with a 3.3V power supply, and the U14 is provided with a model number SN74AUP1G07DCK which is mainly used for signal level conversion; the 3 rd pin of the U16 is connected with a power ground, the 5 th pin of the U16 is connected with the 2 nd pin of the R116 resistor in the power circuit, the 4 th pin of the U16 is connected with the R84 resistor in series to the cathode of a D9 light-emitting diode, the anode of the D9 light-emitting diode is connected with a 3.3V power supply, and the U16 is provided with a model number SN74AUP1G07DCK which is mainly used for signal level conversion; the 3 rd pin of the U17 is connected with a power ground, the 5 th pin of the U17 is connected with the 2 nd pin of the R116 resistor in the power circuit, the 4 th pin of the U17 is connected with the R87 resistor in series to the cathode of a D10 light-emitting diode, the anode of the D10 light-emitting diode is connected with a 3.3V power supply, and the U17 is provided with a model number SN74AUP1G07DCK which is mainly used for signal level conversion; the 3 rd pin of the U6 is connected with a power ground, the 5 th pin of the U6 is connected with a 1.8V power supply under the filtering of a C89 capacitor, the 4 th pin of the U6 is connected with a resistor R49 in series to the cathode of a D2 light-emitting diode, the anode of the U6 is connected with the 3.3V power supply, and the U6 is SN74AUP1G06DCKR and is mainly used for signal level conversion; the 3 rd pin of the U8 is connected with a power ground, the 5 th pin of the U8 is connected with a 1.8V power supply under the filtering of a C97 capacitor, the 4 th pin of the U8 is connected with a resistor R51 in series to the cathode of a D3 light-emitting diode, the anode of the U8 is connected with the 3.3V power supply, and the U8 is SN74AUP1G07DCK which is mainly used for signal level conversion; the 3 rd pin of the U9 is connected with a power ground, the 5 th pin of the U9 is connected with a 1.8V power supply under the filtering of a C100 capacitor, the 4 th pin of the U9 is connected with an R57 resistor in series to the cathode of a D5 light-emitting diode, the anode of the D5 light-emitting diode is connected with the 3.3V power supply, and the U9 is in a model of SN74AUP1G06DCKR and is mainly used for signal level conversion; a15 th pin of a U01 in the control circuit is connected with a power ground, an 8 th pin of a U01 in the control circuit is connected with an R045 resistor to a 3.3V power supply in series under filtering of C040 and C041 capacitors, a1 st pin of the U01 is connected with an R08 resistor to a 3.3V power supply in series, a3 rd pin of the U01 is connected with an R07 resistor to a 3.3V power supply in series, an 18 th pin of the U01 is connected with an R05 resistor to a 3.3V power supply in series, a 17 th pin of the U01 is connected with an R06 resistor to a 3.3V power supply in series, a 16 th pin of the U01 is connected with an R09 resistor to the power ground in series, a4 th pin of the U01 is connected with a C143 capacitor to the power ground in series, a4 th pin of the U01 is connected with an R99 resistor to a2 nd pin of an R116 in the power circuit, a4 th pin of the U01 is connected with an R101 resistor to a1 st pin and a3 pin of an SP2 switch, and a4 th pin of the SP2 is connected with the power ground; the 5 th pin of the U01 is connected in series with a C162 capacitor to the power ground, the 4 th pin of the U01 is connected in series with a R105 resistor to the 2 nd pin of the R116 in the power circuit, the 4 th pin of the U01 is connected in series with a R108 resistor to the 1 st and 3 rd pins of the SP3 switch, and the 4 th and 2 nd pins of the SP3 switch are connected to the power ground; the 6 th pin of the U01 is connected with a C165 capacitor in series to the power ground, the 4 th pin of the U01 is connected with a R111 resistor in series to the 2 nd pin of the R116 resistor in the power circuit, the 4 th pin of the U01 is connected with a R113 resistor in series to the 1 st and 3 rd pins of the SP4 switch, and the 4 th and 2 nd pins of the SP4 switch are connected with the power ground; the 7 th pin of the U01 is connected with a C163 capacitor in series to a power ground, the 4 th pin of the U01 is connected with a R106 resistor in series to the 2 nd pin of the R116 in the power circuit, the 4 th pin of the U01 is connected with a R109 resistor in series to the 1 st and 3 rd pins of the SP5 switch, and the 4 th and 2 nd pins of the SP5 switch are connected with the power ground; the 20 th pin of the U01 is connected in series with a C161 capacitor to a power ground, the 4 th pin of the U01 is connected in series with an R104 resistor to the 2 nd pin of the R116 in the power circuit, the 4 th pin of the U01 is connected in series with an R107 resistor to the 1 st and 3 rd pins of the SP1 switch, the 4 th and 2 nd pins of the SP1 switch are connected to the power ground, and the U01 is of an ESP-12E type and is mainly used for connecting a wireless WIFI network; the 19 th pin and the 20 th pin of the U01 are sequentially connected with the 4 th pin and the 5 th pin of a Pa1 connector, the 1 st pin and the 2 nd pin of the Pa1 connector are connected with the 1 st pin of a J13 interface in the power circuit, the 3 rd pin of the Pa1 connector is connected with a power ground, and an I2C bus of the 4 th pin and the 5 th pin of the Pa1 connector is used for connecting the circuits of 4 projection units together for unified control.
A core device of the HDMI interface switching circuit is a TS3DV642A0RUAR chip U12, and is mainly used for switching signals of HDMI, a 43 th pin of the U12 is connected to a power ground, a1 st pin of the U12 is connected to a1 st pin of the C177 capacitor in the power circuit under filtering of a C129 capacitor, 31, 32, 33, 34, 35, 36, 37, and 38 pins of the U12 are sequentially connected to 12, 10, 3, 1, 6, 4, 9, and 7 of an HDMI1 interface, and 18, 19, 41, and 42 pins of the U12 are sequentially connected to 13, 19, 16, and 15 pins of the HDMI1 interface; the 22 th, 23 th, 24 th, 25 th, 26 th, 27 th, 28 th and 29 th pins of the U12 are sequentially connected with the 12 th, 10 th, 3 th, 1 th, 6 th, 4 th, 9 th and 7 th pins of the HDMI2 interface, the 20 th, 21 th, 39 th and 40 th pins of the U12 are sequentially connected with the 13 th, 19 th, 16 th and 15 th pins of the HDMI2 interface, the 2 nd, 17 th, 16 th and 40 th pins of the U12 are sequentially connected with the 36 th, 37 th and 38 th pins of the U13 in the control circuit, the 10 th, 11 th, 7 th and 8 th pins of the U12 are sequentially connected with the 6 th, 1 th, 3 th and 4 th pins of the U10, the 5 th, 6 th, 12 th and 13 th pins of the U12 are sequentially connected with the 6 th, 1 th, 3 th and 4 th pins of the U11 chip, the 2 nd pin of the U12 is connected with a power ground, the 5 th pin of the U12 is connected with a 3.3V power supply, the 3 rd pin of the U12 is connected with the 1 st pin of the D8, and the 3 rd pin of the U5848 is connected with the 2 th pin of the U5848 is connected with the pin of the U12, the 3 rd pin of the U12 is connected with the 3 rd pin of a Q1 field effect transistor, and the 6 th pin of the U18 chip is connected with the 2 nd pin of the Q1 field effect transistor.
The core device of the HDMI interface data processing circuit is an ITE6801 chip U15, pins 26, 27, 28, 29, 31, 32, 33 and 34 of the U15 are sequentially connected with pins 13, 12, 6, 5, 8, 7, 11 and 10 of a U12 in the HDMI interface switching circuit, a pin 16 of the U15 is connected with a pin 5 of the HDMI interface switching circuit U18 chip in series through a resistor, a pin 17 of the U15 is connected with a pin 6 of the HDMI interface switching circuit U18 chip in series through a resistor R71, pins 25, 30, 35 and 40 of the U15 are connected with a 3.3V power supply under the filtering of C122, C123, C124, C125 and C126 capacitors, a pin 24 of the U15 is connected with a 3.3V power supply under the filtering of C127 and C130 capacitors, a pin 24 of the U15 is connected with a 1.2V power supply under the filtering of C131 capacitors, a pin 23 of the U15 feels that the filtering of the U3884 and the pin 23 is connected with a 3.3V power supply under the filtering of C3884 and F1.137 The series F9 power supply under C140 capacitive filtering senses 1.2V power supply, the pins 7, 15, 43, 48, 64 and 71 of the U15 are connected with 1.2V power supply under C156, C157, C158, C159, C160, C154 and C155 capacitive filtering, the R103 resistor is connected in parallel between the pins 38 and 39 of the U15, the X3 crystal oscillator is connected in parallel between the pins 38 and 39 of the U15, the pin 38 of the U15 is connected with the C152 capacitor in series to the power ground, the pin 39 of the U15 is connected with the C153 capacitor in series to the power ground, the pin 19 of the U15 is connected with the R25 resistor in series to the pin 14 of the U733 of the HDMI interface switching circuit, the pins 6, 50, 55, 63, 70 and 76 of the U15 are connected with 1.8V power supply under C113, C112 and C114 capacitive filtering, the pin 20 of the U15 is connected with 3V power supply under C111 capacitive filtering, the pin 853 of the U635 resistor 15 of the U8233 circuit is controlled by the pin 8536 of the U635, 4. Pins 3, 2, 1, 74, 73 and 72 are sequentially connected with pins 1, 2, 3, 4, 5, 6, 7 and 8 of an RA1 exclusion, pins 69, 68, 67, 66, 65, 62, 61 and 60 of the U15 are sequentially connected with pins 1, 2, 3, 4, 5, 6, 7 and 8 of an RA2 exclusion, and pins 59, 58, 57, 56, 54, 53, 52 and 51 of the U15 are sequentially connected with pins 1, 2, 3, 4, 5, 6, 7 and 8 of an RA3 exclusion.
The core device of the audio processing circuit is a TLV320DAC3101 chip Ua2 which is mainly used for converting digital audio data into analog audio signals, the 2 nd and 3 rd pins of the Ua2 are connected with a 1.8V power supply under Ca69 and Ca68 capacitive filtering, the 3.3V power supply in the power supply circuit is connected with the 1 st pin of a Fa3 inductor, the 2 nd pin of the Fa3 inductor is connected with the 17 th pin of the Ua2 under Ca14 capacitive filtering, the 17 th pin of the Ua2 is externally connected with Ca66 and Ca15 capacitive filtering for ground, the 2 nd pin of the Fa3 inductor is connected with the 28 th pin of the Ua2 under Ca67 and Ca59 capacitive filtering, the 33 th, 16 th, 18 th, 20 th, 25 th, 29 th and 1 th pins of the Ua2 are connected with the power supply ground, the 21 st and 24 th pins of the Ua2 are connected with the Ua 64 th pins of the Ca65, 63 and Ca64 capacitive filtering, and the Ua 64 th pin of the power supply circuit is sequentially connected with the Ua 13 and the Ua 599 th pin 599 of the HDMI 639 interface circuit in the HDMI 639 and 10 th pin of the HDMI circuit for processing, 13 pins, the 19 th, 22 th, 23 th and 26 th pins of the Ua2 are sequentially connected with the 4 th, 3 rd, 2 th and 1 st pins of a Ja5 connector, the 30 th pin of the Ua2 is connected with the 3 rd pin of a Ja2 interface in series through a C1 capacitor, the 27 th pin of the Ua2 is connected with the 2 nd pin of a Ja2 interface in series through a Ca2 capacitor, the 1 st pin of the Ja2 connector is connected with a power ground, the 5 th, 6 th, 7 th and 8 th pins of the Ua2 are sequentially connected with the 1 st pins of R92, R93, R95 and R98 resistors in the HDMI interface data processing circuit, and the 2 nd pins of the R92, R93, R95 and R98 resistors are sequentially connected with the 42 th, 45 th, 46 th and 41 th pins of the U15 in the HDMI interface data processing circuit.
In the display control circuit, the DPP3435 chip U5 has the C, D, E, F, G, H, J, K, L, M, G, C, F, G, H, J, K pins connected to a power supply ground, the DPP3435 chip U5 has the D, E, M, L, H, F, D, C, D, J, K, L, M, C pins externally connected to C, C and C pins connected to ground, the DPP3435 chip U5 has the C, D, E, F, K, M, C, N, C, N and N are connected to the DPP3435 chip U5, An N7 pin is connected with an R59 resistor in series to a 1.8V power supply under the capacitive filtering of C81, C83, C84 and C85, an H2 pin of the DPP3435 chip U5H is connected with C56 and C57 capacitors in series to the G57 and H57 pins of the DPP3435 chip U5 57, a G57 pin and an H57 pin of the DPP3435 chip U5 57 are connected with F57 magnetic beads to the D57 pin of the DPP3435 chip U5U 72, an R57 resistor is connected in parallel between the H57 pin and the J57 pin of the DPP3435 chip U5U 72, an H57 pin of the DPP3435 chip U5U 72 is connected with the X57 pin of an X57 crystal oscillator, the DPP 3435U 5U 72 pin is connected with the J57 pin of the DPP 57, the DPP3435 chip U5 is connected with the power supply pin of the DPP 57, the DPP 3472 is connected with the C57 pin of the DPP 57, the DPP3435 chip U5 is connected with the C57, the DPP 3472 pin is connected with the C57 resistor is connected with the C57, the DPP 57 pin 57, the DPP3435 chip 3435U 57 is connected with the C57 pin 57, the DPP 57 pin is connected with the C57, the third power supply pin 57, the DPP 57 pin is connected with the C57, the DPP 3435U 57 pin 57, the DPP 3435C 57, the DPP 3435C 57 pin is connected with the C57, the C57 pin is connected with the DPP 3472 pin 57, the C57 pin is connected with the C57, the DPP 57 pin is connected with the C57 pin 57, the DPP 57 pin is connected with the C57, the first pin is connected with the first pin 57, and the DPP 3435C 57 pin is connected with the DPP 57, the DPP 57 pin is connected with the first pin 57, the C3435C 57, the first pin 57, the DPP 57, the power supply pin 57, the first pin 57, the second pin 57, the DPP 57, the first pin is connected with the DPP 57, and the second pin is connected with the DPP 57, and the DPP3435 chip 3435C 57, and the DPP 57, and the first pin 57 pin is connected with the DPP 57, and the DPP 57 pin 57, the DPP 3435C 57, the DPP 3435C 57, the second pin is connected with the DPP 57, and the DPP 57, the DPP 57, a B12 pin of a DPP3435 chip U5A is connected in series with an R34 resistor to a2 nd pin of the U4 chip, a14 pin of the DPP3435 chip U5A is connected in series with a R40 resistor to a1 st pin of the U4 chip, the 3 rd, 7 th, and 8 th pins of the U4 chip are connected with a D5H pin of the DPP3435 chip U5H, the P H, and N H pins of the DPP3435 chip U5H are connected in series with R H, and the 1 st pin of the R H resistor, the 2 nd pins of the R H, and R H resistors are connected in sequence with the 8 th, 75 th, 10 th, and 9 th pins of the U H chip in the HDMI data processing circuit, the K H, L H, M H, N H, and P H, R H, P H, R H, P14, R H, and P H, R H, and P14, R H in the HDMI data processing circuit are connected in the HDMI interface data processing circuit, and P H, and P14, and P H are connected in sequence, 15. 14, 13, 12, 11, 10, 9 pins, the R6, P7, R7, P8, R8, P9, R9, P10 pins of the DPP3435 chip U5E are sequentially connected to the 16, 15, 14, 13, 12, 11, 10, 9 pins of the RA3 exclusion in the HDMI interface data processing circuit, the N8 pin of the DPP3435 chip U5E is connected in series to the R58 resistor to a 1.8V power supply, the N8 pin of the DPP3435 chip U5E is connected to the 3 rd pin of the U13 in the control circuit, and the DPP3435 chip is mainly used for converting video data into optical signals and outputting the optical signals to the projection lens interface circuit.
The 1 st and 2 th pins of a U7 chip in the projection lamp light processing circuit are connected with the 1 st pin of a J13 interface in the power supply circuit under the filtering of C92, C93, C94 and C95 capacitors, the 10 th pin of the U7 chip is connected with the 1 st pin of a J13 interface in the power supply circuit under the filtering of C99 capacitors, the 5 th, 12 th, 20 th, 23, 45 and 46 pins of the U7 chip are connected with a power ground, the 7 th pin of the U7 chip is connected with a series R46 resistor connected with the C15 pin of the U5C of the DPP3435 chip, the 3 rd pin of the U7 chip is connected with a series R47 resistor connected with the D14 pin of the U5C of the DPP3435 chip, the 8 th pin of the U7 chip is connected with a D7 pin of the U3435 chip 7, the L7 is connected between the 11 th pin and the D3615 pin of the U7 chip in series, the inductive U7 is connected with a cathode pin of the power supply circuit, the C7 of the DPP 7, the C7 is externally connected with a filtering diode 7 and a filtering diode 7, a 17 th pin of the U7 chip is externally connected with a C106 capacitor for filtering to ground, a 19 th pin of the U7 chip is externally connected with a C103 capacitor for filtering to ground, an 18 th pin of the U7 chip is connected with a1 st pin of the J13 interface under the filtering of C109 and C110 capacitors, a 21 st pin of the U7 chip is externally connected with a C108 capacitor for filtering to be connected with a 1.8V power supply, L6 inductors are connected in parallel between 24 th and 29 th pins of the U7 chip, a 29 th pin of the U7 chip is connected with a D3 pin of the DPP3435 chip U5C, the 28 th, 31 th and 34 th pins of the U7 chip are sequentially connected with a12, B15 and B14 pins of the U5D of the DPP3435 chip, L6 inductors are connected in parallel between 44 th, 43 th and 48 th pins 47 of the U7 th, 40 th, 39 th, 38 th and 34 th pins of the U7 th chip are sequentially connected with a J3 th, J6 th pins of the J9 and J9 th, J3 th pins of the J9, and J9 th pin of the U7 chip are used for providing a projection lens for supporting for connecting with a projection lens, And green and blue light sources, wherein the model number of U7 is PAD2005 which is mainly used for providing a light source for a projection lens and providing a partial power supply for a DPP3435 chip.
In the projection lens interface circuit, pins 1 and 50 of a J8 connector are connected with a 1.8V power supply under the filtering of a C55 capacitor, pins 37 and 38 of a J8 connector are connected with a 1.8V power supply under the filtering of a C73 capacitor, pins 2, 7, 12, 15, 20, 21, 22, 23, 25, 49, 48, 44, 39, 36, 31, 30 and 26 of the J8 connector are connected with a power ground, pins 47, 46 and 45 of the J8 connector are sequentially connected with pins 17, 15 and 14 of a U7 chip, pins 3 and 4 of the J8 connector are sequentially connected with pins B2 and B1 of a DPP3435 chip U5B, pin 6R 31 of the J8 connector is connected with pin A1 of the DPP3435 chip U5B in series, and pin 5 of the J8 connector is connected with pin 6R 6 of the DPP3435 connector in series with pins 3519, 19, 11, 3617, 16, 19, 16 and 16 of the DPP3435 chip U5, 32. Pins 33, 34, 35, 36, 40, 41, 42 and 43 are sequentially connected with pins A3, B3, A4, B4, A7, B7, A10, B10, A11, B11, B9, A9, B8, A8, B6, A6, B5 and A5 of the DPP3435 chip U5B, pins 23, 27 and 28 of the J8 connector are sequentially connected with pins 6, 5 and 1 of the U4 chip in the display control circuit, and the J8 connector is AXT550124 in model and is mainly used for connecting a matched projector lens.
The invention has the beneficial effects that:
(1) the television splicing box circuit of the intelligent control system can switch video sources through wireless operation of a mobile phone APP.
(2) According to the television splicing box circuit of the intelligent control system, each picture can be connected with two HDMI video sources, and 8 video signals can be connected in total for switching and watching.
(3) The television splicing box circuit of the intelligent control system can simultaneously put four pictures and four sets of pictures
And simultaneously putting the pictures on a screen for playing.
Drawings
FIG. 1 is a power supply circuit of an embodiment of the present application;
FIG. 2 is a control circuit according to an embodiment of the present application;
FIG. 3 is a control circuit according to an embodiment of the present application;
fig. 4 is an HDMI interface switching circuit according to an embodiment of the present application;
fig. 5 is an HDMI interface data processing circuit according to an embodiment of the present application;
FIG. 6 is an audio processing circuit of an embodiment of the present application;
FIG. 7 is a display control circuit according to an embodiment of the present application;
FIG. 8 is a display control circuit according to an embodiment of the present application;
FIG. 9 is a display control circuit according to an embodiment of the present application;
FIG. 10 is a projection light processing circuit according to an embodiment of the present application;
FIG. 11 is a projection lens interface circuit according to an embodiment of the present application;
fig. 12 is a functional schematic of an embodiment of the present application.
Detailed Description
To facilitate an understanding of the inventive circuit, the inventive circuit is described in more detail below with reference to the figures and the specific embodiments. Preferred embodiments of the present circuit are shown in the drawings, but the present invention may be embodied in many different forms and is not limited to the embodiments described in the specification. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for descriptive purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
The working principle is as follows:
the circuit of the invention is matched with a projection lens to simultaneously put four pictures in order to display the pictures on a screen, the size of the pictures can be adjusted at will, the four pictures can be automatically corrected in the circuit so that the four pictures can be spliced without overlapping and without gaps, the circuit drawing is a circuit of a projection unit, the other three projection unit circuits are the same as the circuit of the first unit, the control system arranges the four projection unit circuits together to form a multi-channel spliced projection picture, each projection unit circuit can be connected with two channel HDMI video signals, and the channel switching can be carried out by keys in the circuit and can also be carried out by wireless operation of a mobile phone APP through connecting a wireless network.
The implementation mode is as follows:
as shown in fig. 12, a tv splicing box circuit with an intelligent control system includes a power circuit, a control circuit, an HDMI interface switching circuit, an HDMI interface data processing circuit, an audio processing circuit, a display control circuit, a projection light processing circuit, and a projection lens interface circuit, wherein the power circuit adjusts a power voltage in a corresponding range to supply power to each unit circuit, the control circuit can adjust, for example, volume, channel selection, and geometric correction of a picture, the HDMI interface switching circuit is responsible for switching video of an HDMI interface, the HDMI interface data processing circuit is responsible for converting HDMI interface data into video decoding data, the audio processing circuit converts digital audio coding data into analog audio signals, the display control circuit is responsible for converting video data into optical signals and outputting the optical signals to the projection lens interface circuit, the projection light processing circuit is responsible for providing red, green and blue light sources, and the projection lens interface circuit is connected with the projection lens.
As shown in fig. 1, a pin 1 of a J13 interface in the power supply circuit connects an external 5V power supply, and after filtering to ground through capacitors C166 and C167, the pin is connected in series with a R114 resistor to an anode of a D12 light emitting diode, a cathode of the pin is connected to the ground, a pin 1 of the J13 interface is connected to a pin 4 of a U20 voltage regulator block under filtering of a capacitor C168, the model of the U20 voltage regulator block is TPS71501DCK, a pin 2 of the U20 voltage regulator block is connected to the ground, a pin 5 of the U20 voltage regulator block is connected to a pin 1 of an R116 resistor under filtering of a capacitor C169, a pin 1 of the U20 voltage regulator block is connected in series with a R119 resistor to the ground, and a pin 1 of the U20 voltage regulator block is connected in series with a R118 resistor to a pin 5 of the U20 voltage regulator block; the 2 nd pin of the J13 interface is connected with a power ground; the 1 st pin of the J13 interface is connected with the 1 st pin of a U21 voltage-stabilizing block under the filtering of a C170 capacitor, the 2 nd pin of the U21 voltage-stabilizing block is connected with a power ground, the 3 rd pin of the U21 voltage-stabilizing block is connected with the 1 st pin of an R120 resistor, the 2 nd pin of the U21 voltage-stabilizing block is connected with the 1 st pin of the J13 interface, the 5 th pin of the U21 voltage-stabilizing block is connected with the 1 st pin of an L7 inductor, the 2 nd pin of the U21 voltage-stabilizing block outputs a 1.8V power under the filtering of a C171 capacitor, the 4 th pin of the U21 voltage-stabilizing block is connected with a R122 resistor in series to the power ground, the 4 th pin of the U21 voltage-stabilizing block is connected with a R123 resistor in series to the 2 nd pin of the L7 inductor in series, and the model number of the U21 voltage-stabilizing block is TPS62260 DDCT; the 1 st pin of the J13 interface is connected with the 1 st pin of a U22 voltage-stabilizing block after being filtered by a C172 capacitor, the 2 nd pin of the U22 voltage-stabilizing block is connected with a power ground, the 3 rd pin of the U22 voltage-stabilizing block is connected with the 1 st pin of an R120 resistor, the 5 th pin of the U22 voltage-stabilizing block is connected with the 1 st pin of an L8 inductor, the 2 nd pin thereof outputs 1.2V power under the filtering of the C173 capacitor, the 4 th pin of the U22 voltage-stabilizing block is connected with a R124 resistor in series to the power ground, the 4 th pin of the U22 voltage-stabilizing block is connected with a R125 resistor in series to the 2 nd pin of the L8 inductor in series, and the model number of the U22 voltage-stabilizing block is TPS 35 62260 DDCT; the 1 st pin of the J13 interface is connected with the 1 st pin of a U23 voltage-stabilizing block after being filtered by a C174 capacitor, the 2 nd pin of the U23 voltage-stabilizing block is connected with a power ground, the 3 rd pin of the U23 voltage-stabilizing block is connected with the 1 st pin of an R120 resistor, the 5 th pin of the U23 voltage-stabilizing block is connected with the 1 st pin of an L9 inductor, the 2 nd pin thereof outputs a 3.3V power supply under the filtering of the C175 capacitor, the 4 th pin of the U23 voltage-stabilizing block is connected with a resistor in series to the power ground, the 4 th pin of the U23 voltage-stabilizing block is connected with a resistor in series to the 2 nd pin of the L9 inductor, and the model number of the U23 voltage-stabilizing block is TPS62260 DDCT; the 1 st pin of the J13 interface is connected with the 1 st pin of a U24 voltage-stabilizing block after filtering by a C176 capacitor, the 2 nd pin of the U24 voltage-stabilizing block is connected with a power ground, the 3 rd pin of the U24 voltage-stabilizing block is connected with the 1 st pin of an R120 resistor, the 5 th pin of the U24 voltage-stabilizing block is connected with the 1 st pin of an L10 inductor, the 2 nd pin thereof is connected with the 1 st pin of a C177 capacitor, the 4 th pin of the U24 voltage-stabilizing block is connected with an R128 resistor in series to the power ground, the 4 th pin of the U24 voltage-stabilizing block is connected with an R129 resistor in series to the 2 nd pin of the L10 inductor, the 1 st pin of the R120 resistor is connected with the 1 st pin of an R121 resistor, and the model number of the U24 voltage-stabilizing block is TPS62260 DDCT.
As shown in fig. 2 and fig. 3, the core device of the steering circuit is an MSP430F2274IDAR chip U13, the pins 2 and 16 of the U13 are serially connected with R77 resistance to the pin 2 of the R116 resistance in the power circuit under the capacitive filtering of C117 and C118, the pins 4 and 15 of the U13 are connected with the power ground, the pin 3 of the U13 is connected with the pin 2 of the U6 chip, the pin 6 of the U13 is connected with the pin 2 of the U9 chip, the pin 7 of the U13 is serially connected with R75 resistance to the pin 2 of the R77 resistance, the pin 7 of the U13 is serially connected with C128 capacitance to the power ground, the pin 14 of the U13 is connected with the pin 1 of the SW1 switch, the pins 3 and 6 of the SW1 switch are serially connected with R90 resistance to the pin 2 of the R116 resistance in the power series circuit, the pin 1, 4 of the SW1 is serially connected with R96 resistance to the power ground, the pin 141 of the SW1 is serially connected with the power switch, the 20 th pin of the U13 is connected with a resistor R89 in series to the 2 nd pin of the resistor R121 in the power supply circuit, the 25 th pin of the U13 is connected with the 2 nd pin of the U17, the 26 th pin of the U13 is connected with the 2 nd pin of the U16, and the 27 th pin of the U13 is connected with the 2 nd pin of the U14; the 3 rd pin of the U14 is connected with a power ground, the 5 th pin of the U14 is connected with the 2 nd pin of the R116 resistor in the power circuit, the 4 th pin of the U14 is connected with the R81 resistor in series to the cathode of a D7 light-emitting diode, the anode of the D7 light-emitting diode is connected with a 3.3V power supply, and the U14 is provided with a model number SN74AUP1G07DCK which is mainly used for signal level conversion; the 3 rd pin of the U16 is connected with a power ground, the 5 th pin of the U16 is connected with the 2 nd pin of the R116 resistor in the power circuit, the 4 th pin of the U16 is connected with the R84 resistor in series to the cathode of a D9 light-emitting diode, the anode of the D9 light-emitting diode is connected with a 3.3V power supply, and the U16 is provided with a model number SN74AUP1G07DCK which is mainly used for signal level conversion; the 3 rd pin of the U17 is connected with a power ground, the 5 th pin of the U17 is connected with the 2 nd pin of the R116 resistor in the power circuit, the 4 th pin of the U17 is connected with the R87 resistor in series to the cathode of a D10 light-emitting diode, the anode of the D10 light-emitting diode is connected with a 3.3V power supply, and the U17 is provided with a model number SN74AUP1G07DCK which is mainly used for signal level conversion; the 3 rd pin of the U6 is connected with a power ground, the 5 th pin of the U6 is connected with a 1.8V power supply under the filtering of a C89 capacitor, the 4 th pin of the U6 is connected with a resistor R49 in series to the cathode of a D2 light-emitting diode, the anode of the U6 is connected with the 3.3V power supply, and the U6 is SN74AUP1G06DCKR and is mainly used for signal level conversion; the 3 rd pin of the U8 is connected with a power ground, the 5 th pin of the U8 is connected with a 1.8V power supply under the filtering of a C97 capacitor, the 4 th pin of the U8 is connected with a resistor R51 in series to the cathode of a D3 light-emitting diode, the anode of the U8 is connected with the 3.3V power supply, and the U8 is SN74AUP1G07DCK which is mainly used for signal level conversion; the 3 rd pin of the U9 is connected with a power ground, the 5 th pin of the U9 is connected with a 1.8V power supply under the filtering of a C100 capacitor, the 4 th pin of the U9 is connected with an R57 resistor in series to the cathode of a D5 light-emitting diode, the anode of the D5 light-emitting diode is connected with the 3.3V power supply, and the U9 is in a model of SN74AUP1G06DCKR and is mainly used for signal level conversion; a15 th pin of a U01 in the control circuit is connected with a power ground, an 8 th pin of a U01 in the control circuit is connected with an R045 resistor to a 3.3V power supply in series under filtering of C040 and C041 capacitors, a1 st pin of the U01 is connected with an R08 resistor to a 3.3V power supply in series, a3 rd pin of the U01 is connected with an R07 resistor to a 3.3V power supply in series, an 18 th pin of the U01 is connected with an R05 resistor to a 3.3V power supply in series, a 17 th pin of the U01 is connected with an R06 resistor to a 3.3V power supply in series, a 16 th pin of the U01 is connected with an R09 resistor to the power ground in series, a4 th pin of the U01 is connected with a C143 capacitor to the power ground in series, a4 th pin of the U01 is connected with an R99 resistor to a2 nd pin of an R116 in the power circuit, a4 th pin of the U01 is connected with an R101 resistor to a1 st pin and a3 pin of an SP2 switch, and a4 th pin of the SP2 is connected with the power ground; the 5 th pin of the U01 is connected in series with a C162 capacitor to the power ground, the 4 th pin of the U01 is connected in series with a R105 resistor to the 2 nd pin of the R116 in the power circuit, the 4 th pin of the U01 is connected in series with a R108 resistor to the 1 st and 3 rd pins of the SP3 switch, and the 4 th and 2 nd pins of the SP3 switch are connected to the power ground; the 6 th pin of the U01 is connected with a C165 capacitor in series to the power ground, the 4 th pin of the U01 is connected with a R111 resistor in series to the 2 nd pin of the R116 resistor in the power circuit, the 4 th pin of the U01 is connected with a R113 resistor in series to the 1 st and 3 rd pins of the SP4 switch, and the 4 th and 2 nd pins of the SP4 switch are connected with the power ground; the 7 th pin of the U01 is connected with a C163 capacitor in series to a power ground, the 4 th pin of the U01 is connected with a R106 resistor in series to the 2 nd pin of the R116 in the power circuit, the 4 th pin of the U01 is connected with a R109 resistor in series to the 1 st and 3 rd pins of the SP5 switch, and the 4 th and 2 nd pins of the SP5 switch are connected with the power ground; the 20 th pin of the U01 is connected in series with a C161 capacitor to a power ground, the 4 th pin of the U01 is connected in series with an R104 resistor to the 2 nd pin of the R116 in the power circuit, the 4 th pin of the U01 is connected in series with an R107 resistor to the 1 st and 3 rd pins of the SP1 switch, the 4 th and 2 nd pins of the SP1 switch are connected to the power ground, and the U01 is of an ESP-12E type and is mainly used for connecting a wireless WIFI network; the 19 th pin and the 20 th pin of the U01 are sequentially connected with the 4 th pin and the 5 th pin of a Pa1 connector, the 1 st pin and the 2 nd pin of the Pa1 connector are connected with the 1 st pin of a J13 interface in the power circuit, the 3 rd pin of the Pa1 connector is connected with a power ground, and an I2C bus of the 4 th pin and the 5 th pin of the Pa1 connector is used for connecting the circuits of 4 projection units together for unified control.
As shown in fig. 4, a core device of the HDMI interface switching circuit is a TS3DV642A0RUAR chip U12, which is mainly used for switching signals of HDMI, a 43 th pin of the U12 is connected to a power ground, a1 st pin of the U12 is connected to a1 st pin of the C177 capacitor in the power circuit under filtering of a C129 capacitor, pins 31, 32, 33, 34, 35, 36, 37, and 38 of the U12 are sequentially connected to 12 th, 10 th, 3, 1, 6, 4, 9, and 7 of an HDMI1 interface, and pins 18, 19, 41, and 42 of the U12 are sequentially connected to pins 13, 19, 16, and 15 of the HDMI1 interface; the 22 th, 23 th, 24 th, 25 th, 26 th, 27 th, 28 th and 29 th pins of the U12 are sequentially connected with the 12 th, 10 th, 3 th, 1 th, 6 th, 4 th, 9 th and 7 th pins of the HDMI2 interface, the 20 th, 21 th, 39 th and 40 th pins of the U12 are sequentially connected with the 13 th, 19 th, 16 th and 15 th pins of the HDMI2 interface, the 2 nd, 17 th, 16 th and 40 th pins of the U12 are sequentially connected with the 36 th, 37 th and 38 th pins of the U13 in the control circuit, the 10 th, 11 th, 7 th and 8 th pins of the U12 are sequentially connected with the 6 th, 1 th, 3 th and 4 th pins of the U10, the 5 th, 6 th, 12 th and 13 th pins of the U12 are sequentially connected with the 6 th, 1 th, 3 th and 4 th pins of the U11 chip, the 2 nd pin of the U12 is connected with a power ground, the 5 th pin of the U12 is connected with a 3.3V power supply, the 3 rd pin of the U12 is connected with the 1 st pin of the D8, and the 3 rd pin of the U5848 is connected with the 2 th pin of the U5848 is connected with the pin of the U12, the 3 rd pin of the U12 is connected with the 3 rd pin of a Q1 field effect transistor, and the 6 th pin of the U18 chip is connected with the 2 nd pin of the Q1 field effect transistor.
As shown in fig. 5, the core device of the HDMI interface data processing circuit is an ITE6801 chip U15, the 26 th, 27 th, 28 th, 29 th, 31 th, 32 th, 33 th, 34 th pins of the U15 are sequentially connected to the 13 th, 12 th, 6 th, 5 th, 8 th, 7 th, 11 th, 10 th pins of the U12 in the HDMI interface switching circuit, the 16 th pin of the U15 is connected in series with R71 to be resistively connected to the 5 th pin of the HDMI interface switching circuit U18 chip, the 17 th pin of the U15 is connected in series with R73 to be resistively connected to the 6 th pin of the HDMI interface switching circuit U18 chip, the 25 th, 30 th, 35 th, 40 th pins of the U15 are connected to a 3.3V power supply under the C122, C123, C124, C125, C126 capacitive filtering, the 24 th pin of the U15 is connected to a 3.3V power supply under the C127, C130 capacitive filtering, the 24 th pin of the U15 is connected to a 1.2V filtering power supply under the C131 filtering capacitance, and the U632V 2F 23 is connected to be sensed by C2F filtering capacitance, the 37 th pin of the U15 senses 1.2V power by series connection of F9 under C138 and C140 capacitive filtering, the 7 th, 15 th, 43, 48, 64 and 71 th pins of the U15 are connected with 1.2V power by C156, C157, C158, C159, C160, C154 and C155 capacitive filtering, the R103 resistor is connected in parallel between the 38 th and 39 th pins of the U15, the X3 crystal oscillator is connected in parallel between the 38 th and 39 th pins of the U15, the 38 th pin of the U15 is connected with C152 capacitive filtering to power ground in series, the 39 th pin of the U15 is connected with C153 capacitive filtering to power ground in series, the 19 th pin of the U15 is connected with R69 resistor to the 14 th pin of the U12 of the HDMI interface switching circuit, the 6 th, 50 th, 55 th, 63 th, 70 th and 76 th pins of the U15 are connected with 1.8V power by C113, C112 series connection of C114 capacitive filtering, the 20 th pin of the U15 is connected with the U8233 and the U853 is connected with the U853 resistor 8912, the pins 5, 4, 3, 2, 1, 74, 73 and 72 of the U15 are sequentially connected with the pins 1, 2, 3, 4, 5, 6, 7 and 8 of an RA1 exclusion, the pins 69, 68, 67, 66, 65, 62, 61 and 60 of the U15 are sequentially connected with the pins 1, 2, 3, 4, 5, 6, 7 and 8 of the RA2 exclusion, and the pins 59, 58, 57, 56, 54, 53, 52 and 51 of the U15 are sequentially connected with the pins 1, 2, 3, 4, 5, 6, 7 and 8 of the RA3 exclusion.
As shown in fig. 6, the core device of the audio processing circuit is a TLV320DAC3101 chip Ua2, which is mainly used for converting digital audio data into analog audio signals, the 2 nd and 3 rd pins of the Ua2 are connected with a 1.8V power supply under Ca69 and Ca68 capacitive filtering, the 3.3V power supply in the power supply circuit is connected with the 1 st pin of a Fa3 inductor, the 2 nd pin of the Fa3 inductor is connected with the 17 th pin of the Ua2 under Ca14 capacitive filtering, the 17 th pin of the Ua2 is externally connected with Ca66 and Ca15 capacitive filtering to ground, the 2 nd pin of the Fa3 inductor is connected with the 28 th pin of the Ua2 under Ca67 and Ca59 capacitive filtering, the 33 th, 16 th, 18 th, 20 th, 25 th, 29 th and 1 st pin of the Ua2 is connected with the power supply ground, the 21 st and 24 th pins of the Ua2 are connected with the U599 th pins of the power supply circuit under Ca65, Ca63 and Ca64 th pins of the HDMI 639 and the HDMI connector of the HDMI circuit is sequentially connected with the U599 th pin 599 and the HDMI connector 14 of the HDMI connector of the HDMI circuit for processing, 13 pins, the 19 th, 22 th, 23 th and 26 th pins of the Ua2 are sequentially connected with the 4 th, 3 rd, 2 th and 1 st pins of a Ja5 connector, the 30 th pin of the Ua2 is connected with the 3 rd pin of a Ja2 interface in series through a C1 capacitor, the 27 th pin of the Ua2 is connected with the 2 nd pin of a Ja2 interface in series through a Ca2 capacitor, the 1 st pin of the Ja2 connector is connected with a power ground, the 5 th, 6 th, 7 th and 8 th pins of the Ua2 are sequentially connected with the 1 st pins of R92, R93, R95 and R98 resistors in the HDMI interface data processing circuit, and the 2 nd pins of the R92, R93, R95 and R98 resistors are sequentially connected with the 42 th, 45 th, 46 th and 41 th pins of the U15 in the HDMI interface data processing circuit.
As shown in fig. 7, 8 and 9, in the display control circuit, the DPP3435 chip U5 has its C, D, E, F, G, H, J, K, L, M, G, C, F, G, H, J, K pins connected to a power ground, the DPP3435 chip U5 has its D, E, M, L, H, F, D, C, D, J, K, L, M, C pins externally connected to C, C capacitor ground, and the DPP3435 chip U5 has its C, C, M7, N3 and N7 pins are connected with a power supply of 1.8V in series through R84 resistors under the capacitive filtering of C81, C83, C84 and C84, the H84 pin of the DPP3435 chip U5 84 is connected with C84 and C84 capacitors to the G84 and H84 pins of the DPP3435 chip U5 84, the G84 and H84 pins of the DPP3435 chip U5 84 are connected with F84 magnetic beads to the power ground in series, the J84 and H84 pins of the DPP3435 chip U5U 72 are connected with F84 magnetic beads to the D84 pin of the DPP3435 chip U5 84 in series, R84 resistors are connected between the H84 and J84 pins of the DPP3435 chip U5U 72 in parallel, the H84 pin of the DPP3435 chip U5U 72 is connected with the first pin of an X84 crystal oscillator, the DPP 3435U 5J 84 pin 84 is connected with the first pin 84, the DPP 3435U 84 is connected with the power supply of the C84, the DPP3435 chip U84 is connected with the power supply, the power supply 3 pin 84, the DPP 3435U 84, the DPP3435 chip U84 is connected with the power supply pin 84, the power supply is connected with the power supply pin 84, the first pin 84, the DPP 84, the third chip 84, the DPP 3435U 84, the DPP 3435U 84 is connected with the first pin 84, the second chip 84, the DPP 84, the third chip 84, the DPP 84 is connected with the third 84, and the power supply is connected with the power supply pin 84, the first pin 84, and the first pin 84, the second chip 84, and the DPP 84, the DPP 343672, and the DPP 84, the second chip 84, the DPP 84 is connected with the first 84, and the second 84, and the DPP 84, the second 84, the DPP 343672 is connected with the DPP 343672, and the DPP 84, the DPP3435 chip 84 pins 84, the first 84, the second 84, the DPP 343672 is connected with the first 84, the second 84, the DPP 84, the first 84, the DPP 84, and the DPP 343672 is connected with the DPP 84, and the DPP 343672, the DPP 84, and the first 84 pin 84, the first 84, the second 84 pin 84, and the DPP 343672 is connected with the first 84, and the DPP3435 chip 84, the second 84 pin 84 is connected with the DPP 343672, and the DPP34, a B12 pin of a DPP3435 chip U5A is connected in series with an R34 resistor to a2 nd pin of the U4 chip, a14 pin of the DPP3435 chip U5A is connected in series with a R40 resistor to a1 st pin of the U4 chip, the 3 rd, 7 th, and 8 th pins of the U4 chip are connected with a D5H pin of the DPP3435 chip U5H, the P H, and N H pins of the DPP3435 chip U5H are connected in series with R H, and the 1 st pin of the R H resistor, the 2 nd pins of the R H, and R H resistors are connected in sequence with the 8 th, 75 th, 10 th, and 9 th pins of the U H chip in the HDMI data processing circuit, the K H, L H, M H, N H, and P H, R H, P H, R H, P14, R H, and P H, R H, and P14, R H in the HDMI data processing circuit are connected in the HDMI interface data processing circuit, and P H, and P14, and P H are connected in sequence, 15. 14, 13, 12, 11, 10, 9 pins, the R6, P7, R7, P8, R8, P9, R9, P10 pins of the DPP3435 chip U5E are sequentially connected to the 16, 15, 14, 13, 12, 11, 10, 9 pins of the RA3 exclusion in the HDMI interface data processing circuit, the N8 pin of the DPP3435 chip U5E is connected in series to the R58 resistor to a 1.8V power supply, the N8 pin of the DPP3435 chip U5E is connected to the 3 rd pin of the U13 in the control circuit, and the DPP3435 chip is mainly used for converting video data into optical signals and outputting the optical signals to the projection lens interface circuit.
As shown in fig. 10, the 1 st and 2 nd pins of the U7 chip in the projection lamp light processing circuit are connected with the 1 st pin of the J13 interface in the power supply circuit under the capacitive filtering of C92, C93, C94 and C95, the 10 th pin of the U7 chip is connected with the 1 st pin of the J13 interface in the power supply circuit under the capacitive filtering of C99, the 5 th, 12, 20, 23, 45, 46 and pins of the U7 chip are connected with the power ground, the 7 th pin of the U7 chip is connected with the C15 pin of the DPP3435 chip U5C in series R46 in resistance, the 3 rd pin of the U7 chip is connected with the D14 pin of the U3435 chip U5C in series R47 in resistance, the 8 th pin R7 of the U7 chip is connected with the D15 pin of the U5 chip C in series, the DPP 15 th pin is connected with the DPP 3615 and the L15 and the anode 15 of the U15 chip is connected with the capacitor 15 and the cathode 15 and the C48 2, the 15 th pin of the U7 chip is externally connected with a C105 capacitor for filtering to ground, the 17 th pin of the U7 chip is externally connected with a C106 capacitor for filtering to ground, the 19 th pin of the U7 chip is externally connected with a C103 capacitor for filtering to ground, the 18 th pin of the U7 chip is connected with the 1 st pin of the J13 interface of the power supply circuit under the capacitive filtering of C109 and C110, the 21 st pin of the U7 chip is externally connected with a C108 capacitor for filtering to 1.8V power, an L6 inductor is connected in parallel between the 24 th pin and the 29 th pin of the U7 chip, the 29 th pin of the U7 chip is connected with the D3 pin of the DPP3435 chip U5C, the 28 th, 31 th and 34 th pins of the U7 chip are sequentially connected with the a12, B15 and B14 pins of the U5 chip U5D, the L7 th pin is connected in parallel between the 44 th, 43 pin and the 48, 47 pin of the U7, the DPP 3438, the J38, the J29 th pin is sequentially connected with the L4 and 364 th pin of the DPP 364, the J7 connector is used for connecting a matched projection lens to provide red, green and blue light sources for the lens, and the model U7 PAD2005 is mainly used for providing a light source for the projection lens and providing a partial power supply for the DPP3435 chip.
As shown in fig. 11, in the projection lens interface circuit, the 1 st and 50 th pins of the J8 connector are connected to a 1.8V power supply under C55 capacitive filtering, the 37 th and 38 th pins of the J8 connector are connected to a 1.8V power supply under C73 capacitive filtering, the 2 nd, 7 th, 12 th, 15 th, 20 th, 21 th, 22 th, 23 th, 25 th, 49 th, 48 th, 44 th, 39 th, 36 th, 31 th, 30 th and 26 th pins of the J8 connector are connected to a power supply ground, the 47 th, 46 th and 45 th pins of the J8 connector are connected to the 17 th, 15 th and 14 th pins of the U7 chip in turn, the 3 rd and 4 th pins of the J8 connector are connected to the B2 and B1 pins of the U5B of the DPP3435 chip in turn, the 6 th pin R31 of the J2 connector is connected to the a1 pin of the U5 chip in series, the 5 th pin 6866 th, 346 th, R6 th, the DPP connector is connected to the DPP 3527 th, 9 th, 3614 th, 16 th, DPP3435, DPP 27 th, B9 th, B3614 th, B9 th and B9 th pins of the DPP 9 th and B3614 th pins of the chip 3611 th pins of the chip 8 and B3611 of the chip 3611 th pins of the chip 7 chip 3611 connector are connected in series 3435 chip 8 and B3611 connector in series, 17. Pins 18, 19, 32, 33, 34, 35, 36, 40, 41, 42 and 43 are sequentially connected with pins A3, B3, A4, B4, A7, B7, A10, B10, A11, B11, B9, A9, B8, A8, B6, A6, B5 and A5 of the DPP3435 chip U5B, pins 23, 27 and 28 of the J8 connector are sequentially connected with pins 6, 5 and 1 of the U4 chip in the display control circuit, and the J8 connector is AXT550124 in model number and is mainly used for connecting a matched projector lens.
Claims (9)
1. A television splicing box circuit with an intelligent control system comprises a power supply circuit, a control circuit, an HDMI interface switching circuit, an HDMI interface data processing circuit, an audio processing circuit, a display control circuit, a projection light processing circuit and a projection lens interface circuit, wherein the power supply circuit adjusts power supply voltage in a corresponding range to supply power to each unit circuit, the control circuit can adjust volume, channel selection and picture geometric correction, the HDMI interface switching circuit is responsible for switching videos of an HDMI interface, the HDMI interface data processing circuit is responsible for converting HDMI interface data into video decoding data, the audio processing circuit converts digital audio coding data into analog audio signals, the display control circuit is responsible for converting video data into optical signals and outputting the optical signals to the projection lens interface circuit, the projection light processing circuit is responsible for providing red, green and blue light sources, and the projection lens interface circuit is connected with the projection lens.
2. The television splice box circuit with the intelligent control system as claimed in claim 1, wherein a1 st pin of a J13 interface in the power circuit is used for connecting an external 5V power supply, and is connected with an R114 resistor to an anode of a D12 light emitting diode after being filtered to the ground by C166 and C167 capacitors, a cathode of the D12 light emitting diode is connected with the ground of the power supply, a1 st pin of the J13 interface is connected with a4 th pin of a U20 voltage stabilizing block under the filtering of a C168 capacitor, a2 nd pin of the U20 voltage stabilizing block is connected with the ground of the power supply, a5 th pin of the U20 voltage stabilizing block is connected with a1 st pin of an R116 resistor under the filtering of a C169 capacitor, a1 st pin of the U20 voltage stabilizing block is connected with a R119 resistor to the ground of the power supply, and a1 st pin of the U20 voltage stabilizing block is connected with a R118 resistor to a5 th pin of the U20 voltage stabilizing block; the 2 nd pin of the J13 interface is connected with a power ground; the 1 st pin of the J13 interface is connected with the 1 st pin of a U21 voltage-stabilizing block under the filtering of a C170 capacitor, the 2 nd pin of the U21 voltage-stabilizing block is connected with a power ground, the 3 rd pin of the U21 voltage-stabilizing block is connected with the 1 st pin of an R120 resistor, the 2 nd pin of the U21 voltage-stabilizing block is connected with the 1 st pin of the J13 interface, the 5 th pin of the U21 voltage-stabilizing block is connected with the 1 st pin of an L7 inductor, the 2 nd pin of the U21 voltage-stabilizing block outputs a 1.8V power under the filtering of a C171 capacitor, the 4 th pin of the U21 voltage-stabilizing block is connected with a R122 resistor in series to the power ground, and the 4 th pin of the U21 voltage-stabilizing block is connected with a R123 resistor in series to the 2 nd pin of the L7 inductor in series; the 1 st pin of the J13 interface is connected with the 1 st pin of a U22 voltage-stabilizing block after being filtered by a C172 capacitor, the 2 nd pin of the U22 voltage-stabilizing block is connected with a power ground, the 3 rd pin of the U22 voltage-stabilizing block is connected with the 1 st pin of an R120 resistor, the 5 th pin of the U22 voltage-stabilizing block is connected with the 1 st pin of an L8 inductor, the 2 nd pin thereof outputs 1.2V power under the filtering of the C173 capacitor, the 4 th pin of the U22 voltage-stabilizing block is connected with a R124 resistor in series to the power ground, and the 4 th pin of the U22 voltage-stabilizing block is connected with the R125 resistor in series to the 2 nd pin of the L8 inductor; the 1 st pin of the J13 interface is connected with the 1 st pin of a U23 voltage-stabilizing block after being filtered by a C174 capacitor, the 2 nd pin of the U23 voltage-stabilizing block is connected with a power ground, the 3 rd pin of the U23 voltage-stabilizing block is connected with the 1 st pin of an R120 resistor, the 5 th pin of the U23 voltage-stabilizing block is connected with the 1 st pin of an L9 inductor, the 2 nd pin thereof outputs 3.3V power under the filtering of the C175 capacitor, the 4 th pin of the U23 voltage-stabilizing block is connected with a resistor in series to the power ground, and the 4 th pin of the U23 voltage-stabilizing block is connected with a resistor in series to the 2 nd pin of the L9 inductor; the 1 st pin of the J13 interface is connected with the 1 st pin of a U24 voltage-stabilizing block after filtering by a C176 capacitor, the 2 nd pin of the U24 voltage-stabilizing block is connected with a power ground, the 3 rd pin of the U24 voltage-stabilizing block is connected with the 1 st pin of an R120 resistor, the 5 th pin of the U24 voltage-stabilizing block is connected with the 1 st pin of an L10 inductor, the 2 nd pin thereof is connected with the 1 st pin of a C177 capacitor, the 4 th pin of the U24 voltage-stabilizing block is connected with an R128 resistor in series to the power ground, the 4 th pin of the U24 voltage-stabilizing block is connected with an R129 resistor in series to the 2 nd pin of the L10 inductor, and the 1 st pin of the R120 resistor is connected with the 1 st pin of the R121 resistor.
3. The TV splicing box circuit with intelligent control system according to claim 1, wherein the pins 2 and 16 of U13 chip in said control circuit are serially connected with R77 resistor to the pin 2 of said R116 resistor in said power circuit under the filtering of C117 and C118 capacitors, the pins 4 and 15 of said U13 chip are connected with power ground, the pin 3 of said U13 chip is connected with the pin 2 of U6 chip, the pin 6 of said U13 chip is connected with the pin 2 of U9 chip, the pin 7 of said U13 chip is serially connected with R75 resistor to the pin 2 of R77 resistor, the pin 7 of said U13 chip is serially connected with C128 capacitor to power ground, the pin 14 of said U13 chip is connected with the pin 1 of SW1 switch, the pins 3 and 6 of said SW1 switch are serially connected with R90 resistor to the pin 2 of said R116 resistor in said power circuit, the pin 3 and 6 of said SW1 switch is serially connected with R38 resistor to the pin 2 of said power circuit, the 2 nd pin of the SW1 switch is connected in series with a C141 capacitor to the power ground, the 20 th pin of the U13 chip is connected in series with an R89 resistor to the 2 nd pin of the R121 resistor in the power supply circuit, the 25 th pin of the U13 chip is connected with the 2 nd pin of the U17 chip, the 26 th pin of the U13 chip is connected with the 2 nd pin of the U16 chip, and the 27 th pin of the U13 chip is connected with the 2 nd pin of the U14 chip; the 3 rd pin of the U14 chip is connected with the ground, the 5 th pin of the U14 chip is connected with the 2 nd pin of the R116 resistor in the power circuit, the 4 th pin of the U14 chip is connected with the R81 resistor in series to the cathode of the D7 light-emitting diode, and the anode of the D7 light-emitting diode is connected with the 3.3V power supply; the 3 rd pin of the U16 chip is connected with the ground, the 5 th pin of the U16 chip is connected with the 2 nd pin of the R116 resistor in the power circuit, the 4 th pin of the U16 chip is connected with the R84 resistor in series to the cathode of the D9 light-emitting diode, and the anode of the D9 light-emitting diode is connected with the 3.3V power supply; the 3 rd pin of the U17 chip is connected with the ground, the 5 th pin of the U17 chip is connected with the 2 nd pin of the R116 resistor in the power circuit, the 4 th pin of the U17 chip is connected with the R87 resistor in series to the cathode of the D10 light-emitting diode, and the anode of the D10 light-emitting diode is connected with the 3.3V power supply; the 3 rd pin of the U6 chip is connected with a power ground, the 5 th pin of the U6 chip is connected with a 1.8V power supply under the filtering of a C89 capacitor, the 4 th pin of the U6 chip is connected with an R49 resistor in series to the cathode of a D2 light-emitting diode, and the anode of the U6 chip is connected with the 3.3V power supply; the 3 rd pin of the U8 chip is connected with a power ground, the 5 th pin of the U8 chip is connected with a 1.8V power supply under the filtering of a C97 capacitor, the 4 th pin of the U8 chip is connected with an R51 resistor in series to the cathode of a D3 light-emitting diode, and the anode of the U8 chip is connected with the 3.3V power supply; the 3 rd pin of the U9 chip is connected with the ground, the 5 th pin of the U9 chip is connected with the 1.8V power supply under the filtering of a C100 capacitor, the 4 th pin of the U9 chip is connected with an R57 resistor in series to the cathode of a D5 light-emitting diode, and the anode of the D5 light-emitting diode is connected with the 3.3V power supply; a15 th pin of a U01 chip in the control circuit is connected with a power ground, an 8 th pin of a U01 module in the control circuit is connected with an R045 resistor in series to a 3.3V power supply under filtering of C040 and C041 capacitors, a1 st pin of a U01 module is connected with an R08 resistor in series to a 3.3V power supply, a3 rd pin of a U01 module is connected with an R07 resistor in series to a 3.3V power supply, an 18 th pin of a U01 module is connected with an R05 resistor in series to a 3.3V power supply, a 17 th pin of a U01 module is connected with an R06 resistor in series to a 3.3V power supply, a 16 th pin of a U01 module is connected with an R09 resistor in series to a power ground, a4 th pin of a U01 module is connected with a C143 capacitor in series to a power ground, a4 th pin R99 resistor of a U01 module is connected with a2 nd pin of a R116 in series in the power circuit, and a4 th pin of a4 of a U01 module is connected with a R101 to an SP2 switch in series, a SP3 pin, and a SP3, and a switch pin 2, and a switch is connected with a power supply pin 364 th pin 363 and a switch; the 5 th pin of the U01 module is connected with C162 capacitor in series to the power ground, the 4 th pin of the U01 module is connected with R105 resistor in series to the 2 nd pin of R116 in the power circuit, the 4 th pin of the U01 module is connected with R108 resistor to the 1 st and 3 rd pins of the SP3 switch, and the 4 th and 2 nd pins of the SP3 switch are connected with the power ground; the 6 th pin of the U01 module is connected with C165 capacitor in series to the power ground, the 4 th pin of the U01 module is connected with R111 resistor in series to the 2 nd pin of R116 resistor in the power circuit, the 4 th pin of the U01 module is connected with R113 resistor in series to the 1 st and 3 rd pins of the SP4 switch, and the 4 th and 2 nd pins of the SP4 switch are connected with the power ground; the 7 th pin of the U01 module is connected with C163 capacitor in series to the power ground, the 4 th pin of the U01 module is connected with R106 resistor in series to the 2 nd pin of R116 in the power circuit, the 4 th pin of the U01 module is connected with R109 resistor to the 1 st and 3 rd pins of the SP5 switch, and the 4 th and 2 nd pins of the SP5 switch are connected with the power ground; the 20 th pin of the U01 module is connected in series with C161 capacitor to power ground, the 4 th pin of the U01 module is connected in series with R104 resistor to the 2 nd pin of R116 in the power circuit, the 4 th pin of the U01 is connected in series with R107 resistor to the 1 st and 3 rd pins of the SP1 switch, and the 4 th and 2 nd pins of the SP1 switch are connected to power ground.
4. The TV splicing box circuit with intelligent control system according to claim 1, wherein the 43 th pin of U12 chip in the HDMI interface switching circuit is connected to the power ground, the 1 st pin of U12 chip is connected to the 1 st pin of C177 capacitor in the power circuit under the filtering of C129 capacitor, the 31 st, 32 th, 33 th, 34 th, 35 th, 36 th, 37 th, 38 th pins of U12 chip are sequentially connected to the 12 th, 10 th, 3 th, 1 th, 6 th, 4 th, 9 th, 7 th pins of HDMI1 interface, the 18 th, 19 th, 41 th, 42 th pins of U12 chip are sequentially connected to the 13 th, 19 th, 16 th, 15 th pins of HDMI1 interface; the 22 th, 23 th, 24 th, 25 th, 26 th, 27 th, 28 th, 29 th pins of the U12 chip are sequentially connected to the 12 th, 10 th, 3 th, 1 th, 6 th, 4 th, 9 th, 7 th pins of the U12 chip are sequentially connected to the 13 th, 19 th, 16 th, 15 th pins of the HDMI2 interface, the 2 nd, 17 th, 16 th pins of the U12 chip are sequentially connected to the 36 th, 37 th, 38 th pins of the U13 chip in the control circuit, the 10 th, 11 th, 7 th, 8 th pins of the U12 chip are sequentially connected to the 6 th, 1 th, 3 th, 4 th pins of the U10 chip, the 5 th, 6 th, 12 th, 13 th pins of the U12 chip are sequentially connected to the 6 th, 1 th, 3 th, 4 th pins of the U11 chip, the 2 nd pin of the U12 chip is connected to a power ground, the 5 th pin of the U12 chip is connected to a 3.3V power supply, the 3 rd pin of the U12 chip is connected to the 854 th pin of the 854 th chip is connected to the D8 th pin of the chip, the 4 th pin of the U12 chip is connected with the 5 th pin of the U18 chip, the 3 rd pin of the U12 chip is connected with the 3 rd pin of the Q1 field effect transistor, and the 6 th pin of the U18 chip is connected with the 2 nd pin of the Q1 field effect transistor.
5. The TV splicing box circuit with intelligent control system of claim 1, wherein the 26 th, 27 th, 28 th, 29 th, 31 th, 32 th, 33 th, 34 th pins of U15 chip in the HDMI interface data processing circuit are sequentially connected with the 13 th, 12 th, 6 th, 5 th, 8 th, 7 th, 11 th, 10 th pins of U12 chip in the HDMI interface switching circuit, the 16 th pin of U15 chip is connected with the 5 th pin of U18 chip of the HDMI interface switching circuit in series with R71 resistance, the 17 th pin of U15 chip is connected with the 6 th pin of U18 chip of the HDMI interface switching circuit in series with R73 resistance, the 25 th, 30 th, 35 th, 40 th pins of U15 chip are connected with 3.3V power supply under C122, C123, C124, C125, C126 capacitance filtering, the 24 th pin of U15 chip is connected with 3.3V power supply under C127, C130 capacitance filtering, the 24 th pin of U15 chip is connected with 1.2V power supply under C131, the 23 rd pin of the U15 chip is serially connected with F8 to sense 1.2V power under the capacitive filtering of C135 and C137, the 37 th pin of the U15 chip is serially connected with F9 to sense 1.2V power under the capacitive filtering of C138 and C140, the 7 th, 15 th, 43 th, 48 th, 64 th and 71 th pins of the U15 chip are connected with 1.2V power under the capacitive filtering of C156, C157, C158, C159, C160, C154 and C155, the 38 th and 39 th pins of the U15 chip are parallelly connected with R103 resistor, the 38 th and 39 th pins of the U15 chip are parallelly connected with X3 crystal oscillator, the 38 th pin of the U15 chip is serially connected with C152 capacitor to power ground, the 39 th pin of the U15 chip is capacitively connected with C153 to power ground, the 19 th pin of the U15 chip is serially connected with R69 resistor to the 14 th pin of the U12 chip, the 6 th pin of the U15 chip is serially connected with R69 capacitor to switch circuit, 70, C55C 112, C114 th pin of the U15 chip is serially connected with C114, the 20 th pin of the U15 chip is connected with a 3.3V power supply under the filtering of a C111 capacitor, the 12 th pin of the U15 chip is connected with the 33 th pin of the U13 in the control circuit in series through an R78 resistor, the 5 th, 4 th, 3 th, 2 th, 1 th, 74 th, 73 th and 72 th pins of the U15 chip are sequentially connected with the 1 st, 2 th, 3 th, 4 th, 5 th, 6 th, 7 th and 8 th pins of an RA1 resistor bank, the 69 th, 68 th, 67 th, 66 th, 65 th, 62 th, 61 th and 60 th pins of the U15 chip are sequentially connected with the 1 st, 2 th, 3 th, 4 th, 5 th, 6 th, 7 th and 8 th pins of an RA2 resistor bank, and the 59 th, 58 th, 57 th, 56 th, 54 th, 53 th, 52 th and 51 th pins of the U15 chip are sequentially connected with the 1 st, 2 th, 3 th, 4 th, 5, 6 th, 7 th and 8 th pins of the RA3 resistor bank.
6. The TV splicing box circuit with intelligent control system as claimed in claim 1, wherein the 2 nd and 3 rd pins of Ua2 chip in the audio processing circuit are connected to 1.8V power supply under Ca69 and Ca68 capacitive filtering, the 3.3V power supply in the power supply circuit is connected to the 1 st pin of Fa3 inductor, the 2 nd pin of Fa3 inductor is connected to the 17 th pin of the Ua2 chip under Ca14 capacitive filtering, the 17 th pin of the Ua2 chip is externally connected to Ca66 and Ca15 capacitive filtering to ground, the 2 nd pin of the Fa3 inductor is connected to the 28 th pin of the Ua2 chip under Ca67 and Ca59 capacitive filtering, the 33 rd, 16 th, 18 th, 20 th, 25 th, 29 th and 1 th pins of the Ua2 chip are connected to ground, the 21 st and 24 th pins of the Ua2 chip are connected to the 24 th pins of the Ua 581 st pin of the power supply circuit under Ca65, Ca63 and Ca64 capacitive filtering, and the 3 th pin of the Ua 585 th interface of the Ua 5814 and the HDMI chip is connected to ground in turn, 13 pins, the 19 th, 22 th, 23 th and 26 th pins of the Ua2 chip are sequentially connected with the 4 th, 3 rd, 2 th and 1 st pins of a Ja5 connector, the 30 th pin of the Ua2 chip is connected with the 3 rd pin of a Ja2 interface in series through a C1 capacitor, the 27 th pin of the Ua2 chip is connected with the 2 nd pin of a Ja2 interface in series through a Ca2 capacitor, the 1 st pin of the Ja2 connector is connected with a power ground, the 5 th, 6 th, 7 th and 8 th pins of the Ua2 chip are sequentially connected with the 1 st pin of R92, R93, R95 and R98 resistors in the HDMI interface data processing circuit, and the 2 nd pins of R92, R93, R95 and R98 resistors are sequentially connected with the 42 th, 45 th, 46 th and 41 th pins of a U15 chip in the HDMI interface data processing circuit.
7. The TV splicing box circuit with intelligent control system according to claim 1, wherein the display control circuit is characterized in that the C, D, E, F, G, H, J, K, L, M, G, C, F, G, H, J, K pins of DPP3435 chip U5 are connected to a power supply ground, the D, E, M, L, H, F, D, C, D, J, K, L, M, C pins of DPP3435 chip U5 are externally connected with C, DPP 35 capacitor ground, and the pins of the DPP3435 chip U5 are connected to C, c78, C79 are connected with 1.8V power supply under capacitive filtering, M79, N79 pins of the DPP3435 chip U5 79 are connected with R79 resistor to 1.8V power supply under capacitive filtering of C79, H79 pins of the DPP3435 chip U5 79 are connected with C79 and C79 capacitor to G79 and H79 pins of the DPP3435 chip U5 79, G79 and H79 pins of the DPP3435 chip U5U 72 are connected with F79 magnetic beads to power ground, J79 and H79 pins of the DPP3435 chip U5U 72 are connected with D79 pins of the DPP 79 to D79 pins of the DPP3435 chip U5, the DPP 79 and DPP 343672 pins 79 of the DPP 3435U 79 are connected with the DPP 79, the DPP 3435J 79 and the DPP 79, the DPP 79 is connected with the DPP 79, the DPP3435, the DPP 79, the DPP3435 is connected with the C79, the power supply, the DPP 79, the DPP3435, the DPP 79, the first and the DPP 79 pins of the DPP 79, the DPP 79 is connected with the DPP 3435X 79, the DPP3435, the DPP 79, the first 79, the DPP 3435X 79, the DPP3435 is connected with the DPP 79, the first 79, the DPP 79, the first, the DPP 79, the first, the DPP 79, the DPP3435, the DPP 79, the DPP3435, the DPP 79, the first, the DPP 79, the first, the DPP 79, the DPP3435, the DPP 79, the first, the DPP 79, the second 79, the DPP3435, the DPP 79, the DPP3435, the first, the DPP 79, the first, the DPP3435, the DPP 79, the DPP3435, the DPP 79, the DPP3435, the DPP 343672, the DPP 79, the, a pin B13 of a DPP3435 chip U5A is serially connected with a pin R39 resistor to a pin 5 of the U4 chip, a pin B12 of the DPP3435 chip U5A is serially connected with a pin R34 resistor to a pin 2 of the U4 chip, a pin a14 of the DPP3435 chip U5A is serially connected with a pin R40 resistor to a pin 1 of the U4 chip, pins 3, 7 and 8 of the U4 chip are connected with a pin D11 of the DPP3435 chip U5H, pins P2, P3, P1 and N5 of the DPP3435 chip U5E are serially connected with a pin 1 of a resistor R68, R74 and R74 in turn, a pin 2 of resistors of the R74, a pin h 74, a pin L74, N3614, N74, N3614, N74, N72, N74, N3614, a data processing circuit in turn, the pins R1, R2, R3, P4, R4, P5, R5, and P6 of the DPP3435 chip U5E are sequentially connected to the pins 16, 15, 14, 13, 12, 11, 10, and 9 of the RA2 resistor bank in the HDMI interface data processing circuit, the pins R6, P7, R7, P8, R8, P9, R9, and P10 of the DPP3435 chip U5E are sequentially connected to the pins 16, 15, 14, 13, 12, 11, 10, and 9 of the RA3 resistor bank in the HDMI interface data processing circuit, the pin N8 of the DPP3435 chip U5E is serially connected to the resistor R58 to the power supply of 1.8V, and the pin N8 of the DPP3435 chip U5E is connected to the pin 3 of the U13 in the steering circuit.
8. The TV splicing box circuit with intelligent control system according to claim 1, wherein the 1 st and 2 nd pins of U7 chip in the projection light processing circuit are connected with the 1 st pin of J13 interface in the power circuit under the capacitive filtering of C92, C93, C94 and C95, the 10 th pin of U7 chip is connected with the 1 st pin of J13 interface in the power circuit under the capacitive filtering of C99, the 5 th, 12, 20, 23, 45, 46 th pin of U7 chip is connected with power ground, the 7 th pin of U7 chip is connected with the C15 pin of U5C of DPP3435 chip in series R46 resistance, the 3 rd pin of U7 chip is connected with the D14 pin of U5C chip in series R47 resistance, the 8 th pin of U7 chip is connected with the D15 pin of DPP3435 chip C in series R48 resistance, the U15 th pin of DPP 8672 is connected with the cathode 15 of the U15L 15 chip 15 in parallel connection with the cathode 3611 th pin of the DPP 15 and the U15, an anode of the U7 chip is connected in series with a C107 capacitor to a power ground, a15 th pin of the U7 chip is externally connected with a C105 capacitor for filtering to the ground, a 17 th pin of the U7 chip is externally connected with a C106 capacitor for filtering to the ground, a 19 th pin of the U7 chip is externally connected with a C103 capacitor for filtering to the ground, an 18 th pin of the U7 chip is connected with a1 st pin of a J13 interface of the power circuit under the capacitive filtering of C109 and C110, a 21 st pin of the U7 chip is externally connected with a C108 capacitor for filtering to be connected with a 1.8V power supply, L6 inductors are connected in parallel between the 24 th and 29 th pins of the U7 chip, the 29 th pin of the U7 chip is connected with a D3 pin of a U5C of the DPP3435 chip, the 28 th, 31 th and 34 th pins of the U7 chip are sequentially connected with A12, B15 and B14 pins of the U3435 chip U5, the U44, L43 and J38 th pins of the U7 chip are sequentially connected with L48 and 47 pins of the DPP 346 chip, and the L4 pins of the U38 and J38 chip are sequentially connected with the U38 th pins of the 3638 and J38, 2. 3 and 4 pins.
9. The TV splicing box circuit with intelligent control system according to claim 1, wherein the projection lens interface circuit has the J8 connector with 1.8V power supply at the 1 st and 50 th pins filtered by C55 capacitance, the J8 connector with the 37 th and 38 th pins filtered by C73 capacitance is connected with 1.8V power supply, the J8 connector with the 2 nd, 7 th, 12 th, 15 th, 20 th, 21 th, 22 th, 23 th, 25 th, 49 th, 48 th, 44, 39 th, 36 th, 31 th, 30 th and 38 th pins connected with the power ground, the J8 connector with the 47 th, 46 th and 45 th pins connected with the 17 th, 15 th and 14 th pins of the U7 chip in turn, the J8 connector with the 3 rd and 4 th pins connected with the B2 and B1 pins of the U3435 chip U5B in turn, the J8 connector with the 396326 th pin connected in series with the R31 to the DPP 3435U 345A 342 pin of the DPP 6329, and the J638 connector with the DPP 638 th and the DPP 23A 638 pin connected with the DPP 638A chip in turn, the 8 th, 9 th, 10 th, 11 th, 13 th, 14 th, 16 th, 17 th, 18 th, 19 th, 32 th, 33 th, 34 th, 35 th, 36 th, 40 th, 41 th, 42 th and 43 th pins of the J8 connector are sequentially connected with the A3 th, B3 th, A4 th, B4 th, A7 th, B7 th, a10 th, B10 th, a11 th, B11 th, B9 th, a9 th, B8 th, a8 th, B6 th, A6 th, B5 th and A5 th pins of the U4 chip in the display control circuit, and the 23 th, 27 th and 28 th pins of the J8 connector are sequentially connected with the 6 th, 5 th and 1 th pins of the U4 chip in the display control circuit.
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