CN113630126A - Polar code decoding processing method, device and equipment - Google Patents

Abstract

The invention provides a polar code decoding processing method, a polar code decoding processing device and polar code decoding processing equipment, and relates to the technical field of communication. The method comprises the following steps: receiving polarization code data to be decoded; according to the incomplete binary tree structure of the polarized code data, path expansion and path metric value updating are carried out on the first type node in the subtree, and path metric value updating is carried out on the second type node in the subtree; obtaining path metric values of all paths of the subtree after path expansion; and determining a hard bit sequence of the first type node of the subtree in the original bit sequence according to the path metric value. The scheme of the invention realizes the purpose of improving the decoding efficiency of the polar code.

Description

Polar code decoding processing method, device and equipment

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a method, an apparatus, and a device for decoding a polar code.

Background

Currently, for decoding Polar codes, a decoding method based on fast Successive Cancellation list fscl (fast Successive Cancellation list) is proposed. The FSCL predefines the leaf node type and the processing mode of the corresponding leaf node in decoding, and the binary tree is pruned into an incomplete binary tree, so that the decoding processing process is simplified.

However, in the conventional FSCL decoding process, path expansion needs to be performed on each encountered leaf node, a path metric value PM and a hard bit sequence of a corresponding path are calculated, and then L paths with the minimum PM are obtained according to a PM sorting result and are used as a basis for next path expansion. Thus, it needs to update and sequence the PM values many times, resulting in a significant increase in decoding delay.

Disclosure of Invention

The invention aims to provide a polar code decoding processing method, a polar code decoding processing device and polar code decoding processing equipment so as to improve the polar code decoding efficiency.

To achieve the above object, an embodiment of the present invention provides a polar code decoding processing method, including:

receiving polarization code data to be decoded;

according to the incomplete binary tree structure of the polarized code data, path expansion and path metric value updating are carried out on the first type node in the subtree, and path metric value updating is carried out on the second type node in the subtree;

obtaining path metric values of all paths of the subtree after path expansion;

and determining a hard bit sequence of the first type node of the subtree in the original bit sequence according to the path metric value.

Optionally, the determining, according to the path metric value, a hard bit sequence of the first type node of the sub-tree in an original bit sequence includes:

sorting the path metric values;

selecting a target path according to the sorting result, and acquiring a sorting sequence number of a path metric value corresponding to the target path;

and obtaining a hard bit sequence of the first type node of the subtree in the original bit sequence according to the sequence number.

Optionally, the sorting the path metric values includes:

and in the buffer area, the path metric values are sorted bit by bit from small to large.

Optionally, the path metric value corresponding to the target path is smaller than the path metric values of the remaining paths in the extended path.

Optionally, the obtaining a hard bit sequence of the first type node of the sub-tree in the original bit sequence according to the permutation sequence number includes:

determining the sequence number of the target path in the group corresponding to the expanded initial path according to the sequence number;

acquiring a binary indication value of the sequence number in the group;

and determining hard bit sequences of the first type nodes of the subtrees in the original bit sequences one by one from the high order to the low order of the binary indicated value.

Optionally, the determining, according to the sequence number, the intra-group sequence number of the target path after the initial path expansion includes:

by said permutation of serial number pairs

Obtaining remainder, and taking the obtained remainder as the serial number of the target path in the group corresponding to the expanded initial path; wherein N is_repIs the number of nodes of the first type in the subtree.

Optionally, the cache area corresponding to the path metric value has an initial area with the same number as the initial path in the initial state;

in the path expansion process, each path expansion divides each current area into two equal areas, and corresponding path metric value expansion is stored at the first position of the expanded area.

Optionally, the number of initial path metric values is the same as the initial number of paths.

The embodiment of the invention also provides decoding equipment, which comprises a memory, a processor and a computer program which is stored on the memory and can run on the processor; the processor implements the following steps when executing the program:

receiving polarization code data to be decoded;

according to the incomplete binary tree structure of the polarized code data, path expansion and path metric value updating are carried out on the first type node in the subtree, and path metric value updating is carried out on the second type node in the subtree;

obtaining path metric values of all paths of the subtree after path expansion;

and determining a hard bit sequence of the first type node of the subtree in the original bit sequence according to the path metric value.

Optionally, the processor is further configured to:

sorting the path metric values;

selecting a target path according to the sorting result, and acquiring a sorting sequence number of a path metric value corresponding to the target path;

and obtaining a hard bit sequence of the first type node of the subtree in the original bit sequence according to the sequence number.

Optionally, the processor is further configured to:

and in the buffer area, the path metric values are sorted bit by bit from small to large.

Optionally, the path metric value corresponding to the target path is smaller than the path metric values of the remaining paths in the extended path.

Optionally, the processor is further configured to:

determining the sequence number of the target path in the group corresponding to the expanded initial path according to the sequence number;

acquiring a binary indication value of the sequence number in the group;

and determining hard bit sequences of the first type nodes of the subtrees in the original bit sequences one by one from the high order to the low order of the binary indicated value.

Optionally, the processor is further configured to:

by said permutation of serial number pairs

Obtaining remainder, and taking the obtained remainder as the serial number of the target path in the group corresponding to the expanded initial path; wherein N is_repIs the number of nodes of the first type in the subtree.

Optionally, the cache area corresponding to the path metric value has an initial area with the same number as the initial path in the initial state;

in the path expansion process, each path expansion divides each current area into two equal areas, and corresponding path metric value expansion is stored at the first position of the expanded area.

Optionally, the number of initial path metric values is the same as the initial number of paths.

The embodiment of the present invention further provides a polar code decoding processing apparatus, including:

the receiving module is used for receiving the polarized code data to be decoded;

the first processing module is used for performing path expansion and path metric value updating on a first type node in a subtree and performing path metric value updating on a second type node in the subtree according to the incomplete binary tree structure of the polarized code data;

the second processing module is used for acquiring the path metric values of all paths of the subtree after path expansion;

and the third processing module is used for determining a hard bit sequence of the first type node of the subtree in the original bit sequence according to the path metric value.

Optionally, the third processing module includes:

the ordering submodule is used for ordering the path metric values;

the first processing submodule is used for selecting a target path according to the sorting result and acquiring the arrangement serial number of the path metric value corresponding to the target path;

and the second processing sub-module is used for obtaining a hard bit sequence of the first type node of the subtree in the original bit sequence according to the arrangement sequence number.

Optionally, the sorting sub-module is further configured to:

and in the buffer area, the path metric values are sorted bit by bit from small to large.

Optionally, the path metric value corresponding to the target path is smaller than the path metric values of the remaining paths in the extended path.

Optionally, the first processing sub-module includes:

a determining unit, configured to determine, according to the sequence number, an intra-group sequence number of the target path after the initial path expansion;

an obtaining unit, configured to obtain a binary indication value of the sequence number in the group;

and the processing unit is used for determining the hard bit sequences of the first type nodes of the subtrees in the original bit sequences one by one from the high order to the low order of the binary indicated value.

Optionally, the determining unit is further configured to:

by said permutation of serial number pairs

Obtaining remainder, and taking the obtained remainder as the serial number of the target path in the group corresponding to the expanded initial path; wherein N is_repIs the number of nodes of the first type in the subtree.

Optionally, the cache area corresponding to the path metric value has an initial area with the same number as the initial path in the initial state;

in the path expansion process, each path expansion divides each current area into two equal areas, and corresponding path metric value expansion is stored at the first position of the expanded area.

Optionally, the number of initial path metric values is the same as the initial number of paths.

Embodiments of the present invention also provide a readable storage medium, on which a program or an instruction is stored, where the program or the instruction, when executed by a processor, implements the steps in the polar code decoding processing method described above.

The technical scheme of the invention has the following beneficial effects:

in the method of the embodiment of the invention, after receiving the polarized code data to be decoded, the path expansion and the path metric value updating are carried out on the first type node in the sub-tree and the path metric value updating is carried out on the second type node in the sub-tree according to the incomplete binary tree structure of the polarized code data, so that the path metric values of all paths of the sub-tree after the path expansion are obtained, and finally the hard bit sequence of the first type node of the sub-tree in the original bit sequence is determined according to the obtained path metric values. Therefore, one sub-tree decoding process can simultaneously process one or more continuous first type nodes and second type nodes without interruption, and after the processing is finished, a hard bit sequence of the first type nodes of the sub-tree in the original bit sequence can be obtained, so that the decoding efficiency of the polarization code is improved.

Drawings

FIG. 1 is a flowchart illustrating a polar code decoding method according to an embodiment of the present invention;

FIG. 2 is a flowchart illustrating a method for decoding a polar code according to an embodiment of the present invention;

FIG. 3 is a diagram illustrating storage of path metric values according to an embodiment of the present invention;

FIG. 4 is a second schematic diagram illustrating path metric storage according to an embodiment of the present invention;

FIG. 5 is a third schematic diagram illustrating path metric storage according to an embodiment of the present invention;

FIG. 6 is a schematic diagram illustrating an application flow of a polar code decoding processing method according to an embodiment of the present invention;

FIG. 7 is a partial binary tree diagram;

FIG. 8 is a block diagram of a decoding apparatus according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of a polar code decoding processing apparatus according to an embodiment of the present invention.

Detailed Description

In order to make the technical problems, technical solutions and advantages of the present invention more apparent, the following detailed description is given with reference to the accompanying drawings and specific embodiments.

As shown in fig. 1, a polar code decoding processing method according to an embodiment of the present invention includes:

step 101, receiving polarization code data to be decoded;

102, according to the incomplete binary tree structure of the polarized code data, performing path expansion and path metric value updating on a first type node in a subtree, and performing path metric value updating on a second type node in the subtree;

step 103, obtaining path metric values of all paths of the subtree after path expansion;

and 104, determining a hard bit sequence of the first type node of the subtree in the original bit sequence according to the path metric value.

Through the above steps, the polarization code decoding processing method according to the embodiment of the present invention, after receiving polarization code data to be decoded, performs path expansion and path metric value updating on a first type node in a subtree and performs path metric value updating on a second type node in the subtree according to an incomplete binary tree structure of the polarization code data, thereby obtaining path metric values of all paths of the subtree after path expansion, and finally determining a hard bit sequence of the first type node of the subtree in an original bit sequence according to the obtained path metric values. Therefore, one sub-tree decoding process can simultaneously process one or more continuous first type nodes and second type nodes without interruption, and after the processing is finished, a hard bit sequence of the first type nodes of the sub-tree in the original bit sequence can be obtained, so that the decoding efficiency of the polarization code is improved.

In this embodiment, the incomplete binary tree structure of the polarized code data is obtained by pruning a complete binary tree, and the types of leaf nodes in the incomplete binary tree structure include RATE0, REP, SPC and RATE 1. Where REP is the first type node and RATE0 is the second type node. The number of binary tree layers represented for a polarization code of code length N is log2(N) + 1.

In this way, in the process of layer-by-layer decoding a sub-tree from top to bottom and from left to right, when a leaf node is encountered, if the leaf node is REP, path expansion and path metric value updating are performed, and if the leaf node is RATE0, path metric value updating is performed until the next leaf node is SPC or RATE 1. And the multiple sub-tree decoding will constitute a complete Polar decoding.

Wherein the initial path number P of the subtree_initAt the time of first decoding P_initFor system presetting, then P_initFor all the path numbers after path expansion in the last decoding.

Optionally, as shown in fig. 2, step 104 includes:

step 201, sorting the path metric values;

step 202, selecting a target path according to the sorting result, and acquiring a sorting sequence number of a path metric value corresponding to the target path;

step 203, obtaining the hard bit sequence of the first type node of the subtree in the original bit sequence according to the sequence number.

According to step 201 and 203, after the path metric values obtained in step 103 are sorted, a target path is selected according to the sorting result, and the arrangement sequence number of the path metric values corresponding to the target path is obtained, and then the hard bit sequence of the first type node of the subtree in the original bit sequence is obtained according to the arrangement sequence number of the path metric values corresponding to the target path.

In this embodiment, a buffer of the path metric value PM is set, and the size of the buffer is set according to the maximum number of paths of the path extension, for example, the maximum number of paths of the path extension is L_maxThen the cache region is of length L_maxARRAY PM _ ARRAY. Wherein the PM _ ARRAY initial value is all zero, and then according to P_initThe initial values of PM are evenly distributed in PM _ ARRAY.

If P _init1, corresponding to an initial PM value of PM_init0Then the PM _ ARRAY cache is updated as shown in Table 1 below (L)_max64, 64 values are all PM_init0)：

PMinit0

PMinit0

…

PMinit0

PMinit0

PMinit0

…

PMinit0

TABLE 1

If P _init2, corresponding to an initial PM value of PM_init0And PM_init1Then the PM _ ARRAY cache is updated as shown in Table 2 below (L)_max64, the first 32 values are PM_init0The last 32 values are PM_init1)：

PMinit0

PMinit0

…

PMinit0

PMinit1

PMinit1

…

PMinit1

TABLE 2

If P_initCorresponding to an initial PM value of PM 4_init0、PM_init1、PM_init2And PM_init3Then the PM _ ARRAY cache is updated as shown in Table 3 below (L)_max64, the first 16 values are PM_init0Sequentially 16 values being PM_init1Sequentially 16 values being PM_init2Sequentially 16 values being PM_init3)：

PMinit0

…

PMinit1

…

PMinit2

…

PMinit3

…

TABLE 3

Of course，P_initIs the number L of target paths.

During decoding, the occurrence of the leaf node REP will cause path extension and PM value update (the RATE0 node does not extend the path, but needs to update the PM value): for each path, two PM values, Δ PM, will be generated for each REP node that appears_i,rep0And Δ PM_i,rep1Wherein i represents the ith REP node; each time a RATE0 node appears, a PM value, Δ PM, will be generated_j,rate0Where j denotes the jth RATE0 node. Thus, passing through N_repA REP node and N_rate0After a RATE0 node, the total path number to be sorted is P_ext，

At the same time P_extPM update value of the strip path:

a cache is required.

In this embodiment, optionally, the cache area corresponding to the path metric value has an initial area with the same number as the initial path in the initial state;

in the path expansion process, each path expansion divides each current area into two equal areas, and corresponding path metric value expansion is stored at the first position of the expanded area.

Here, the initial state of the buffer is the state at the start of decoding a sub-tree, and the buffer is divided into the same number of initial regions as the number of initial paths in the initial state. Then, with the path expansion, each path expansion divides each current area into two equal areas, and stores the corresponding path metric value expansion at the first position of the expanded area.

Optionally, the number of initial path metric values is the same as the initial number of paths.

If P_init＝1(L_max64), as shown in fig. 3, the buffer has only one initial region in the initial state, and 64 bits each store the initial path metric value PM_init0(ii) a For the first time of path expansion, the cache area is divided into two areas equally, and at the moment, 0 bit and 32 bit store updated path metric values; for the second path expansion, the buffer area is divided into 4 areas, and at the moment, updated path metric values are stored in 0 bit, 16 bit, 32 bit and 48 bit; for the third time of path expansion, the buffer area is divided into 8 areas, and at the moment, updated path metric values are stored in 0 bit, 8 bit, 16 bit, 24 bit, 32 bit, 40 bit, 48 bit and 56 bit; for the fourth path expansion, the buffer area will be divided into 16 areas, and at this time, the updated path metric values are stored in 0 bit, 4 bit, 8 bit, 12 bit, 16 bit, 20 bit, 24 bit, 28 bit, 32 bit, 36 bit, 40 bit, 44 bit, 48 bit, 52 bit, 56 bit and 60 bit.

If P_init＝2(L_max64), as shown in fig. 4, the buffer is divided into 2 initial regions in the initial state, i.e. 0-31 bits store the initial path metric PM_init0And storing initial path metric values PM at 32-63 bits_init1(ii) a For the first time of path expansion, the buffer area is divided into 4 areas, and at the moment, updated path metric values are stored in 0 bit, 16 bit, 32 bit and 48 bit; for the second path expansion, the buffer area is divided into 8 areas, and at the moment, updated path metric values are stored in 0 bit, 8 bit, 16 bit, 24 bit, 32 bit, 40 bit, 48 bit and 56 bit; for the third time of path expansion, the buffer area will be divided into 16 areas, and at this time, the updated path metric values are stored in 0 bit, 4 bit, 8 bit, 12 bit, 16 bit, 20 bit, 24 bit, 28 bit, 32 bit, 36 bit, 40 bit, 44 bit, 48 bit, 52 bit, 56 bit and 60 bit.

If P_init＝4(L_max64), as shown in fig. 5, the buffer is divided into 4 initial regions in the initial state, i.e. 0-15 bits store the initial path metric PM_init0And storing initial path metric values P at 16-31 bit positionsM_init1And storing initial path metric values PM at 32-47 bits_init2And storing initial path metric values PM at 48-63 bit positions_init3(ii) a For the first time of path expansion, the buffer area is divided into 8 areas, and at the moment, updated path metric values are stored in 0 bit, 8 bit, 16 bit, 24 bit, 32 bit, 40 bit, 48 bit and 56 bit; for the second path expansion, the buffer will be divided into 16 regions, and at this time, the updated path metric values are stored in 0 bit, 4 bit, 8 bit, 12 bit, 16 bit, 20 bit, 24 bit, 28 bit, 32 bit, 36 bit, 40 bit, 44 bit, 48 bit, 52 bit, 56 bit and 60 bit.

Therefore, in the embodiment of the invention, the path metric value is stored in the cache region, so that the high utilization rate of the storage space can be realized.

In this embodiment, optionally, step 201 is:

and in the buffer area, the path metric values are sorted bit by bit from small to large.

Here, the path metric values obtained in step 103 are compactly arranged so as to determine a hard bit sequence based on the arrangement number of the path metric values corresponding to the target path.

In the sorting, the sorting order of the path metric values is configured according to the order from small to large of the path metric values. Wherein the selected sequence number of the corresponding path metric value is marked as PM_{idx_k}K is 0,1, … L-1, k denotes the kth target path, and L is the number of target paths.

Optionally, the path metric value corresponding to the target path is smaller than the path metric values of the remaining paths in the extended path.

Thus, the selected target path is the smallest L paths among all paths.

In this embodiment, the maximum number of target paths L may also be set_selL is less than or equal to L_selTo limit the selection of the target path. Of course, if P_extLess than L_sel，P_extThe strip path will be allIs selected as the target path.

After the target path is selected and the sequence number of the path metric value corresponding to the target path is obtained, step 203 may be executed. In this embodiment, optionally, step 203 includes:

determining the sequence number of the target path in the group corresponding to the expanded initial path according to the sequence number;

acquiring a binary indication value of the sequence number in the group;

and determining hard bit sequences of the first type nodes of the subtrees in the original bit sequences one by one from the high order to the low order of the binary indicated value.

Here, the target path corresponds to the intra-group sequence number after the initial path expansion, and is the intra-group sequence number of the initial path group before the path metric value is sorted. And the group number of the initial path group is denoted as GRP_idx，

The sequence numbers in the group are marked as REP_idx. Determining the sequence number REP of the target path in the group after the initial path expansion according to the sequence number of the path metric value corresponding to the target path_idxAnd finally determining the hard bit sequences of the first type nodes of the subtree in the original bit sequence one by one from the high order to the low order of the binary indication value. Thus, the decoding layer position of each REP node is combined to be used as the basis for processing the SPC/RATE1 node next time.

For example, REP_idxThe binary indication value of (a) is:

then N from high to low_repThe binary value, one by one, corresponds to the decoded hard bit sequence of the REP node in the sub-decoding process, i.e.

Corresponding to the first REP decoded hard bit sequence, … …, b₀The hard bit sequence is decoded corresponding to the last REP.

Optionally, the determining, according to the sequence number, the intra-group sequence number of the target path after the initial path expansion includes:

by said permutation of serial number pairs

Obtaining remainder, and taking the obtained remainder as the serial number of the target path in the group corresponding to the expanded initial path; wherein N is_repIs the number of nodes of the first type in the subtree.

That is to say that the first and second electrodes,

referring to fig. 6, in the decoding process of the polarization code, P is set for the received polarization code to be decoded_initAnd a corresponding initial PM value. Through the incomplete binary tree structure of the polarization code, the REP number N can be counted_repAnd performing path expansion on the first type nodes in the subtree, and calculating the number P of the expanded paths_ext. And updating the path metric value of the first type node and the second type node in the subtree, and updating the expanded P_extPM values of the strip paths, and compact arrangement. Then, the L paths with the minimum PM value can be screened out, and the arrangement serial number PM is recorded_{idx_k}. Further represented by the formula REP_idx＝PM_{idx_k}％2^NrepGet the sequence number REP in the group_idxAnd obtaining REP_idxBinary representation b_Nrepb_Nrep-1...b₁b₀。REP_idxN from high to low_repThe bits correspond to the decoded hard bit sequence of the REP node from high to low of the decoding layer one by one. And obtaining a REP coded bit sequence for subsequent operation according to the characteristics and the layer position of the REP node. In addition, GRP is expressed by the formula_idx＝PM_{idx_k}/2^NrepObtaining the group number GRP of the initial path group_idxAnd GRP_idxThe method can be used for splicing hard bit sequences decoded in two stages. Finally, the decoded results are merged as the basis for the next processing of the SPC/RATE1 node.

The application of the method of the embodiment of the present invention is described below by taking (128, 36) Polar code as an example. The incomplete binary tree structure of the (128, 36) Polar code is shown in FIG. 7. In the first PM sorting process, the nodes to be processed are 3, 9, 21, and 45, and the initial path number is assumed to be 1, and since there are 3 REP nodes, after the path is expanded, 8(L ═ 8) paths and corresponding PM values are obtained, and the 8 PM values are sorted in ascending order, and the sorted result corresponds to the sequence number in the group after the initial path is expanded. If the minimum intra-group sequence number is 3, the REP decode value of the node 9 in the corresponding screening path is 0, the REP decode value of the node 21 is 1, and the REP decode value of the node 45 is 1; if the intra-group sequence number of the next small value is 2, the REP decode value of the node 9 in the corresponding screening path is 0, the REP decode value of the node 21 is 1, and the REP decode value of the node 45 is 0; by analogy, the node information of each RATE0 and REP in 8 paths can be obtained, as shown in table 4 below:

TABLE 4

Therefore, compared with the method that only one RATE0 or REP node can be processed at a time, the method does not need to be sequenced for many times, and the decoding time delay is reduced; moreover, the information bit and the coding bit sequence of each extension path are prevented from needing to be stored and additionally occupying a large amount of storage space in the process of processing the nodes 3, 9, 21 and 45 one by one.

By applying the decoding device of the method of the embodiment of the present invention, after a plurality of continuous RATE0 nodes and REP nodes are collected together for processing, the classification of the sub-trees becomes simple, and the total cycle of Polar decoding is greatly reduced, for example, (N-128, K-36) Polar codes only need to be split into 4 decoding sub-trees, and the total cycle of decoding is 296 cycles. One sub-tree decoding process can simultaneously process one or more continuous REP nodes and RATE0 nodes without interruption, and after the processing is finished, REP node information of a plurality of screened paths can be obtained; the times of updating and sequencing the PM values are obviously less than that of the traditional FSCL algorithm, so that the decoding delay can be greatly reduced, and the decoding efficiency is improved.

Under the scene that the 5G subcarrier interval is 30KHz, a physical downlink control channel PDCCH Polar decoder has a total decoding cycle of 430-1200 according to the difference of values of Polar codes N and K. Considering that Polar decoding also has an early termination function, the actual cycle of PDCCH Polar decoding is around 500 on average. When designing a PDCCH accelerator, 2-way Polar decoder can be provided, the comprehensive layout and wiring frequency is 200MHz, 36 times of blind tests of PDCCH in 5G require about the processing time delay: 36 × 500/200/2 ═ 45us, and the total processing delay of the PDCCH requires 2.5 symbols (about 87us), so Polar decoders can contend for processing times greater than 1 symbol (35us) for PDCCH symbol-level and bit-level calculations, providing more redundancy to the system design.

In summary, in the method according to the embodiment of the present invention, after receiving the polarization code data to be decoded, according to the incomplete binary tree structure of the polarization code data, the path extension and the path metric value update are performed on the first type node in the subtree, and the path metric value update is performed on the second type node in the subtree, so as to obtain the path metric values of all paths of the subtree after the path extension, and finally determine the hard bit sequence of the first type node in the original bit sequence according to the obtained path metric values. Therefore, one sub-tree decoding process can simultaneously process one or more continuous first type nodes and second type nodes without interruption, and after the processing is finished, a hard bit sequence of the first type nodes of the sub-tree in the original bit sequence can be obtained, so that the decoding efficiency of the polarization code is improved.

As shown in fig. 8, an embodiment of the present invention further provides a decoding apparatus, which includes a memory 810, a processor 820, and a computer program stored in the memory 810 and executable on the processor 820; the processor 820, when executing the program, implements the following steps:

receiving polarization code data to be decoded;

according to the incomplete binary tree structure of the polarized code data, path expansion and path metric value updating are carried out on the first type node in the subtree, and path metric value updating is carried out on the second type node in the subtree;

obtaining path metric values of all paths of the subtree after path expansion;

and determining a hard bit sequence of the first type node of the subtree in the original bit sequence according to the path metric value.

Optionally, the processor is further configured to:

sorting the path metric values;

selecting a target path according to the sorting result, and acquiring a sorting sequence number of a path metric value corresponding to the target path;

and obtaining a hard bit sequence of the first type node of the subtree in the original bit sequence according to the sequence number.

Optionally, the processor is further configured to:

and in the buffer area, the path metric values are sorted bit by bit from small to large.

Optionally, the path metric value corresponding to the target path is smaller than the path metric values of the remaining paths in the extended path.

Optionally, the processor is further configured to:

determining the sequence number of the target path in the group corresponding to the expanded initial path according to the sequence number;

acquiring a binary indication value of the sequence number in the group;

and determining hard bit sequences of the first type nodes of the subtrees in the original bit sequences one by one from the high order to the low order of the binary indicated value.

Optionally, the processor is further configured to:

by said permutation of serial number pairs

Obtaining remainder, and taking the obtained remainder as the serial number of the target path in the group corresponding to the expanded initial path; wherein N is_repIs the number of nodes of the first type in the subtree.

Optionally, the cache area corresponding to the path metric value has an initial area with the same number as the initial path in the initial state;

in the path expansion process, each path expansion divides each current area into two equal areas, and corresponding path metric value expansion is stored at the first position of the expanded area.

Optionally, the number of initial path metric values is the same as the initial number of paths.

The decoding device further comprises a transceiver 930.

In FIG. 8, a bus architecture (represented by a bus), which may include any number of interconnected buses and bridges, links together various circuits including one or more processors, represented by the general purpose processor 820, and a memory, represented by the memory 810. The bus may also link various other circuits such as peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further herein. The bus interface provides an interface between the bus and the transceiver 830. The transceiver 830 may be one element or a plurality of elements, such as a plurality of receivers and transmitters, providing a means for communicating with various other apparatus over a transmission medium. For example: the transceiver 830 receives external data from other devices. The transceiver 830 is used for transmitting data processed by the processor 820 to other devices.

The processor 820 is responsible for managing the bus and general processing. And memory 810 may be used to store data used by processor 820 in performing operations.

Alternatively, processor 820 may be a CPU, ASIC, FPGA, or CPLD.

After receiving the polarization code data to be decoded, the decoding device performs path expansion and path metric value updating on a first type node in a subtree and performs path metric value updating on a second type node in the subtree according to the incomplete binary tree structure of the polarization code data, so that path metric values of all paths of the subtree after path expansion are obtained, and finally, a hard bit sequence of the first type node of the subtree in an original bit sequence is determined according to the obtained path metric values. Therefore, one sub-tree decoding process can simultaneously process one or more continuous first type nodes and second type nodes without interruption, and after the processing is finished, a hard bit sequence of the first type nodes of the sub-tree in the original bit sequence can be obtained, so that the decoding efficiency of the polarization code is improved.

As shown in fig. 9, an embodiment of the present invention further provides a polar code decoding processing apparatus, including:

a receiving module 910, configured to receive polar code data to be decoded;

a first processing module 920, configured to perform path expansion and path metric value update on a first type node in a sub-tree according to the incomplete binary tree structure of the polarized code data, and perform path metric value update on a second type node in the sub-tree;

a second processing module 930, configured to obtain path metric values of all paths of the subtree after path expansion;

a third processing module 940, configured to determine a hard bit sequence of the first type node of the sub-tree in the original bit sequence according to the path metric value.

Optionally, the third processing module includes:

the ordering submodule is used for ordering the path metric values;

the first processing submodule is used for selecting a target path according to the sorting result and acquiring the arrangement serial number of the path metric value corresponding to the target path;

and the second processing sub-module is used for obtaining a hard bit sequence of the first type node of the subtree in the original bit sequence according to the arrangement sequence number.

Optionally, the sorting sub-module is further configured to:

and in the buffer area, the path metric values are sorted bit by bit from small to large.

Optionally, the path metric value corresponding to the target path is smaller than the path metric values of the remaining paths in the extended path.

Optionally, the first processing sub-module includes:

a determining unit, configured to determine, according to the sequence number, an intra-group sequence number of the target path after the initial path expansion;

an obtaining unit, configured to obtain a binary indication value of the sequence number in the group;

and the processing unit is used for determining the hard bit sequences of the first type nodes of the subtrees in the original bit sequences one by one from the high order to the low order of the binary indicated value.

Optionally, the determining unit is further configured to:

by said permutation of serial number pairs

Obtaining remainder, and taking the obtained remainder as the serial number of the target path in the group corresponding to the expanded initial path; wherein N is_repIs the number of nodes of the first type in the subtree.

Optionally, the cache area corresponding to the path metric value has an initial area with the same number as the initial path in the initial state;

in the path expansion process, each path expansion divides each current area into two equal areas, and corresponding path metric value expansion is stored at the first position of the expanded area.

Optionally, the number of initial path metric values is the same as the initial number of paths.

After receiving the polarized code data to be decoded, the device performs path expansion and path metric value updating on a first type node in a subtree and performs path metric value updating on a second type node in the subtree according to the incomplete binary tree structure of the polarized code data, so that path metric values of all paths of the subtree after path expansion are obtained, and finally, a hard bit sequence of the first type node of the subtree in an original bit sequence is determined according to the obtained path metric values. Therefore, one sub-tree decoding process can simultaneously process one or more continuous first type nodes and second type nodes without interruption, and after the processing is finished, a hard bit sequence of the first type nodes of the sub-tree in the original bit sequence can be obtained, so that the decoding efficiency of the polarization code is improved.

The apparatus is an apparatus to which the above-described polar code decoding processing method is applied, and the implementation of the above-described polar code decoding processing method embodiment is applied to the apparatus, and the same technical effects can be achieved.

Another embodiment of the present invention also provides a readable storage medium, on which a program or instructions are stored, which when executed by a processor implement the steps in the polar code decoding processing method as described above.

Alternatively, the readable storage medium may be a computer readable medium. Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.

It is further noted that the terminals described in this specification include, but are not limited to, smart phones, tablets, etc., and that many of the functional components described are referred to as modules in order to more particularly emphasize their implementation independence.

In embodiments of the present invention, modules may be implemented in software for execution by various types of processors. An identified module of executable code may, for instance, comprise one or more physical or logical blocks of computer instructions which may, for instance, be constructed as an object, procedure, or function. Nevertheless, the executables of an identified module need not be physically located together, but may comprise disparate instructions stored in different bits which, when joined logically together, comprise the module and achieve the stated purpose for the module.

Indeed, a module of executable code may be a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, and across several memory devices. Likewise, operational data may be identified within the modules and may be embodied in any suitable form and organized within any suitable type of data structure. The operational data may be collected as a single data set, or may be distributed over different locations including over different storage devices, and may exist, at least partially, merely as electronic signals on a system or network.

When a module can be implemented by software, considering the level of existing hardware technology, a module implemented by software may build a corresponding hardware circuit to implement a corresponding function, without considering cost, and the hardware circuit may include a conventional Very Large Scale Integration (VLSI) circuit or a gate array and an existing semiconductor such as a logic chip, a transistor, or other discrete components. A module may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices or the like.

The exemplary embodiments described above are described with reference to the drawings, and many different forms and embodiments of the invention may be made without departing from the spirit and teaching of the invention, therefore, the invention is not to be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of elements may be exaggerated for clarity. The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Unless otherwise indicated, a range of values, when stated, includes the upper and lower limits of the range and any subranges therebetween.

While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (22)

1. A method for decoding and processing polar codes, comprising:

receiving polarization code data to be decoded;

according to the incomplete binary tree structure of the polarized code data, path expansion and path metric value updating are carried out on the first type node in the subtree, and path metric value updating is carried out on the second type node in the subtree;

obtaining path metric values of all paths of the subtree after path expansion;

and determining a hard bit sequence of the first type node of the subtree in the original bit sequence according to the path metric value.

2. The method of claim 1, wherein determining the hard bit sequence of the first type node of the sub-tree in the original bit sequence based on the path metric value comprises:

sorting the path metric values;

selecting a target path according to the sorting result, and acquiring a sorting sequence number of a path metric value corresponding to the target path;

and obtaining a hard bit sequence of the first type node of the subtree in the original bit sequence according to the sequence number.

3. The method of claim 2, wherein the ordering the path metric values comprises:

and in the buffer area, the path metric values are sorted bit by bit from small to large.

4. The method of claim 2, wherein the path metric value corresponding to the target path is less than the path metric values of the remaining paths in the extended path.

5. The method of claim 2, wherein obtaining the hard bit sequence of the first type node of the subtree in the original bit sequence according to the permutation sequence number comprises:

determining the sequence number of the target path in the group corresponding to the expanded initial path according to the sequence number;

acquiring a binary indication value of the sequence number in the group;

and determining hard bit sequences of the first type nodes of the subtrees in the original bit sequences one by one from the high order to the low order of the binary indicated value.

6. The method according to claim 5, wherein the determining, according to the sequence number, that the target path corresponds to the sequence number in the group after the initial path expansion comprises:

by said permutation of serial number pairs

Obtaining remainder, and taking the obtained remainder as the serial number of the target path in the group corresponding to the expanded initial path; wherein，N_repIs the number of nodes of the first type in the subtree.

7. The method according to claim 1, wherein the buffer area corresponding to the path metric value has the same number of initial regions as the number of initial paths in the initial state;

in the path expansion process, each path expansion divides each current area into two equal areas, and corresponding path metric value expansion is stored at the first position of the expanded area.

8. The method of claim 7 wherein the number of initial path metric values is the same as the initial number of paths.

9. A coding apparatus comprising a memory, a processor, and a computer program stored on the memory and executable on the processor; wherein the processor implements the following steps when executing the program:

receiving polarization code data to be decoded;

according to the incomplete binary tree structure of the polarized code data, path expansion and path metric value updating are carried out on the first type node in the subtree, and path metric value updating is carried out on the second type node in the subtree;

obtaining path metric values of all paths of the subtree after path expansion;

and determining a hard bit sequence of the first type node of the subtree in the original bit sequence according to the path metric value.

10. The decoding device of claim 9, wherein the processor is further configured to:

sorting the path metric values;

selecting a target path according to the sorting result, and acquiring a sorting sequence number of a path metric value corresponding to the target path;

and obtaining a hard bit sequence of the first type node of the subtree in the original bit sequence according to the sequence number.

11. The decoding device of claim 10, wherein the processor is further configured to:

and in the buffer area, the path metric values are sorted bit by bit from small to large.

12. The coding apparatus of claim 10, wherein a path metric value corresponding to the target path is less than path metric values of remaining paths in the extension path.

13. The decoding device of claim 10, wherein the processor is further configured to:

determining the sequence number of the target path in the group corresponding to the expanded initial path according to the sequence number;

acquiring a binary indication value of the sequence number in the group;

and determining hard bit sequences of the first type nodes of the subtrees in the original bit sequences one by one from the high order to the low order of the binary indicated value.

14. The decoding device of claim 13, wherein the processor is further configured to:

by said permutation of serial number pairs

Obtaining remainder, and taking the obtained remainder as the serial number of the target path in the group corresponding to the expanded initial path; wherein N is_repIs the number of nodes of the first type in the subtree.

15. The decoding apparatus according to claim 9, wherein the buffer area corresponding to the path metric value has the same number of initial regions as the number of initial paths in an initial state;

in the path expansion process, each path expansion divides each current area into two equal areas, and corresponding path metric value expansion is stored at the first position of the expanded area.

16. The coding apparatus of claim 15, wherein the number of initial path metric values is the same as the initial number of paths.

17. A polar code decoding processing apparatus, comprising:

the receiving module is used for receiving the polarized code data to be decoded;

the first processing module is used for performing path expansion and path metric value updating on a first type node in a subtree and performing path metric value updating on a second type node in the subtree according to the incomplete binary tree structure of the polarized code data;

the second processing module is used for acquiring the path metric values of all paths of the subtree after path expansion;

and the third processing module is used for determining a hard bit sequence of the first type node of the subtree in the original bit sequence according to the path metric value.

18. The apparatus of claim 17, wherein the third processing module comprises:

the ordering submodule is used for ordering the path metric values;

the first processing submodule is used for selecting a target path according to the sorting result and acquiring the arrangement serial number of the path metric value corresponding to the target path;

and the second processing sub-module is used for obtaining a hard bit sequence of the first type node of the subtree in the original bit sequence according to the arrangement sequence number.

19. The apparatus of claim 18, wherein the ordering sub-module is further configured to:

and in the buffer area, the path metric values are sorted bit by bit from small to large.

20. The apparatus of claim 18 wherein the path metric value corresponding to the target path is less than the path metric values of the remaining paths in the extended path.

21. The apparatus of claim 18, wherein the first processing sub-module comprises:

a determining unit, configured to determine, according to the sequence number, an intra-group sequence number of the target path after the initial path expansion;

an obtaining unit, configured to obtain a binary indication value of the sequence number in the group;

and the processing unit is used for determining the hard bit sequences of the first type nodes of the subtrees in the original bit sequences one by one from the high order to the low order of the binary indicated value.

22. A readable storage medium having a program or instructions stored thereon, wherein the program or instructions, when executed by a processor, implement the steps of the polar code decoding processing method according to any one of claims 1 to 8.

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