CN113629136B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN113629136B
CN113629136B CN202010373428.6A CN202010373428A CN113629136B CN 113629136 B CN113629136 B CN 113629136B CN 202010373428 A CN202010373428 A CN 202010373428A CN 113629136 B CN113629136 B CN 113629136B
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layer
aluminum
semiconductor structure
metal
forming
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CN113629136A (en
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张钦彤
石峰
刘源
贾楠
刘自瑞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

The application provides a semiconductor structure and a forming method thereof, wherein the semiconductor structure comprises: a semiconductor substrate; a gate dielectric layer and a metal gate electrode which are sequentially positioned on the semiconductor substrate; alumina barrier layers at the bottom and on both sides of the metal gate; aluminum films at the bottom and sidewalls of the aluminum oxide barrier layer; and side walls positioned on two sides of the gate dielectric layer and the aluminum film. The semiconductor structure and the forming method thereof have the advantages that the preparation method is simple, the production efficiency can be improved, the product particle defects are reduced, and the grid threshold voltage can be controlled by controlling the thickness of the aluminum film.

Description

Semiconductor structure and forming method thereof
Technical Field
The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the continuous development of semiconductor technology, the semiconductor technology has penetrated into various fields in life, such as aerospace, medical device ring and mobile phone communication, without separating chips prepared by the semiconductor technology. An important component of semiconductor devices is the metal gate, however, metal atoms in the metal gate diffuse into the gate dielectric layer affecting the threshold voltage of the device, and thus a barrier layer is required to control the diffusion of the metal atoms to control the threshold voltage.
However, the barrier layer formation process in the gate structure of the current semiconductor device still has a problem of difficult control, and it is required to provide a more effective or reliable technical solution.
Disclosure of Invention
The application provides a semiconductor structure and a forming method thereof, which can control gate threshold voltage and improve production efficiency.
One aspect of the present application provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, wherein a gate dielectric layer, a pseudo gate layer and side walls positioned on two sides of the gate dielectric layer and the pseudo gate layer are sequentially formed on the semiconductor substrate; removing the pseudo gate layer to form an opening; forming an aluminum film at the bottom and the side wall of the opening; forming an alumina barrier layer on the surface of the aluminum film; and forming a metal grid on the surface of the alumina barrier layer, wherein the metal grid fills the opening.
In some embodiments of the present application, the aluminum film has a thickness of 25 to 35 angstroms.
In some embodiments of the present application, the method for forming an aluminum oxide barrier layer on the surface of the aluminum film includes: exposing the semiconductor structure to air to oxidize the aluminum film surface to form the aluminum oxide barrier layer.
In some embodiments of the present application, the method for forming an aluminum oxide barrier layer on the surface of the aluminum film includes: disposing the semiconductor structure in a reaction chamber; and introducing oxygen into the reaction cavity to oxidize the surface of the aluminum film to form the aluminum oxide barrier layer.
In some embodiments of the present application, the alumina barrier layer has a thickness of 10 to 20 angstroms.
In some embodiments of the present application, the metal gate includes a titanium aluminum layer, a titanium nitride layer, a titanium metal layer, and an aluminum metal layer sequentially on the surface of the aluminum oxide barrier layer.
In some embodiments of the present application, the method for forming a semiconductor structure further includes: and forming a cap layer on the surface of the gate dielectric layer, wherein the cap layer comprises a titanium metal layer positioned on the surface of the gate dielectric layer and a titanium nitride-rich titanium nitride layer positioned on the surface of the titanium metal layer.
Another aspect of the present application also provides a semiconductor structure, comprising: a semiconductor substrate; a gate dielectric layer and a metal gate electrode which are sequentially positioned on the semiconductor substrate; alumina barrier layers at the bottom and on both sides of the metal gate; aluminum films at the bottom and sidewalls of the aluminum oxide barrier layer; and side walls positioned on two sides of the gate dielectric layer and the aluminum film.
In some embodiments of the present application, the metal gate includes a titanium aluminum layer, a titanium nitride layer, a titanium metal layer, and an aluminum metal layer sequentially on the surface of the aluminum oxide barrier layer.
In some embodiments of the present application, the aluminum film has a thickness of 5 to 25 angstroms.
In some embodiments of the present application, the alumina barrier layer has a thickness of 10 to 20 angstroms.
In some embodiments of the present application, the semiconductor structure further comprises: and the capping layer is positioned on the surface of the gate dielectric layer and comprises a titanium metal layer positioned on the surface of the gate dielectric layer and a titanium nitride-rich titanium nitride layer positioned on the surface of the titanium metal layer.
The semiconductor structure and the forming method thereof have the advantages that the preparation method is simple, the production efficiency can be improved, the product particle defects are reduced, and the grid threshold voltage can be controlled by controlling the thickness of the aluminum film.
Drawings
The following figures describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals refer to like structure throughout the several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description purposes only and are not intended to limit the scope of the present application, other embodiments may equally well accomplish the intent of the invention in this application. It should be understood that the drawings are not to scale. Wherein:
fig. 1 to 10 are schematic structural diagrams illustrating steps in a method for forming a semiconductor structure according to an embodiment of the present application.
Detailed Description
The following description provides specific applications and requirements to enable any person skilled in the art to make and use the teachings of the present application. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical scheme of the invention is described in detail below with reference to the examples and the accompanying drawings.
In some current metal gate structures, tantalum nitride is typically used as a barrier layer, which is typically prepared using atomic layer deposition. However, due to the nature of the tantalum nitride material and the technical characteristics of the atomic layer deposition method, the tantalum nitride barrier layer prepared by the method is easy to generate particle defects, the means for monitoring the preparation process in the production process are few, the control is difficult, in addition, the production efficiency is lower, and the preparation cost is higher.
Based on the above problems, the present application provides a method for forming a semiconductor structure, which uses an alumina material as a barrier layer, wherein the alumina is formed by oxidizing an aluminum film, and the method is simple in preparation, low in cost, high in production efficiency, easy to control, and capable of reducing particle defects.
The embodiment of the application provides a method for forming a semiconductor structure, which comprises the following steps: referring to fig. 4, a semiconductor substrate 100 is provided, and a gate dielectric layer 110 and a dummy gate layer 120, and side walls 130 located at two sides of the gate dielectric layer 110 and the dummy gate layer 120 are sequentially formed on the semiconductor substrate 100; referring to fig. 6, the dummy gate layer 120 is removed to form an opening 121; referring to fig. 7, an aluminum film 150 is formed at the bottom and side walls of the opening 121; referring to fig. 8, an alumina barrier layer 160 is formed on the surface of the aluminum film 150; referring to fig. 9, a metal gate 170 is formed on the surface of the alumina barrier layer 160, and the metal gate 170 fills the opening 121.
Fig. 1 to 10 are schematic structural diagrams illustrating steps in a method for forming a semiconductor structure according to an embodiment of the present application. The semiconductor structure is, for example, an NMOS device.
Referring to fig. 1, a semiconductor substrate 100 is provided. The material of the semiconductor substrate 100 may be silicon (Si), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The semiconductor substrate 100 may also be a structure grown with an epitaxial layer.
Referring to fig. 2, a gate dielectric material layer 110a and a dummy gate material layer 120a are sequentially formed on the semiconductor substrate 100. In some embodiments of the present application, the method of forming the gate dielectric material layer 110a and the dummy gate material layer 120a includes a chemical vapor deposition process or a physical vapor deposition process, etc.
Referring to fig. 3, the gate dielectric material layer 110a and the dummy gate material layer 120a are etched to form a gate dielectric layer 110 and a dummy gate layer 120.
In some embodiments of the present application, the method of etching the gate dielectric material layer 110a and the dummy gate material layer 120a includes dry etching or wet etching.
In some embodiments of the present application, the gate dielectric layer 110 may be a composite structure formed of multiple dielectric layers, for example, including a first dielectric layer and a second dielectric layer sequentially on the semiconductor substrate 100. Wherein the material of the first dielectric layer is silicon oxide; the material of the second dielectric layer is, for example, hafnium oxide.
In some embodiments of the present application, the material of the gate dielectric layer 110 may include silicon oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, aluminum oxide, and the like.
In some embodiments of the present application, the material of the dummy gate layer 120 may include polysilicon.
In some embodiments of the present application, the method for forming a semiconductor structure further includes: a cap layer (not shown) is formed on the surface of the gate dielectric layer 120, and the cap layer includes a titanium metal layer on the surface of the gate dielectric layer and a titanium nitride-rich layer on the surface of the titanium metal layer. The double-layer structure of the titanium metal layer and the nitrogen-enriched titanium nitride layer is used as the cap layer, and the problems of high electric leakage, poor thermal stability, low breakdown voltage and the like can not be caused under the condition that the thickness of the equivalent oxide layer is not influenced.
Referring to fig. 4, spacers 130 are formed on both sides of the gate dielectric layer 110 and the dummy gate layer 120. The sidewall 130 may protect the gate dielectric layer 110 and the dummy gate layer 120.
In some embodiments of the present application, the material of the sidewall 130 includes silicon nitride or silicon oxide.
In some embodiments of the present application, the sidewall 130 may have a single-layer structure. In other embodiments of the present application, the sidewall 130 may also be a multi-layer composite structure, such as a silicon oxide-silicon nitride-silicon oxide-silicon nitride structure, or the like.
In some embodiments of the present application, the method for forming the sidewalls 130 on two sides of the gate dielectric layer 110 and the dummy gate layer 120 includes: forming a sidewall material layer on the semiconductor substrate 100 and the dummy gate layer 120; and etching the side wall material layer to form the side wall 130.
In some embodiments of the present application, the method for forming the sidewall material layer on the semiconductor substrate 100 and the dummy gate layer 120 includes a chemical vapor deposition process or a physical vapor deposition process.
In some embodiments of the present application, the method for etching the sidewall material layer to form the sidewall 130 includes wet etching.
Referring to fig. 5, a dielectric layer 140 is formed on the semiconductor substrate 100, and the top of the dielectric layer 140 is flush with the upper surface of the dummy gate layer 120. The dielectric layer 140 may planarize the surface of the semiconductor structure, and improve the accuracy of etching the dummy gate layer 120 in the subsequent process.
In some embodiments of the present application, the method for forming the dielectric layer 140 on the semiconductor substrate 100, where the dielectric layer 140 is flush with the upper surface of the dummy gate layer 120 includes: forming a dielectric layer 140 on the semiconductor substrate 100 and on the dummy gate layer 120 removes the dielectric layer 140 above the upper surface of the dummy gate layer 120 using a chemical mechanical polishing process. The material of the dielectric layer 140 is, for example, silicon oxide.
Referring to fig. 6, the dummy gate layer 120 is removed to form an opening 121. The openings 121 are used to fill the metal gates.
In some embodiments of the present application, the method of removing the dummy gate layer 120 includes wet etching or dry etching.
Referring to fig. 7, an aluminum film 150 is formed at the bottom and side walls of the opening 121. In one aspect, the aluminum film 150 surface may oxidize to form aluminum oxide as a barrier layer to prevent the metal of the metal gate from diffusing into the gate dielectric layer 110; on the other hand, aluminum atoms of the aluminum film 150 may diffuse into the gate dielectric layer 110 to adjust a device threshold voltage. Reasons for selecting the aluminum film include: the work function of the metal aluminum meets the requirement of a metal gate in an NMOS device on the work function; the oxide alumina of metallic aluminum is easily formed; and can be used as a material for blocking the diffusion of metal atoms; the price of metallic aluminum is cheaper.
In the method for forming a semiconductor structure provided in the present application, the threshold voltage may be controlled by controlling the thickness of the aluminum film 150 to control the amount of aluminum atoms diffused into the gate dielectric layer 110, as compared to the difficulty in controlling the diffusion of metal gate metal atoms in conventional semiconductor structure processes. Specifically, the lower the thickness of the aluminum film 150, the fewer aluminum atoms that can diffuse into the gate dielectric layer 110, and the higher the threshold voltage; conversely, the higher the thickness of the aluminum film 150, the more aluminum atoms that can diffuse into the gate dielectric layer 110, and the lower the threshold voltage.
In some embodiments of the present application, the aluminum film 150 has a thickness of 25 to 35 angstroms, for example 25 angstroms, 30 angstroms, 35 angstroms, or the like. Since a portion of the aluminum film 150 is oxidized, the thickness of the aluminum film 150 is slightly thicker than the actual thickness, and a certain thickness is reserved for the subsequent oxidation.
In some embodiments of the present application, the method of forming the aluminum film 150 at the bottom and both sides of the opening 121 includes a physical vapor deposition method. Compared with the atomic layer deposition method for forming the barrier layer in the conventional process, the physical vapor deposition method is easy to control and has higher deposition efficiency. The physical vapor deposition method comprises the following technological parameters: the sputtering power is 1500W to 2500W, and the larger the sputtering power is, the faster the deposition rate is, and the larger the grain size is; the reaction pressure is 1mTorr to 5mTorr, the larger the reaction pressure is, the smaller the grain size is, and the higher the film hardness is; the reaction temperature is 200 degrees celsius to 400 degrees celsius, the higher the reaction temperature, the larger the grain size. In an actual process, specific process parameters may be set as desired.
Referring to fig. 8, an aluminum oxide barrier layer 160 is formed on the surface of the aluminum film 150. Alumina has very stable properties and can prevent diffusion of metal atoms in the metal gate. It should be noted that the dimensional proportion in the drawings does not represent the actual dimensional proportion, but merely for brevity and convenience of description of the positional relationship and shape structure among the structures in the semiconductor structure, for example, the alumina barrier layer 160 is a thin film formed by oxidizing the surface of the aluminum film 150, and the alumina barrier layer 160 is exaggerated in the drawings, so that the alumina barrier layer 160 is more clearly described.
In some embodiments of the present application, the method for forming the aluminum oxide barrier layer 160 on the surface of the aluminum film 150 includes: exposing the semiconductor structure to air oxidizes the surface of the aluminum film 150 to form the aluminum oxide barrier layer 160. The natural oxidation time is greater than 30 minutes. The method utilizes the characteristic that aluminum metal can be naturally oxidized in air to form aluminum oxide, has simple process and does not need extra cost, but the natural oxidation speed is slower, and the production efficiency is lower.
In other embodiments of the present application, the method for forming the aluminum oxide barrier layer 160 on the surface of the aluminum film 150 includes: disposing the semiconductor structure in a reaction chamber; oxygen is introduced into the reaction chamber to oxidize the surface of the aluminum film 150 to form the aluminum oxide barrier layer 160. This method oxidizes the aluminum film 150 to form aluminum oxide by actively supplying oxygen, has a faster oxidation rate and higher production efficiency, and the reaction site is not exposed to air in the reaction chamber, and there is no fear of any unexpected damage to the semiconductor structure, but adds a certain additional cost.
In some embodiments of the present application, the alumina barrier layer 160 has a thickness of 10a to 20a, for example, 10a, 15 a, 20a, or the like. Since a part of the aluminum film is oxidized, the thickness of the remaining aluminum film is 5 to 25 angstroms.
In the method for forming a semiconductor structure provided herein, the threshold voltage may be controlled by controlling the thickness of the alumina barrier layer 160 to control the amount of metal atoms that diffuse from the metal gate electrode into the gate dielectric layer 110. Specifically, the higher the thickness of the alumina barrier layer 160, the greater the ability to block diffusion of metal atoms of the metal gate; conversely, the higher the thickness of the alumina barrier 160, the lower the ability to block diffusion of metal gate metal atoms. In actual production, the oxidation time can be controlled as required to control the thickness of the alumina barrier layer.
In comparison with the conventional method of forming a barrier layer for blocking the diffusion of metal atoms of a metal gate by atomic layer deposition, the method of forming a semiconductor structure provided in the present application can form the aluminum oxide barrier layer 160 which can also block the diffusion of metal atoms of a metal gate by depositing the aluminum film 150 by physical vapor deposition and oxidizing the aluminum film 150. On one hand, compared with an atomic layer deposition method, the physical vapor deposition method has the advantages of simpler oxidation process, higher production efficiency and lower cost; on the other hand, the physical vapor deposition method can reduce product particle defects and improve the reliability of the device; in addition, the thicknesses of the aluminum film 150 and the aluminum oxide barrier layer 160 may be well controlled in the physical vapor deposition process, thereby controlling the amount of metal atoms diffused into the gate dielectric layer 110, and thus controlling the device threshold voltage.
Referring to fig. 9, a metal gate 170 is formed on the surface of the alumina barrier 160, and the metal gate 170 fills the opening 121.
In some embodiments of the present application, the metal gate 170 may be a multi-layer composite structure, and the metal gate 170 may include a titanium aluminum layer, a titanium nitride layer, a titanium metal layer, and an aluminum metal layer sequentially disposed on the surface of the aluminum oxide barrier layer 170. The titanium aluminum layer and titanium nitride layer may adjust the work function of the metal gate 170, the titanium metal layer serves as an adhesion layer between the aluminum metal layer and the titanium nitride layer, and the aluminum metal layer is a gate main structure. In some embodiments of the present application, the method of forming the titanium aluminum layer, titanium nitride layer, titanium metal layer, and aluminum metal layer includes a physical vapor deposition method.
Referring to fig. 10, an interlayer dielectric layer 180 is formed on the dielectric layer 140, the sidewall 130 and the metal gate 170, and a contact structure 190 penetrating the interlayer dielectric layer 180 and electrically connecting the metal gate 170 is formed in the interlayer dielectric layer 180.
In some embodiments of the present application, the material of the interlayer dielectric layer 180 includes silicon oxide.
In some embodiments of the present application, the material of the contact structure 190 is a metal, such as tungsten or copper or aluminum.
In some embodiments of the present application, the method of forming the interlayer dielectric layer 190 includes a chemical vapor deposition process, a physical vapor deposition process, or the like.
On one hand, compared with an atomic layer deposition method, the physical vapor deposition method and the oxidation process are simpler, the production efficiency is higher, and the cost is lower; on the other hand, the physical vapor deposition method can reduce product particle defects and improve the reliability of the device; in addition, the thicknesses of the aluminum film 150 and the aluminum oxide barrier layer 160 may be well controlled in the physical vapor deposition process, thereby controlling the amount of metal atoms diffused into the gate dielectric layer 110, and thus controlling the device threshold voltage.
Embodiments of the present application also provide a semiconductor structure, referring to fig. 10, comprising: a semiconductor substrate 100; a gate dielectric layer 110, a metal gate 170, which are sequentially located on the semiconductor substrate 100; an alumina barrier layer 160 located at the bottom and both sides of the metal gate 170; an aluminum film 150 at the bottom and sidewalls of the aluminum oxide barrier layer 160; and side walls 130 positioned on both sides of the gate dielectric layer 110 and the aluminum film 150.
As shown in fig. 10, the material of the semiconductor substrate 100 may be silicon (Si), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The semiconductor substrate 100 may also be a structure grown with an epitaxial layer.
With continued reference to fig. 10, the gate dielectric layer 110 may be a composite structure formed of multiple dielectric layers, including, for example, a first dielectric layer and a second dielectric layer sequentially on the semiconductor substrate 100. Wherein the material of the first dielectric layer is silicon oxide; the material of the second dielectric layer is, for example, hafnium oxide.
In some embodiments of the present application, the material of the gate dielectric layer 110 may include silicon oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, aluminum oxide, and the like.
In some embodiments of the present application, the semiconductor structure further comprises: a capping layer (not shown) is disposed on the surface of the gate dielectric layer 120, and the capping layer includes a titanium metal layer disposed on the surface of the gate dielectric layer and a titanium nitride-rich layer disposed on the surface of the titanium metal layer. The double-layer structure of the titanium metal layer and the nitrogen-enriched titanium nitride layer is used as the cap layer, and the problems of high electric leakage, poor thermal stability, low breakdown voltage and the like can not be caused under the condition that the thickness of the equivalent oxide layer is not influenced.
With continued reference to fig. 10, sidewalls 130 are formed on both sides of the gate dielectric layer 110 and the gate structure. The sidewall 130 may protect the gate dielectric layer 110 and the gate structure.
In some embodiments of the present application, the material of the sidewall 130 includes silicon nitride or silicon oxide.
In some embodiments of the present application, the sidewall 130 may have a single-layer structure. In other embodiments of the present application, the sidewall 130 may also be a multi-layer composite structure, such as a silicon oxide-silicon nitride-silicon oxide-silicon nitride structure, or the like.
With continued reference to fig. 10, a dielectric layer 140 is formed on the semiconductor substrate 100, and the top of the dielectric layer 140 is flush with the upper surface of the gate structure.
With continued reference to fig. 10, aluminum atoms of the aluminum film 150 may diffuse into the gate dielectric layer 110 to adjust the device threshold voltage. In contrast to conventional semiconductor structures, which have difficulty controlling the diffusion of metal atoms of the metal gate, the semiconductor structure provided herein can control the amount of aluminum atoms diffused into the gate dielectric layer 110 by controlling the thickness of the aluminum film 150, thereby controlling the threshold voltage. Specifically, the lower the thickness of the aluminum film 150, the fewer aluminum atoms that can diffuse into the gate dielectric layer 110, and the higher the threshold voltage; conversely, the higher the thickness of the aluminum film 150, the more aluminum atoms that can diffuse into the gate dielectric layer 110, and the lower the threshold voltage. Reasons for selecting the aluminum film include: the work function of the metal aluminum meets the requirement of a metal gate in an NMOS device on the work function; the oxide alumina of metallic aluminum is easily formed; and can be used as a material for blocking the diffusion of metal atoms; the price of metallic aluminum is cheaper.
In some embodiments of the present application, the aluminum film 150 has a thickness of 25 to 35 angstroms, for example 25 angstroms, 30 angstroms, 35 angstroms, or the like. Since a portion of the aluminum film 150 is oxidized, the thickness of the aluminum film 150 is slightly thicker than the actual thickness, and a certain thickness is reserved for the subsequent oxidation.
With continued reference to fig. 10, an aluminum oxide barrier layer 160 is formed on the surface of the aluminum film 150. Alumina has very stable properties and can prevent diffusion of metal atoms in the metal gate. It should be noted that the dimensional proportion in the drawings does not represent the actual dimensional proportion, but merely for brevity and convenience of description of the positional relationship and shape structure among the structures in the semiconductor structure, for example, the alumina barrier layer 160 is a thin film formed by oxidizing the surface of the aluminum film 150, and the alumina barrier layer 160 is exaggerated in the drawings, so that the alumina barrier layer 160 is more clearly described.
In some embodiments of the present application, the alumina barrier layer 160 has a thickness of 5 a to 25 a, such as 5 a, 10a, 15 a, 20a, 25 a, or the like. The semiconductor structure provided herein can control the threshold voltage by controlling the amount of metal atoms that diffuse from the metal gate into the gate dielectric layer 110 by controlling the thickness of the aluminum oxide barrier layer 160. Specifically, the higher the thickness of the alumina barrier layer 160, the greater the ability to block diffusion of metal atoms of the metal gate; conversely, the higher the thickness of the alumina barrier 160, the lower the ability to block diffusion of metal gate metal atoms. In actual production, the oxidation time can be controlled as required to control the thickness of the alumina barrier layer.
In the semiconductor structure provided by the application, the thickness of the aluminum film 150 and the aluminum oxide barrier layer 160 can be well controlled, so that the amount of metal atoms diffused into the gate dielectric layer 110 can be controlled, and the threshold voltage of the device can be controlled.
With continued reference to fig. 10, a metal gate 170 is formed on the surface of the aluminum oxide barrier 160.
In some embodiments of the present application, the metal gate 170 may be a multi-layer composite structure, and the metal gate 170 may include a titanium aluminum layer, a titanium nitride layer, a titanium metal layer, and an aluminum metal layer sequentially disposed on the surface of the aluminum oxide barrier layer 170. The titanium aluminum layer and titanium nitride layer may adjust the work function of the metal gate 170, the titanium metal layer serves as an adhesion layer between the aluminum metal layer and the titanium nitride layer, and the aluminum metal layer is a gate main structure.
With continued reference to fig. 10, an interlayer dielectric layer 180 is formed on the dielectric layer 140, the sidewall 130 and the metal gate 170, and a contact structure 190 penetrating the interlayer dielectric layer 180 and electrically connecting the metal gate 170 is formed in the interlayer dielectric layer 180.
In some embodiments of the present application, the material of the interlayer dielectric layer 180 includes silicon oxide.
In some embodiments of the present application, the material of the contact structure 190 is a metal, such as tungsten or copper or aluminum.
In the semiconductor structure described herein, the thickness of the aluminum film 150 and the aluminum oxide barrier layer 160 can be well controlled, thereby controlling the amount of metal atoms that diffuse into the gate dielectric layer 110, and thus controlling the device threshold voltage.
In view of the foregoing, it will be evident to those skilled in the art after reading this application that the foregoing application may be presented by way of example only and may not be limiting. Although not explicitly described herein, those skilled in the art will appreciate that the present application is intended to embrace a variety of reasonable alterations, improvements and modifications to the embodiments. Such alterations, improvements, and modifications are intended to be within the spirit and scope of the exemplary embodiments of the present application.
It should be understood that the term "and/or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means without intermediate elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present application. Like reference numerals or like reference numerals designate like elements throughout the specification.
Furthermore, the present specification describes example embodiments by reference to idealized example cross-sectional and/or plan and/or perspective views. Thus, differences from the illustrated shapes, due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

Claims (10)

1. A method of forming a semiconductor structure, comprising:
providing a semiconductor substrate, wherein a gate dielectric layer, a pseudo gate layer and side walls positioned on two sides of the gate dielectric layer and the pseudo gate layer are sequentially formed on the semiconductor substrate;
removing the pseudo gate layer to form an opening;
forming an aluminum film at the bottom and the side wall of the opening;
forming an alumina barrier layer on the surface of the aluminum film;
and forming a metal grid electrode on the surface of the alumina barrier layer, wherein the metal grid electrode fills the opening, and the metal grid electrode comprises a titanium aluminum layer, a titanium nitride layer, a titanium metal layer and an aluminum metal layer which are sequentially positioned on the surface of the alumina barrier layer.
2. The method of forming a semiconductor structure of claim 1, wherein the aluminum film has a thickness of 25 to 35 angstroms.
3. The method of forming a semiconductor structure of claim 1, wherein the method of forming an aluminum oxide barrier layer on the aluminum film surface comprises: exposing the semiconductor structure to air to oxidize the aluminum film surface to form the aluminum oxide barrier layer.
4. The method of forming a semiconductor structure of claim 1, wherein the method of forming an aluminum oxide barrier layer on the aluminum film surface comprises: disposing the semiconductor structure in a reaction chamber; and introducing oxygen into the reaction cavity to oxidize the surface of the aluminum film to form the aluminum oxide barrier layer.
5. The method of forming a semiconductor structure of claim 1, wherein the aluminum oxide barrier layer has a thickness of 10 to 20 angstroms.
6. The method of forming a semiconductor structure of claim 1, further comprising: and forming a cap layer on the surface of the gate dielectric layer, wherein the cap layer comprises a titanium metal layer positioned on the surface of the gate dielectric layer and a titanium nitride-rich titanium nitride layer positioned on the surface of the titanium metal layer.
7. A semiconductor structure, comprising:
a semiconductor substrate;
the metal grid comprises a titanium aluminum layer, a titanium nitride layer, a titanium metal layer and an aluminum metal layer which are sequentially positioned on the surface of the aluminum oxide barrier layer;
alumina barrier layers at the bottom and on both sides of the metal gate;
aluminum films at the bottom and sidewalls of the aluminum oxide barrier layer; and
and the side walls are positioned at two sides of the gate dielectric layer and the aluminum film.
8. The semiconductor structure of claim 7, wherein the aluminum film has a thickness of 5 to 25 angstroms.
9. The semiconductor structure of claim 7, wherein the aluminum oxide barrier layer has a thickness of 10 to 20 angstroms.
10. The semiconductor structure of claim 7, further comprising: and the capping layer is positioned on the surface of the gate dielectric layer and comprises a titanium metal layer positioned on the surface of the gate dielectric layer and a titanium nitride-rich titanium nitride layer positioned on the surface of the titanium metal layer.
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Publication number Priority date Publication date Assignee Title
CN103579175A (en) * 2012-07-25 2014-02-12 台湾积体电路制造股份有限公司 Copper contact plugs with barrier layers
CN108074816A (en) * 2016-11-18 2018-05-25 中芯国际集成电路制造(上海)有限公司 Transistor and forming method thereof
CN108155235A (en) * 2016-12-02 2018-06-12 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN109616515A (en) * 2018-11-26 2019-04-12 上海集成电路研发中心有限公司 A kind of metal gate structure and its manufacturing method
CN110310889A (en) * 2018-03-27 2019-10-08 台湾积体电路制造股份有限公司 Method for patterning the layer containing lanthanum

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Publication number Priority date Publication date Assignee Title
CN103579175A (en) * 2012-07-25 2014-02-12 台湾积体电路制造股份有限公司 Copper contact plugs with barrier layers
CN108074816A (en) * 2016-11-18 2018-05-25 中芯国际集成电路制造(上海)有限公司 Transistor and forming method thereof
CN108155235A (en) * 2016-12-02 2018-06-12 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
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