CN113629008A - Preparation method of semiconductor device and semiconductor device - Google Patents

Preparation method of semiconductor device and semiconductor device Download PDF

Info

Publication number
CN113629008A
CN113629008A CN202110902056.6A CN202110902056A CN113629008A CN 113629008 A CN113629008 A CN 113629008A CN 202110902056 A CN202110902056 A CN 202110902056A CN 113629008 A CN113629008 A CN 113629008A
Authority
CN
China
Prior art keywords
substrate
layer
seed layer
interlayer insulating
silicon seed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202110902056.6A
Other languages
Chinese (zh)
Other versions
CN113629008B (en
Inventor
上官明沁
吕佐文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujian Jinhua Integrated Circuit Co Ltd
Original Assignee
Fujian Jinhua Integrated Circuit Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujian Jinhua Integrated Circuit Co Ltd filed Critical Fujian Jinhua Integrated Circuit Co Ltd
Priority to CN202110902056.6A priority Critical patent/CN113629008B/en
Publication of CN113629008A publication Critical patent/CN113629008A/en
Application granted granted Critical
Publication of CN113629008B publication Critical patent/CN113629008B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The preparation method comprises the steps of placing a substrate in a reaction chamber, heating the substrate, and introducing a first reaction gas into the reaction chamber to form a silicon seed layer covering the inner wall of a contact hole and the upper surface of a first interlayer insulating layer; wherein the first reaction gas at least comprises one of di-sec-butylaminosilane and di-tert-butylaminosilane; and continuously heating the substrate, and introducing a second reaction gas into the reaction chamber to form a phosphorus-doped silicon layer covering the surface of the silicon seed layer, which is far away from the substrate. The amino ligands in the di-sec-butylaminosilane (DSBAS) and the di-tert-butylaminosilane (DTBAS) have larger sizes, so that the incubation period can be greatly shortened when the phosphorus doped silicon layer grows above the formed silicon seed layer, and the possibility that the phosphorus doped silicon layer forms defects such as holes, cracks and the like at the side wall position of the contact hole is greatly reduced.

Description

Preparation method of semiconductor device and semiconductor device
Technical Field
The application relates to the technical field of semiconductor devices, in particular to a preparation method of a semiconductor device and the semiconductor device.
Background
With the trend of miniaturization of various electronic products, the design of Dynamic Random Access Memory (DRAM) must meet the requirements of high integration and high density. For the dram with the recessed gate structure, it has gradually replaced the dram with only the planar gate structure because it can obtain a longer carrier channel length in the same semiconductor substrate.
Generally, a DRAM having a recessed gate structure is formed by a large number of memory cells (memory cells 11) grouped together to form an array region for storing data, and each memory cell may be composed of a transistor device connected in series with a charge storage device to receive voltage signals from a Word Line (WL) and a Bit Line (BL). The bit line structure is electrically connected with the gate structure and the active pattern on the substrate through a bit line plug, the bit line plug is arranged in a contact hole on the surface of the substrate and comprises a seed crystal layer and a semiconductor layer, and the bit line plug is formed by filling the seed crystal layer and the semiconductor layer in the contact hole and then patterning.
With the increase of the demand of DRAM integration, the aspect ratio of the contact hole needs to be increased, and in this case, when the semiconductor layer is formed, defects such as voids and cracks are easily generated at the sidewall position of the contact hole, which easily causes problems such as bit line short circuit, and affects the electrical performance of the semiconductor device.
Disclosure of Invention
In order to solve the problems, the application provides a preparation method of a semiconductor device and the semiconductor device, and solves the technical problem that in the prior art, a semiconductor layer is easy to generate defects such as cavities and cracks at a position close to a contact hole.
In a first aspect, the present application provides a method for manufacturing a semiconductor device, including:
providing a semiconductor substrate, and forming a first interlayer insulating layer over the substrate;
forming a contact hole penetrating the first interlayer insulating layer and extending to the inside of the substrate; wherein the contact hole exposes a portion of the substrate and a portion of the first interlayer insulating layer;
placing the substrate in a reaction chamber, heating the substrate, and introducing a first reaction gas into the reaction chamber to form a silicon seed layer covering the inner wall of the contact hole and the upper surface of the first interlayer insulating layer; wherein the first reaction gas at least comprises one of di-sec-butylaminosilane and di-tert-butylaminosilane;
and continuously heating the substrate, and introducing a second reaction gas into the reaction chamber to form a phosphorus-doped silicon layer covering the surface of the silicon seed layer, which is far away from the substrate.
According to an embodiment of the present application, optionally, in the above method for manufacturing a semiconductor device, the step of placing the substrate in a reaction chamber, heating the substrate, and introducing a first reaction gas into the reaction chamber to form a silicon seed layer covering an inner wall of the contact hole and an upper surface of the first interlayer insulating layer includes:
and placing the substrate in a reaction chamber, heating the substrate, and introducing a first reaction gas into the reaction chamber to form a silicon seed layer covering the inner wall of the contact hole and the upper surface of the first interlayer insulating layer in an atomic layer deposition mode.
According to an embodiment of the present application, optionally, in the above method for manufacturing a semiconductor device, the silicon seed layer has a thickness on the order of an atomic size.
According to an embodiment of the present application, optionally, in the above method for manufacturing a semiconductor device, a thickness of a portion of the silicon seed layer in contact with the substrate is larger than a thickness of a portion in contact with the first interlayer insulating layer.
According to an embodiment of the present application, optionally, in the above method for manufacturing a semiconductor device, the silicon seed layer is an amorphous silicon seed layer.
According to an embodiment of the application, optionally, in the above method for manufacturing a semiconductor device, the second reaction gas includes silane and phosphane which do not include an amino group.
According to an embodiment of the present application, optionally, in the above method for manufacturing a semiconductor device, a total thickness of the silicon seed layer and the phosphorus-doped silicon layer is greater than or equal to a depth of the contact hole.
According to an embodiment of the application, optionally, in the above method for manufacturing a semiconductor device, after the step of forming the phosphorus-doped silicon layer covering the surface of the silicon seed layer away from the substrate, the method further includes:
carrying out planarization treatment on the phosphorus-doped silicon layer;
forming a bit line stack over the phosphorous doped silicon layer after planarization;
patterning the silicon seed layer, the flattened phosphorus-doped silicon layer and the bit line lamination layer to respectively obtain a bit line contact plug and a bit line structure; wherein the bit line structure is electrically connected with the substrate through the bit line contact plug.
According to an embodiment of the present application, optionally, in the above method for manufacturing a semiconductor device, before the step of forming the first interlayer insulating layer over the substrate, the method further includes:
forming a plurality of active patterns arranged at intervals along a first direction in the upper surface of the substrate; wherein each active pattern is isolated by an isolation pattern;
forming a plurality of trench gate structures arranged at intervals along a second direction in the upper surface of the substrate; wherein each of the trench gate structures intersects at least one of the active patterns.
In a second aspect, the present application provides a semiconductor device fabricated using the method of any one of the first aspects.
Compared with the prior art, one or more embodiments in the above scheme can have the following advantages or beneficial effects:
the application provides a preparation method of a semiconductor device and the semiconductor device, wherein the preparation method comprises the steps of providing a semiconductor substrate, and forming a first interlayer insulating layer above the substrate; forming a contact hole penetrating the first interlayer insulating layer and extending to the inside of the substrate; wherein the contact hole exposes a portion of the substrate and a portion of the first interlayer insulating layer; placing the substrate in a reaction chamber, heating the substrate, and introducing a first reaction gas into the reaction chamber to form a silicon seed layer covering the inner wall of the contact hole and the upper surface of the first interlayer insulating layer; wherein the first reaction gas at least comprises one of di-sec-butylaminosilane and di-tert-butylaminosilane; and continuously heating the substrate, and introducing a second reaction gas into the reaction chamber to form a phosphorus-doped silicon layer covering the surface of the silicon seed layer, which is far away from the substrate. The silicon seed layer is formed by at least one of di-sec-butylaminosilane (DSBAS) and di-tert-butylaminosilane (DTBAS), the amino ligands in the di-sec-butylaminosilane (DSBAS) and the di-tert-butylaminosilane (DTBAS) have larger sizes, so that the incubation period can be greatly shortened when a phosphorus doped silicon layer is grown on the formed silicon seed layer, the roughness and the coverage rate of the phosphorus doped silicon layer can be greatly improved, and the possibility that the phosphorus doped silicon layer forms defects such as holes, cracks and the like at the side wall position of the contact hole is greatly reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application and not to limit the application. In the drawings:
fig. 1 is a schematic flow chart illustrating a method of fabricating a semiconductor device according to an exemplary embodiment of the present application;
FIG. 2 is a schematic top plan view of a first intermediate structure formed at a step associated with a method of fabricating a semiconductor device, as illustrated in one exemplary embodiment of the present application;
FIG. 3 is a schematic cross-sectional view of FIG. 2 taken along lines A-A 'and B-B', respectively;
FIG. 4 is a schematic top plan view of a second intermediate structure formed at a step associated with a method of fabricating a semiconductor device as illustrated in an exemplary embodiment of the present application;
FIG. 5 is a schematic cross-sectional view of FIG. 4 taken along lines A-A 'and B-B', respectively;
FIG. 6 is a cross-sectional structural view of a third intermediate structure formed at a step associated with a method of fabricating a semiconductor device, as illustrated in an exemplary embodiment of the present application;
FIG. 7 is a schematic top plan view of a fourth intermediate structure formed during a step associated with one method of fabricating a semiconductor device, as illustrated in one exemplary embodiment of the present application;
FIG. 8 is a schematic cross-sectional view of FIG. 7 taken along lines A-A 'and B-B', respectively;
FIG. 9 is a schematic diagram illustrating a top view of a front side of a semiconductor device in accordance with an exemplary embodiment of the present application;
FIG. 10 is a schematic cross-sectional view of FIG. 9 taken along lines A-A 'and B-B', respectively;
in the drawings, wherein like parts are designated with like reference numerals, the drawings are not necessarily to scale;
the reference signs are:
101-a substrate; 1011-active pattern; 102-an isolation pattern; 103-a trench gate structure; 1031-gate insulating layer; 1032-a gate; 1033 — a second interlayer insulating layer; 104-a first interlayer insulating layer; 105-a contact hole; 1061-a seed layer; 1062-a semiconductor layer; 1071 — a barrier layer; 1072-metal layer.
Detailed Description
The following detailed description will be provided with reference to the accompanying drawings and embodiments, so that how to apply the technical means to solve the technical problems and achieve the corresponding technical effects can be fully understood and implemented. The embodiments and various features in the embodiments of the present application can be combined with each other without conflict, and the formed technical solutions are all within the scope of protection of the present application. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
It will be understood that spatial relationship terms, such as "above", "below", "beneath", and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" other elements would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the present application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.
In order to provide a thorough understanding of the present application, detailed structures and steps will be provided in the following description in order to explain the technical solutions proposed in the present application. The following detailed description of the preferred embodiments of the present application, however, will suggest that the present application may have other embodiments in addition to these detailed descriptions.
The embodiment provides a method for manufacturing a semiconductor device. Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 2-8 are schematic diagrams of a top view and a cross-sectional structure of a semiconductor device according to an embodiment of the present disclosure. Next, detailed steps of an exemplary method of a method of manufacturing a semiconductor device proposed by an embodiment of the present application are described with reference to fig. 1 and fig. 2 to 8.
As shown in fig. 1, the method for manufacturing a semiconductor device of the present embodiment includes the following steps:
step S110: a semiconductor substrate 101 is provided, and a first interlayer insulating layer 104 is formed over the substrate 101.
In step S110, before the step of forming the first interlayer insulating layer 104 over the substrate 101, the method further includes:
(a) forming a plurality of active patterns 1011 spaced apart in a first direction in an upper surface of the substrate 101; wherein, each active pattern 1011 is isolated by the isolation pattern 102;
(b) forming a plurality of trench gate structures 103 arranged at intervals along a second direction in the upper surface of the substrate 101; wherein each trench gate structure 103 intersects at least one active pattern 1011.
A plurality of active patterns 1011 are disposed on the substrate 101 at intervals, each of the active patterns 1011 is parallel to each other and disposed along a first direction, the active patterns 1011 are formed by forming doped regions (not shown) by ion implantation, and an upper surface of the active patterns 1011 is flush with an upper surface of the substrate 101. The active patterns 1011 in two adjacent rows are staggered, and the active patterns 1011 in two adjacent columns are staggered.
Each of the active patterns 1011 is isolated therefrom by an isolation pattern 102, and the isolation pattern 102 serves to define the shape of the active pattern 1011.
A plurality of trench gate structures 103 are disposed on the substrate 101 at intervals, each trench gate structure 103 is parallel to each other and disposed along a second direction (a transverse direction as shown in fig. 2), each trench gate structure 103 intersects at least one active pattern 1011, and exemplarily, each trench gate structure 103 intersects two corresponding rows of active patterns 1011 as shown in fig. 2. The trench gate structure 103 includes a trench, a gate insulating layer 1031 disposed on the sidewall and bottom of the trench, and a gate electrode 1032 and a second interlayer insulating layer 1033 filled in the lower and upper portions of the trench, respectively. The thickness of the gate is less than the depth of the trench, but the top of the gate 1032 is higher than the bottom of the doped region (not shown) in the active pattern 1011. The second interlayer insulating layer 1033 is formed of, for example, a silicon nitride layer and/or a silicon oxynitride layer.
The first interlayer insulating layer 104 is disposed over the substrate 101 and covers the active pattern 1011 and the trench gate structure 103, and a material of the first interlayer insulating layer 104 includes at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.
Step S120: as shown in fig. 2 and 3, a contact hole 105 penetrating the first interlayer insulating layer 104 and extending to the inside of the substrate 101 is formed; wherein the contact hole 105 exposes a portion of the substrate 101 and a portion of the first interlayer insulating layer 104.
The contact hole 105 penetrates the first interlayer insulating layer 104 and extends into the active pattern 1011, the isolation pattern 102, and the trench gate structure 103. The contact hole 105 exposes a portion of the substrate 101 and a portion of the first interlayer insulating layer 104 for subsequent deposition of a film layer.
Step S130: as shown in fig. 4 and 5, the substrate 101 is placed in a reaction chamber, the substrate 101 is heated, and a first reaction gas is introduced into the reaction chamber to form a silicon seed layer 1061 covering the inner wall of the contact hole 105 and the upper surface of the substrate 101; wherein the first reaction gas at least comprises one of di-sec-butylaminosilane (DSBAS) and di-tert-butylaminosilane (DTBAS).
Specifically, the substrate 101 is placed in a reaction chamber, the substrate 101 is heated, and a first reaction gas is introduced into the reaction chamber to form the silicon seed layer 1061 covering the inner wall of the contact hole 105 and the upper surface of the substrate 101 by atomic layer deposition.
The silicon seed layer 1061 has certain crystalline characteristics and a lattice arrangement direction, and can control the crystalline characteristics and the lattice arrangement direction of the silicon layer formed thereon.
The silicon source reaction gas used in step S130 includes at least one of di-sec-butylaminosilane (DSBAS) and di-tert-butylaminosilane (DTBAS).
The silicon seed layer 1061 is formed to a thickness on the order of atomic layers. The thickness of the silicon seed layer 1061 may be 0 to 10A.
The silicon seed layer 1061 has a thickness larger in a portion in contact with the substrate 101 than in a portion in contact with the first interlayer insulating layer 104 due to the difference in material between the substrate 101 and the first interlayer insulating layer 104.
In the present embodiment, silicon seed layer 1061 is formed by at least one of di-sec-butylaminosilane (DSBAS) and di-tert-butylaminosilane (DTBAS), and the amino ligands in di-sec-butylaminosilane (DSBAS) and di-tert-butylaminosilane (DTBAS) have a large size and a large coverage area.
Step S140: as shown in fig. 6, the substrate 101 is further heated, and a second reaction gas is introduced into the reaction chamber to form a phosphorus doped silicon layer 1062 covering the surface of the silicon seed layer 1061 away from the substrate 101.
The thickness of phosphorus doped silicon layer 1062 is much greater than the thickness of silicon seed layer 1061. The phosphorus doped silicon layer 1062 may be several hundred angstroms thick.
The second reaction gas used in step S140 includes silane and phosphane that do not include amino groups, and the silicon film is doped while being formed, so that the phosphorus-doped silicon layer 1062 is finally formed.
The second reaction gas may be monosilane (SiH4) and phosphine (PH 3).
In some cases, the total thickness of silicon seed layer 1061 and phosphorus doped silicon layer 1062 is greater than or equal to the depth of contact hole 105, and silicon seed layer 1061 and phosphorus doped silicon layer 1062 together form the semiconductor layer of the bit line plug.
In the embodiment of the present application, the size of the amino ligand in di-sec-butylaminosilane (DSBAS) and di-tert-butylaminosilane (DTBAS) in the reaction gas for forming the silicon seed layer 1061 is large, the coverage area is also large, when the phosphorus doped silicon layer 1062 grows above the formed silicon seed layer 1061, the incubation period can be greatly shortened, the roughness and the coverage rate of the phosphorus doped silicon layer 1062 can be greatly improved, and the possibility that the phosphorus doped silicon layer 1062 forms voids, cracks and other defects at the sidewall position of the contact hole 105 is greatly reduced, thereby reducing the defects in the bit line plug, such as voids, cracks and the like, and reducing the short-circuit problem of the bit line.
Step S150: the phosphorus doped silicon layer 1062 is planarized.
In the planarization step, the uppermost phosphorous doped silicon layer 1062 is mainly planarized.
Step S160: as shown in fig. 7 and 8, a bit line stack is formed over the phosphorous doped silicon layer 1062 after planarization.
The bitline stack includes a barrier layer 1071 and a metal layer 1072 stacked in sequence over the phosphorus doped silicon layer 1062.
The material of the barrier layer 1071 includes titanium nitride (TiN), and the material of the metal layer 1072 includes tungsten (W).
Step S170: patterning the silicon seed layer 1061, the planarized phosphorus-doped silicon layer 1062, and the bit line stack to obtain bit line contact plugs (not shown) and bit line structures (not shown), respectively; the bit line structure is electrically connected to the substrate 101 (mainly the active pattern 1011) through the bit line contact plug.
The bit line contact plug is composed of a silicon seed layer 1061 and a phosphorus doped silicon layer 1062.
The bit line structure is formed from a bit line stack.
In the embodiment of the application, the defects such as holes and cracks in the bit line plug are greatly reduced, and the short circuit problem of the bit line is greatly reduced.
The structure of the resulting semiconductor device is shown in fig. 9 and 10.
The present embodiment provides a manufacturing method of a semiconductor device, the manufacturing method including providing a semiconductor substrate 101, and forming a first interlayer insulating layer 104 over the substrate 101; forming a contact hole 105 penetrating the first interlayer insulating layer 104 and extending to the inside of the substrate 101; wherein the contact hole 105 exposes a portion of the substrate 101 and a portion of the first interlayer insulating layer 104; placing the substrate 101 in a reaction chamber, heating the substrate 101, and introducing a first reaction gas into the reaction chamber to form a silicon seed layer 1061 covering the inner wall of the contact hole 105 and the upper surface of the first interlayer insulating layer 104; wherein the first reaction gas at least comprises one of di-sec-butylaminosilane and di-tert-butylaminosilane; the substrate 101 is further heated, and a second reaction gas is introduced into the reaction chamber to form a phosphorus doped silicon layer 1062 covering the surface of the silicon seed layer 1061 away from the substrate 101. Silicon seed layer 1061 is formed by at least one of di-sec-butylaminosilane (DSBAS) and di-tert-butylaminosilane (DTBAS), and the amino ligands in di-sec-butylaminosilane (DSBAS) and di-tert-butylaminosilane (DTBAS) have larger sizes, so that when phosphorus doped silicon layer 1062 is grown on formed silicon seed layer 1061, the incubation period can be greatly shortened, the roughness and coverage rate of phosphorus doped silicon layer 1062 can be greatly improved, and the possibility that phosphorus doped silicon layer 1062 forms defects such as voids and cracks at the side wall position of contact hole 105 is greatly reduced.
Although the embodiments disclosed in the present application are described above, the descriptions are only for the convenience of understanding the present application, and are not intended to limit the present application. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims.

Claims (10)

1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, and forming a first interlayer insulating layer over the substrate;
forming a contact hole penetrating the first interlayer insulating layer and extending to the inside of the substrate; wherein the contact hole exposes a portion of the substrate and a portion of the first interlayer insulating layer;
placing the substrate in a reaction chamber, heating the substrate, and introducing a first reaction gas into the reaction chamber to form a silicon seed layer covering the inner wall of the contact hole and the upper surface of the first interlayer insulating layer; wherein the first reaction gas at least comprises one of di-sec-butylaminosilane and di-tert-butylaminosilane;
and continuously heating the substrate, and introducing a second reaction gas into the reaction chamber to form a phosphorus-doped silicon layer covering the surface of the silicon seed layer, which is far away from the substrate.
2. The method according to claim 1, wherein the step of placing the substrate in a reaction chamber, heating the substrate, and introducing a first reaction gas into the reaction chamber to form a silicon seed layer covering an inner wall of the contact hole and an upper surface of the first interlayer insulating layer comprises the steps of:
and placing the substrate in a reaction chamber, heating the substrate, and introducing a first reaction gas into the reaction chamber to form a silicon seed layer covering the inner wall of the contact hole and the upper surface of the first interlayer insulating layer in an atomic layer deposition mode.
3. The method of claim 1, wherein the silicon seed layer has a thickness on the order of atomic dimensions.
4. The method according to claim 1, wherein a thickness of a portion of the silicon seed layer in contact with the substrate is larger than a thickness of a portion in contact with the first interlayer insulating layer.
5. The method according to claim 1, wherein the silicon seed layer is an amorphous silicon seed layer.
6. The method of claim 1, wherein the second reactive gas comprises silane and phosphane that do not contain amino groups.
7. The method of claim 1, wherein the total thickness of the silicon seed layer and the phosphorus doped silicon layer is greater than or equal to the depth of the contact hole.
8. The method of claim 7, wherein after the step of forming the phosphorus doped silicon layer overlying the surface of the silicon seed layer remote from the substrate, the method further comprises:
carrying out planarization treatment on the phosphorus-doped silicon layer;
forming a bit line stack over the phosphorous doped silicon layer after planarization;
patterning the silicon seed layer, the flattened phosphorus-doped silicon layer and the bit line lamination layer to respectively obtain a bit line contact plug and a bit line structure; wherein the bit line structure is electrically connected with the substrate through the bit line contact plug.
9. The method of claim 1, wherein prior to the step of forming a first interlayer insulating layer over the substrate, the method further comprises:
forming a plurality of active patterns arranged at intervals along a first direction in the upper surface of the substrate; wherein each active pattern is isolated by an isolation pattern;
forming a plurality of trench gate structures arranged at intervals along a second direction in the upper surface of the substrate; wherein each of the trench gate structures intersects at least one of the active patterns.
10. A semiconductor device prepared by the method of any one of claims 1 to 9.
CN202110902056.6A 2021-08-06 2021-08-06 Method for manufacturing semiconductor device and semiconductor device Active CN113629008B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110902056.6A CN113629008B (en) 2021-08-06 2021-08-06 Method for manufacturing semiconductor device and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110902056.6A CN113629008B (en) 2021-08-06 2021-08-06 Method for manufacturing semiconductor device and semiconductor device

Publications (2)

Publication Number Publication Date
CN113629008A true CN113629008A (en) 2021-11-09
CN113629008B CN113629008B (en) 2023-09-05

Family

ID=78383198

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110902056.6A Active CN113629008B (en) 2021-08-06 2021-08-06 Method for manufacturing semiconductor device and semiconductor device

Country Status (1)

Country Link
CN (1) CN113629008B (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09246381A (en) * 1996-03-13 1997-09-19 Sony Corp Manufacture of semiconductor device
CN101140897A (en) * 2006-09-04 2008-03-12 中芯国际集成电路制造(上海)有限公司 Plug manufacturing method of contact plug
US20120309165A1 (en) * 2011-06-01 2012-12-06 Elpida Memory, Inc. Semiconductor device having gate trench and manufacturing method thereof
CN110911348A (en) * 2018-09-18 2020-03-24 爱思开海力士有限公司 Method for forming contact plug of semiconductor integrated circuit device
CN111162039A (en) * 2018-11-08 2020-05-15 长鑫存储技术有限公司 Metal conductive structure and preparation method of semiconductor device
CN112117259A (en) * 2019-06-20 2020-12-22 中芯国际集成电路制造(上海)有限公司 Semiconductor device and forming method
CN112420732A (en) * 2020-11-19 2021-02-26 长江存储科技有限责任公司 Three-dimensional memory and preparation method thereof

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09246381A (en) * 1996-03-13 1997-09-19 Sony Corp Manufacture of semiconductor device
CN101140897A (en) * 2006-09-04 2008-03-12 中芯国际集成电路制造(上海)有限公司 Plug manufacturing method of contact plug
US20120309165A1 (en) * 2011-06-01 2012-12-06 Elpida Memory, Inc. Semiconductor device having gate trench and manufacturing method thereof
CN110911348A (en) * 2018-09-18 2020-03-24 爱思开海力士有限公司 Method for forming contact plug of semiconductor integrated circuit device
CN111162039A (en) * 2018-11-08 2020-05-15 长鑫存储技术有限公司 Metal conductive structure and preparation method of semiconductor device
CN112117259A (en) * 2019-06-20 2020-12-22 中芯国际集成电路制造(上海)有限公司 Semiconductor device and forming method
CN112420732A (en) * 2020-11-19 2021-02-26 长江存储科技有限责任公司 Three-dimensional memory and preparation method thereof

Also Published As

Publication number Publication date
CN113629008B (en) 2023-09-05

Similar Documents

Publication Publication Date Title
KR100613526B1 (en) Arrangement and methods for fabricating vertical transistor cells and transistor-controlled memory cells
US10553599B1 (en) Three-dimensional memory device containing drain select isolation structures and on-pitch channels and methods of making the same without an etch stop layer
US8309460B2 (en) Methods of manufacturing semiconductor devices
JP3878019B2 (en) Memory having trench capacitor and selection transistor and method for manufacturing the same
US10756110B1 (en) Method of forming seamless drain-select-level electrodes for a three-dimensional memory device and structures formed by the same
KR101355858B1 (en) Method for fabricating buried bit line of vertical transistor
KR20200062353A (en) 3D memory device including multilevel drain select gate isolation and manufacturing method thereof
WO2020068184A1 (en) Three-dimensional memory device including three-dimensional bit line discharge transistors and method of making the same
CN108389837A (en) Transistor arrangement, memory construction and preparation method thereof
KR20120078917A (en) Semiconductor device and method for forming the same
US5770498A (en) Process for forming a diffusion barrier using an insulating spacer layer
JP3955344B2 (en) Manufacturing method of capacitor in semiconductor device
KR100319207B1 (en) Cylindrical storage capacitor for memory cell and method for fabricating the same
CN113658918B (en) Method for manufacturing semiconductor device and semiconductor device
KR102607426B1 (en) Semiconductor Integrated Circuit Device Having improved resistance characteristic And Method of Manufacturing The Same
US20080067568A1 (en) Capacitor with hemispherical silicon-germanium grains and a method for making the same
CN113629008B (en) Method for manufacturing semiconductor device and semiconductor device
US5909045A (en) Semiconductor memory device having tree-type capacitor
CN115036267A (en) Semiconductor structure and preparation method thereof
CN215933601U (en) Semiconductor device with a plurality of transistors
US6326262B1 (en) Method for fabricating epitaxy layer
US5811332A (en) Method of fabricating a capacitor structure for a semiconductor memory device
CN112542459A (en) Semiconductor device and method for manufacturing the same
CN100373623C (en) Dynamic random access memory unit and its array, and method of making the same
WO2020146051A1 (en) Three-dimensional memory device containing a replacement buried source line and methods of making the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant