CN113628663B

CN113628663B - Calculating an optimized read voltage

Info

Publication number: CN113628663B
Application number: CN202110490244.2A
Authority: CN
Inventors: P·R·哈亚特; J·菲兹帕特里克; A·S·埃侯赛因; S·帕塔萨拉蒂
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2020-05-07
Filing date: 2021-05-06
Publication date: 2024-04-02
Anticipated expiration: 2041-05-06
Also published as: CN113628663A; US11024401B1; US11557361B2; US20210350867A1

Abstract

The application relates to calculating an optimized read voltage. A memory device to determine voltages optimized to read a group of memory cells by: the group of memory cells is read at a plurality of test voltages, a bit count is calculated at the test voltages, and a count difference in the bit counts of adjacent voltage pairs in the test voltages is calculated, respectively. When the smallest one of the count differences is found on one side of the distribution of count differences according to voltage, the memory device is configured to determine a location of an optimized read voltage based on a ratio between a first count difference and a second count difference, wherein the first count difference is the smallest of the count differences and the second count difference is closest in voltage to the first count difference.

Description

Calculating an optimized read voltage

Technical Field

At least some embodiments disclosed herein relate generally to memory systems and, more particularly, but not limited to, memory systems configured to calculate optimized voltages for reading data from memory cells.

Background

The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, a host system may utilize a memory subsystem to store data at and retrieve data from a memory device.

Disclosure of Invention

In one aspect, the present application relates to a memory device comprising: an integrated circuit package enclosing the memory device; and a plurality of groups of memory cells formed on the at least one integrated circuit die; wherein in response to a command identifying a group of memory cells within the plurality of groups, the memory device is configured to: reading the group of memory cells at a plurality of test voltages; determining bit counts at the test voltage, respectively, wherein each bit count at the test voltage identifies a number of memory cells in the group that provide a predetermined bit value when read at the test voltage; calculating count differences in the bit counts of adjacent ones of the test voltages, wherein each count difference in voltage interval between adjacent ones of the test voltages is a difference between bit counts of the adjacent voltage pairs; identifying a first count difference of not greater than at least two of the count differences among the count differences, wherein the first count difference has a voltage interval between two voltage intervals that is not at the at least two of the count differences; and determining a location of an optimized read voltage in the voltage intervals of the first count differences based on a ratio between the first count differences and a second count difference having a voltage interval closest to the voltage interval of the first count differences of the at least two of the count differences.

In another aspect, the present application further provides a method comprising: reading a group of memory cells in a memory device at a plurality of test voltages; determining bit counts at the test voltage, respectively, wherein each bit count at the test voltage identifies a number of memory cells in the group that provide a predetermined bit value when read at the test voltage; calculating count differences in the bit counts of adjacent ones of the test voltages, wherein each count difference in voltage interval between adjacent ones of the test voltages is a difference between bit counts of the adjacent voltage pairs; identifying a first count difference of not greater than at least two of the count differences among the count differences, wherein the first count difference has a voltage interval between two voltage intervals that is not at the at least two of the count differences; and determining a location of an optimized read voltage in the voltage intervals of the first count differences based on a ratio between the first count differences and a second count difference having a voltage interval closest to the voltage interval of the first count differences of the at least two of the count differences.

In yet another aspect, the present application further provides a memory subsystem comprising: a processing device; and at least one memory device having a group of memory cells formed on an integrated circuit die; wherein the processing device is configured to transmit a command to the memory device having an address identifying the group of memory cells; wherein in response to the command, the memory device is configured to: reading the group of memory cells at a plurality of test voltages; determining bit counts at the test voltage, respectively, wherein each bit count at the test voltage identifies a number of memory cells in the group that provide a predetermined bit value when read at the test voltage; calculating count differences in the bit counts of adjacent ones of the test voltages, wherein each count difference in voltage interval between adjacent ones of the test voltages is a difference between bit counts of the adjacent voltage pairs; comparing the count differences; identifying a first count difference of not greater than at least two of the count differences among the count differences, wherein the first count difference has a voltage interval between two voltage intervals that is not at the at least two of the count differences; and determining a location of an optimized read voltage in the voltage intervals of the first count differences based on a ratio between the first count differences and a second count difference having a voltage interval closest to the voltage interval of the first count differences of the at least two of the count differences.

Drawings

Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.

FIG. 1 illustrates an example computing system having a memory subsystem according to some embodiments of the disclosure.

FIG. 2 illustrates an integrated circuit memory device having calibration circuitry configured to measure signal and noise characteristics, according to one embodiment.

FIG. 3 shows an example of measuring signal and noise characteristics to improve memory operation according to one embodiment.

Fig. 4-6 illustrate techniques for calculating an optimized read voltage from a count difference, according to one embodiment.

FIG. 7 shows a method of calculating optimized read voltages for reading a group of memory cells, according to one embodiment.

FIG. 8 is a block diagram of an example computer system in which embodiments of the present disclosure may operate.

Detailed Description

At least some aspects of the present disclosure relate to memory subsystems configured to calculate optimized voltages for reading a group of memory cells from their signal and noise characteristics in an efficient manner. Examples of memory devices and memory modules are described below in connection with fig. 1. In general, a host system may utilize a memory subsystem that includes one or more components (e.g., a memory device that stores data). The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

An integrated circuit memory cell (e.g., a flash memory cell) may be programmed at a threshold voltage to store data by way of its state. For example, if a memory cell is configured/programmed in a state that allows a large amount of current to pass through the memory cell at a threshold voltage, the memory cell is storing one bit; and otherwise the memory cell is storing a zero bit. Further, the memory cells may store multiple bits of data by being configured/programmed differently at multiple threshold voltages. For example, a memory cell may store multiple bits of data by having a combination of states at multiple threshold voltages; and different combinations of the states of the memory cells at the threshold voltage may be interpreted to represent different states of the data bits stored in the memory cells.

However, after configuring/programming the state of an integrated circuit memory cell using a write operation to store data in the memory cell, the optimized threshold voltage for reading the memory cell may shift due to several factors, such as charge loss, read disturb, cross temperature effects (e.g., write and read at different operating temperatures), especially when the memory cell is programmed to store multiple bits of data.

The data may be encoded with redundant information to facilitate error detection and recovery. When data encoded with redundant information is stored in a memory subsystem, the memory subsystem may detect errors in the original encoded data retrieved from the memory subsystem and/or recover the original uncoded data used to generate the encoded data for storage in the memory subsystem. The recovery operation may succeed (or have a high probability of success) when the original encoded data retrieved from the memory subsystem contains less than a threshold amount of errors or the bit error rate in the encoded data is below a threshold. For example, error detection and data recovery may be performed using techniques such as Error Correction Codes (ECC), low Density Parity Check (LDPC) codes, and the like.

When the encoded data retrieved from the memory cells of the memory subsystem is too erroneous to be successfully decoded, the memory subsystem may re-attempt to execute the read command using the adjustment parameters for reading the memory cells. However, searching for parameter sets by multiple read retries with multiple rounds of calibration, reading, decoding failure, and retry until the encoded data retrieved from the memory cells can be decoded into error-free data is very inefficient. For example, blind searching for an optimized read voltage is inefficient. For example, one or more commands introduced between retried reads may result in longer latency for recovering data from errors.

Conventional calibration circuitry has been used to calibrate the memory region from rows in terms of applying a read level signal to account for shifting of the threshold voltages of the memory cells within the memory region. During calibration, the calibration circuitry is configured to apply different test signals to the memory region to count the number of memory cells outputting a specified data state of the test signals. Based on the count, the calibration circuitry determines a read level offset value as a response to the calibration command.

At least some aspects of the present disclosure address the above and other drawbacks by calculating voltages optimized to read a group of memory cells from their signal and noise characteristics using efficient methods that can be implemented in a memory device. For example, the method may be implemented without complex operations on floating point numbers.

For example, in response to a command from a controller of the memory subsystem, the memory device may automatically calibrate voltages for reading groups of memory cells based on measured signal and noise characteristics for the memory cells. When a test voltage is applied to read a memory cell, the signal and noise characteristics measured for the memory cell may be based on a bit count of the memory cells in the group having a predetermined state. Different test voltages separated from each other by a predetermined voltage interval or gap may have different bit counts. The difference in bit counts of two adjacent test voltages provides a count difference in voltage spacing or gap between adjacent test voltages. An optimized read voltage can be obtained at a voltage where the count difference distribution over the voltages reaches a minimum.

When one of the count differences is smaller than its two adjacent neighbors, it may be determined that the minimum value is in the voltage interval or gap of the smallest count difference. As discussed further below in connection with FIG. 5, an improved position of the optimized read voltage within the gap may be calculated based on the ratio of adjacent neighbors.

When there is no count difference between two higher neighbor neighbors, the optimized read voltage may be identified as being in a voltage interval or gap corresponding to a count difference that is less than two of the next two count differences. As discussed further below in connection with FIG. 6, the improved position of the optimized read voltage within the gap may be calculated based on the ratio of the bit counts at the test voltage across the gap.

After calculating the optimized read voltage (e.g., using the techniques shown in fig. 3-6), the memory device can read the memory cells and obtain hard bit data using the optimized read voltage, and optionally facilitate modulating the applied read voltage to an adjacent voltage to further read the memory cells for soft bit data.

Preferably, the operations of reading hard bit data and reading soft bit data are scheduled together during execution of the read command to minimize the time required to obtain soft bit data and/or to avoid delays that may be caused by processing separate read commands or by intervening operations to the memory cells.

Optionally, the measured signal and noise characteristics for the memory cells are further used to evaluate the quality of the hard bit data retrieved using the calibrated read voltage. The evaluation may be performed at least partially concurrently with the reading of the hard bit data. Based on the assessed quality of the hard bit data, the memory device may selectively read and/or transmit soft bit data.

Error detection and data recovery techniques (e.g., error Correction Codes (ECC), low Density Parity Check (LDPC) codes, etc.) may be used to decode hard bit data retrieved from a group of memory cells using calibrated/optimized read voltages. When the error rate in the hard bit data is high, the soft bit data retrieved from the memory cells using the read voltage, which is a predetermined offset from the calibrated/optimized read voltage, may be used to assist in decoding the hard bit data. When soft bit data is used, the error recovery capability in decoding hard bit data is improved.

Optionally, the controller of the memory subsystem may first send a command to the memory device to read the hard bit data with the calibrated read voltage; and in response to a failure to decode the hard bit data, the controller may further send a command to the memory device to read the corresponding soft bit data. Such an implementation is effective when the probability of hard bit data decoding failure without soft bit data is below a threshold. However, when the probability is above the threshold, the additional load of sending a separate command becomes disadvantageous.

When the probability of using soft bit data is above a threshold, it is advantageous to transmit a single command to the memory device to cause the memory device to read the soft bit data and the hard bit data together. Further, the memory device may use the signal and noise characteristics of the memory cells to predict whether soft bit data is likely to be used by the controller. If the probability of using soft bit data is below a threshold, the memory device may skip the operation of reading soft bit data.

For example, during a calibration operation, the memory device may measure signal and noise characteristics of the memory cells and use the measurements to calculate an optimized/calibrated read voltage for reading the memory cells. Once the optimized/calibrated read voltage is obtained, the memory device reads the memory cells to obtain the hard bit data. Subsequently, the memory device adjusts the applied optimized/calibrated read voltage (e.g., via boost modulation) to a predetermined offset (e.g., 50 mV) that is lower than the optimized/calibrated read voltage to retrieve the data set, and further adjusts the currently applied voltage (e.g., via boost modulation) to a predetermined offset that is higher than the optimized/calibrated read voltage to retrieve another data set. The logical operation of XOR (exclusive or) of the two sets of data at both sides with respect to the offset (e.g., 50 mV) of the optimized/calibrated read voltage provides an indication of whether the memory cell is doing the same read at the offset location around the optimized/calibrated read voltage. The result of the XOR operation may be used as soft bit data for decoding hard bit data reads using the optimized/calibrated read voltage. In some implementations, a larger offset (e.g., 90 mV) may be used to read another soft bit data set indicating whether the memory cell is to be read identically at a location according to the larger offset (e.g., 90 mV) around the optimized/calibrated read voltage.

For example, in response to a read command from a controller of the memory subsystem, a memory device of the memory subsystem performs an operation that calibrates a read voltage of the memory cell. Calibration is performed by measuring signal and noise characteristics by reading the memory cells at multiple voltage levels near the estimated location of the optimized read voltage. The optimized read voltage may be calculated based on statistics from results produced by reading the memory cells at the voltage level. For example, the statistics may include and/or may be based on counts measured by the calibration circuitry at voltage levels. Optionally, such signal and noise characteristics may be measured in parallel for the sub-regions to shorten the total time for measuring the signal and noise characteristics. Statistics from the results generated by reading memory cells at voltage levels can be used to predict whether decoding hard bit data retrieved using an optimized read voltage is likely to require the use of soft bit data for successful decoding. Thus, the transmission of soft bit data may be selectively performed based on the prediction.

For example, a predictive model may be generated by machine learning to estimate or evaluate the quality of data retrievable from a set of memory cells using calibrated/optimized read voltages. The predictive model may use as input features calculated from measured signal and noise characteristics of the memory cells to generate predictions. Reading and/or transmission of soft bit data may be selectively skipped based on the prediction.

FIG. 1 illustrates an example computing system 100 including a memory subsystem 110, according to some embodiments of the disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of these.

The memory subsystem 110 may be a storage device, a memory module, or a hybrid of storage devices and memory modules. Examples of storage devices include Solid State Drives (SSDs), flash drives, universal Serial Bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal Flash Storage (UFS) drives, secure Digital (SD) cards, and Hard Disk Drives (HDDs). Examples of memory modules include Dual Inline Memory Modules (DIMMs), small DIMMs (SO-DIMMs), and various types of non-volatile dual inline memory modules (NVDIMMs).

The computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, an unmanned aerial vehicle, a train, an automobile, or other conveyance), an internet of things (IoT) -enabled device, an embedded computer (e.g., one included in a vehicle, an industrial appliance, or a networked business device), or such computing device that includes memory and a processing device.

The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. FIG. 1 illustrates one example of a host system 120 coupled to one memory subsystem 110. As used herein, "coupled to" or "coupled with … …" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

Host system 120 may include a processor chipset (e.g., processing device 118) and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., controller 116) (e.g., NVDIMM controller), and a storage protocol controller (e.g., PCIe controller, SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and to read data from the memory subsystem 110.

Host system 120 may be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, serial Advanced Technology Attachment (SATA) interfaces, peripheral component interconnect express (PCIe) interfaces, universal Serial Bus (USB) interfaces, fibre channel, serial Attached SCSI (SAS), double Data Rate (DDR) memory buses, small Computer System Interfaces (SCSI), dual Inline Memory Module (DIMM) interfaces (e.g., DIMM socket interfaces supporting Double Data Rates (DDR)), open NAND Flash Interfaces (ONFI), double Data Rates (DDR), low Power Double Data Rates (LPDDR), or any other interface. A physical host interface may be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled with host system 120 through a PCIe interface, host system 120 may further utilize an NVM high speed (NVMe) interface to access components (e.g., memory device 130). The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120. Fig. 1 shows a memory subsystem 110 as an example. In general, the host system 120 may access multiple memory subsystems via the same communication connection, multiple separate communication connections, and/or a combination of communication connections.

The processing device 118 of the host system 120 may be, for example, a microprocessor, a Central Processing Unit (CPU), a processing core of a processor, an execution unit, or the like. In some cases, the controller 116 may be referred to as a memory controller, a memory management unit, and/or an initiator. In one example, the controller 116 controls communication via a bus coupled between the host system 120 and the memory subsystem 110. In general, the controller 116 may send commands or requests to the memory subsystem 110 that desire to access the memory devices 130, 140. The controller 116 may further include interface circuitry for communicating with the memory subsystem 110. The interface circuitry may translate responses received from the memory subsystem 110 into information for the host system 120.

The controller 116 of the host system 120 may communicate with the controller 115 of the memory subsystem 110 to perform operations such as reading data, writing data, or erasing data at the memory devices 130, 140, and other such operations. In some cases, the controller 116 is integrated within the same package as the processing device 118. In other cases, the controller 116 is separate from the packaging of the processing device 118. The controller 116 and/or the processing device 118 may include hardware, such as one or more Integrated Circuits (ICs) and/or discrete components, buffers, caches, or a combination thereof. The controller 116 and/or the processing device 118 may be a microcontroller, dedicated logic circuitry (e.g., a Field Programmable Gate Array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

The memory devices 130, 140 may include any combination of different types of non-volatile memory components and/or volatile memory components. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random Access Memory (RAM), such as Dynamic Random Access Memory (DRAM) and Synchronous Dynamic Random Access Memory (SDRAM).

Some examples of non-volatile memory components include NAND (or NOT AND) (NAND) type flash memory AND write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. The cross-point array of non-volatile memory may perform bit storage based on a change in bulk resistance in combination with the stackable cross-meshed data access array. In addition, in contrast to many flash-based memories, cross-point nonvolatile memories may perform in-place write operations in which nonvolatile memory cells may be programmed without prior erasure of the nonvolatile memory cells. NAND type flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

Each of memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a Single Layer Cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), tri-level cells (TLC), quad-level cells (QLC), and five-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of these. In some embodiments, a particular memory device may include an SLC portion of a memory cell, as well as an MLC portion, TLC portion, or QLC portion. The memory cells of memory device 130 may be grouped into pages that may refer to logical units of the memory device to store data. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks.

Although non-volatile memory devices are described, such as 3D cross point type and NAND type memories (e.g., 2D NAND, 3D NAND), memory device 130 may be based on any other type of non-volatile memory, such as Read Only Memory (ROM), phase Change Memory (PCM), self-selected memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic Random Access Memory (MRAM), spin Transfer Torque (STT) -MRAM, conductive Bridging RAM (CBRAM), resistive Random Access Memory (RRAM), oxide-based RRAM (OxRAM), or non-NOR) flash memory, and Electrically Erasable Programmable Read Only Memory (EEPROM).

The memory subsystem controller 115 (or for simplicity, the controller 115) may communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations (e.g., in response to commands scheduled on the command bus by the controller 116). The controller 115 may include hardware, such as one or more Integrated Circuits (ICs) and/or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), etc.), or another suitable processor.

The controller 115 may include a processing device 117 (processor) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the controller 115 comprises an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

In some embodiments, local memory 119 may contain memory registers that store memory pointers, fetched data, and the like. Local memory 119 may also include Read Only Memory (ROM) for storing microcode. Although the example memory subsystem 110 in fig. 1 has been shown as including the controller 115, in another embodiment of the present disclosure, the memory subsystem 110 does not include the controller 115, but may rely on external control (e.g., provided by an external host, or provided by a processor or controller separate from the memory subsystem).

In general, the controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and Error Correction Code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical Block Addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The controller 115 may further include host interface circuitry to communicate with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory device 130 and convert responses associated with the memory device 130 into information for the host system 120.

Memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that may receive addresses from controller 115 and decode the addresses to access memory device 130.

In some embodiments, memory device 130 includes a local media controller 150 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory units of memory device 130. An external controller (e.g., memory subsystem controller 115) may manage memory device 130 externally (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device that is the original memory device combined with a local controller (e.g., local controller 150) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAAND) device.

The controller 115 and/or the memory device 130 may include a read manager 113 configured to calculate voltages optimized for reading a group of memory cells based on signal and noise characteristics of the group of memory cells. In some embodiments, the controller 115 in the memory subsystem 110 includes at least a portion of the read manager 113. In other embodiments, or in combination, the controller 116 and/or the processing device 118 in the host system 120 includes at least a portion of the read manager 113. For example, controller 115, controller 116, and/or processing device 118 may include logic circuitry implementing read manager 113. For example, the controller 115 or the processing device 118 (processor) of the host system 120 may be configured to execute instructions stored in memory for performing the operations of the read manager 113 described herein. In some embodiments, read manager 113 is implemented in an integrated circuit chip disposed in memory subsystem 110. In other embodiments, the read manager 113 may be part of the firmware of the memory subsystem 110, the operating system of the host system 120, a device driver or application, or any combination thereof.

For example, the read manager 113 implemented in the controller 115 may transmit a read command or a calibration command to the memory device 130. In response to such commands, the read manager 113 implemented in the memory device 130 is configured to measure signal and noise characteristics of the group of memory cells by reading the group of memory cells at a plurality of test voltages configured close to the estimated location of the optimized read voltage for the group of memory cells. The test voltages may be configured to be equally spaced apart by the same amount of voltage gap. According to the result of reading the group of memory cells at the test voltage, when the group is read at the test voltage, it is determined that the bit count of the memory cells in the group is storing or reporting a predetermined bit (e.g., 0 or 1 corresponding to whether the memory cells are conductive or nonconductive at the test voltage). The count difference may be calculated from the bit count for each adjacent test voltage pair. The read manager 113 compares the count differences to identify the voltage interval containing the optimized read voltage, and then estimates the location in the voltage interval for the optimized read voltage based on comparing the bit count or count differences closest to the voltage interval. The estimated position may be used as an optimized read voltage to read hard bit data; and a voltage that is a predetermined offset from the optimized read voltage may be used to read the soft bit data.

Fig. 2 illustrates an integrated circuit memory device 130 having a calibration circuit 145 configured to measure signal and noise characteristics, according to one embodiment. For example, the memory device 130 in the memory subsystem 110 of FIG. 1 may be implemented using the integrated circuit memory device 130 of FIG. 2.

The integrated circuit memory device 130 may be enclosed in a single integrated circuit package. The integrated circuit memory device 130 includes multiple groups 131, & gt, 133 of memory cells that may be formed in one or more integrated circuit dies. Typical memory cells in groups 131, 133 may be programmed to store one or more bits of data.

Some memory cells in integrated circuit memory device 130 may be configured to operate together for a particular type of operation. For example, memory cells on an integrated circuit die may be organized into planes, blocks, and pages. The plane contains a plurality of blocks; a block contains a plurality of pages; and a page may have multiple strings of memory cells. For example, an integrated circuit die may be the smallest unit that can independently execute commands or report status; the same concurrent operation may be performed in parallel on multiple planes in the integrated circuit die; the block may be the smallest unit to perform an erase operation; and a page may be the smallest unit used to perform a data programming operation (writing data into a memory cell). Each string connects its memory cells to a common bit line; and the control gates of the memory cells at the same location in the string in the block or page are connected to a common word line. Control signals may be applied to the word lines and bit lines to address individual memory cells.

The integrated circuit memory device 130 has a communication interface 147 to receive commands with addresses 135 from the controller 115 of the memory subsystem 110, retrieve both hard bit data 177 and soft bit data 173 from the memory addresses 135, and provide at least the hard bit data 177 as a response to the commands. Address decoder 141 of integrated circuit memory device 130 converts address 135 into control signals to select a group of memory cells in integrated circuit memory device 130; and read/write circuitry 143 of integrated circuit memory device 130 performs operations to determine hard bit data 177 and soft bit data 173 for the memory cell at address 135.

Integrated circuit memory device 130 has calibration circuitry 145 configured to determine a measure of signal and noise characteristics 139 of memory cells in a group (e.g., 131,..or 133). For example, statistics of memory cells in a group or region having a particular state at one or more test voltages may be measured to determine signal and noise characteristics 139. Optionally, signal and noise characteristics 139 may be provided by memory device 130 to controller 115 of memory subsystem 110 via communication interface 147.

In at least some embodiments, the calibration circuit 145 determines an optimized read voltage for a group of memory cells based on the signal and noise characteristics 139. In some embodiments, the signal and noise characteristics 139 are further used in the calibration circuit 145 to determine whether the error rate in the hard bit data 177 is high enough such that the combination of the hard bit data 177 and the soft bit data 173 is preferably decoded using a precision decoder. When predicting use of the soft bit data 173 based on the prediction/classification of the error rate in the hard bit data 177, the read manager 113 may transmit both the soft bit data 173 and the hard bit data 177 to the controller 115 of the memory subsystem 110.

For example, the calibration circuit 145 may measure the signal and noise characteristics 139 by reading different responses from memory cells in the group (e.g., 131,..times., 133) by varying operating parameters for reading the memory cells (e.g., voltages applied during operations to read data from the memory cells).

For example, when executing a command to read hard bit data 177 and soft bit data 173 from address 135, calibration circuit 145 may measure signal and noise characteristics 139 on the fly. Since the signal and noise characteristics 139 are measured as part of the operation of reading the hard bit data 177 from the address 135, the signal and noise characteristics 139 may be used in the read manager 113 with reduced or zero latency lost in executing the command to read the hard bit data 177 from the address 135.

The read manager 113 of the memory device 130 is configured to use the signal and noise characteristics 139 to determine the voltage to read the memory cells identified by the address 135 for both hard bit data and soft bit data and determine whether to transmit soft bit data to the memory subsystem controller 115.

For example, read manager 113 can use a prediction model trained via machine learning to predict a probability that hard bit data 177 retrieved from a group of memory cells (e.g., 131 or 133) fails a data integrity test. Predictions may be made based on signal and noise characteristics 139. The read manager 113 uses the signal and noise characteristics 139 to predict the outcome of the test before testing using Error Correction Codes (ECC) and/or Low Density Parity Check (LDPC) codes, or even before transmitting the hard bit data 177 to the decoder. Based on the predicted test results, read manager 113 determines whether to transfer soft bit data to memory subsystem controller 115 in response to the command.

For example, if hard bit data 177 is predicted to be decoded using a low power decoder that utilizes hard bit data 177 but not soft bit data 173, read manager 113 may skip the operation of transmitting soft bit data 173 to memory subsystem controller 115; and read manager 113 provides hard bit data 177 read from the memory cells using optimized read voltages calculated from signal and noise characteristics 139 for decoding by a low power decoder. For example, a low power decoder may be implemented in the memory subsystem controller 115. Alternatively, a low power decoder may be implemented in the memory device 130; and the read manager 113 may provide the result of the low power decoder to the memory subsystem controller 115 as a response to the received command.

For example, if predicting hard bit data 177 fails to decode in a low power decoder but may decode using a high power decoder that utilizes both hard bit data and soft bit data, read manager 113 may decide to provide both hard bit data 177 and soft bit data 173 for decoding by the high power decoder. For example, a high power decoder may be implemented in the controller 115. Alternatively, a high power decoder may be implemented in the memory device 130.

Optionally, if the hard bit data 177 is predicted to fail decoding in a decoder available in the memory subsystem 110, the read manager 113 may decide to skip the operation of transmitting the hard bit data 177 to the memory subsystem controller 115, immediately initiate a read retry, such that when the memory subsystem controller 115 requests a read retry, at least part of the read retry operation is performed to reduce the time in response to the request from the memory subsystem controller 115 for a read retry. For example, during a read retry, the read manager 113 instructs the calibration circuit 145 to perform a modified calibration to obtain a new set of signal and noise characteristics 139, which may be further used to determine an improved read voltage.

Data from memory cells identified by address (135) may include hard bit data 177 and soft bit data 173. The optimized read voltage is used to retrieve the hard bit data 177. Hard bit data 177 identifies the state of the memory cells that are programmed to store data and are then detected in view of changes caused by factors such as charge loss, read disturb, cross temperature effects (e.g., writing and reading at different operating temperatures), and the like. The soft bit data 173 is obtained by reading the memory cells using a read voltage centered around each optimized read voltage that is a predetermined offset from the center of the optimized read voltage. The XOR of the read results at the read voltage with the offset indicates whether the memory cell provides a different read result at the read voltage with the offset. The soft bit data 173 may comprise XOR results. In some cases, a set of XOR results is obtained based on a smaller offset; and another set of XOR results is obtained based on the larger offset. In general, multiple sets of XOR results may be obtained for multiple offsets, with each respective offset being used to determine a lower read voltage and a higher read voltage, such that both the lower and higher read voltages have the same respective offset relative to the optimized read voltage to determine the XOR result.

FIG. 3 shows an example of measuring signal and noise characteristics 139 to improve memory operation according to one embodiment.

In FIG. 3, calibration circuit 145 applies different read voltages V _A 、V _B 、V _C 、V _D And V _E To read the states of memory cells in a group (e.g., 131,..or 133). In general, more or less read voltages may be used to generate the signal and noise characteristics 139.

The same memory cell in a group (e.g., 131,..or 133) may exhibit different states due to different voltages applied during a read operation. Thus, in general, at different read voltages V _A 、V _B 、V _C 、V _D And V _E Count C of memory cells having a predetermined state _A 、C _B 、C _C 、C _D And C _E May be different. The predetermined state may be a state in which a large amount of current passes through the memory cell, or a state in which no large amount of current passes through the memory cell. Count C _A 、C _B 、C _C 、C _D And C _E May be referred to as a bit count.

Calibration circuit 145 may be implemented by applying read voltage V one at a time across a group of memory cells (e.g., 131,..or 133) _A 、V _B 、V _C 、V _D And V _E To measure the bit count.

Alternatively, a group of memory cells (e.g., 131,..or 133) may be configured into multiple subgroups; and the calibration circuit 145 can be implemented by applying a read voltage V _A 、V _B 、V _C 、V _D And V _E The bit counts of the subgroups are measured in parallel. The bit count of a subgroup is considered to represent the bit count in the entire group (e.g., 131,..or 133). Thus, a count C is obtained _A 、C _B 、C _C 、C _D And C _E The duration of (a) can be shortened.

In some embodiments, the bit count C is measured during execution of a command to read data from an address 135 mapped to one or more memory cells in a group (e.g., 131,..or 133) _A 、C _B 、C _C 、C _D And C _E . Thus, the controller 115 does not need to send a separate command to request based on the bit count C _A 、C _B 、C _C 、C _D And C _E Is provided, signal and noise characteristics 139 of (a).

The difference between the bit counts of adjacent voltages indicates an error that occurred in the state of the memory cells in the read group (e.g., 133,..or 133).

For example, according to C _A -C _B Calculate the count difference D _A By taking the read voltage from V _A Change to V _B While an indication of an introduced read threshold error.

Similarly, D _B ＝C _B -C _C ；D _C ＝C _C -C _D The method comprises the steps of carrying out a first treatment on the surface of the And D is _D ＝C _D -C _E 。

Based on the count difference D _A 、D _B 、D _C And D _D The obtained curve 157 represents a prediction of the read threshold error E as a function of read voltage. According to curve 157 (and/or count difference), the optimized read voltage V _O Can be calculated as providing the lowest read threshold error D on curve 157 _{Minimum of} Is a point 153 of (2).

In one embodiment, the calibration circuit 145 calculates the optimized read voltage V _O And causes read/write circuit 143 to use optimized read voltage V _O Data is read from address 135.

Alternatively, the calibration circuit 145 may provide the count difference D to the controller 115 of the memory subsystem 110 via the communication interface 147 _A 、D _B 、D _C And D _D And/or an optimized read voltage V calculated by calibration circuit 145 _O 。

FIG. 3 shows the generation of a set of statistical data (e.g., bit counts and/or count differences) for use at an optimized read voltage V _O An example of a read is performed below. In general, a group of memory cells may be configured to store more than one bit in the memory cells; and the plurality of read voltages are used for reading the data stored in the memory cells. Statistics sets may similarly be measured for each of the read voltages to identify a corresponding optimized read voltage, wherein the test voltages in each statistics set are configured near an expected location of the corresponding optimized read voltage. Thus, the signal and noise characteristics 139 measured for a group of memory cells (e.g., 131 or 133) may include multiple sets of statistical data measured for multiple threshold voltages, respectively.

For example, the controller 115 may instruct the memory device 130 to perform a read operation by providing the address 135 and at least one read control parameter. For example, the read control parameter may be a suggested read voltage.

Memory device 130 may perform a read operation by determining the state of the memory cell at address 135 at a read voltage and providing data according to the determined state.

During a read operation, the calibration circuit 145 of the memory device 130 generates the signal and noise characteristics 139. Data and signal and noise characteristics 139 are provided from the memory device 130 to the controller 115 in response. Alternatively, the processing of the signal and noise characteristics 139 may be performed at least in part using logic circuitry configured in the memory device 130. For example, the processing of the signal and noise characteristics 139 may be implemented, partially or fully, using processing logic configured in the memory device 130. For example, processing logic may be implemented using Complementary Metal Oxide Semiconductor (CMOS) circuitry formed on an integrated circuit die of memory device 130 under the array of memory cells. For example, processing logic may be formed within an integrated circuit package of memory device 130 on a separate integrated circuit die that is connected to the integrated circuit die having memory cells using Through Silicon Vias (TSVs) and/or other connection techniques.

The signal and noise characteristics 139 may be determined based at least in part on the read control parameters. For example, when the read control parameter is a recommended read voltage for reading the memory cell at address 135, calibration circuit 145 may calculate a read voltage V around the recommended read voltage _A 、V _B 、V _C 、V _D And V _E 。

The signal and noise characteristics 139 may include a bit count C _A 、C _B 、C _C 、C _D And C _E . Alternatively or in combination, the signal and noise characteristics 139 may include a count difference D _A 、D _B 、D _C And D _D 。

Optionally, calibration circuit 145 uses a method to determine the count difference D _A 、D _B 、D _C And D _D Calculating an optimized read voltage V _O The method comprises the steps of carrying out a first treatment on the surface of the And the controller 115 uses a different method to calculate the optimized read voltage V from the signal and noise characteristics 139 and optionally other data not available to the calibration circuit 145 _O 。

When calibrating circuit 145Can be based on the count difference D generated during the read operation _A 、D _B 、D _C And D _D Calculating an optimized read voltage V _O When the signal and noise characteristics optionally include an optimized read voltage V _O . Furthermore, memory device 130 may use optimized read voltage V in determining hard bit data in data from memory cells at address 135 _O . Can be obtained by reading the voltage V from the optimization _O The read voltage, which is shifted by a predetermined amount, reads the memory cells to obtain soft bit data among the data. Alternatively, the memory device 130 uses a controller-specified read voltage provided in the read control parameter when reading data.

The controller 115 may be configured with a stronger processing power than the calibration circuitry 145 of the integrated circuit memory device 130. Further, the controller 115 may have other signal and noise characteristics suitable for the memory cells in the group (e.g., 133,..or 133). Thus, in general, the controller 115 may calculate an optimized read voltage V _O For example, for a subsequent read operation, or for a retry of a read operation).

In general, the calibration circuit 145 need not provide the signal and noise characteristics 139 in the form of a distribution of bit counts over a set of read voltages or in the form of a distribution of count differences over a set of read voltages. For example, the calibration circuit 145 may provide an optimized read voltage V calculated by the calibration circuit 145 _O As signal and noise characteristics 139.

The calibration circuit 145 may be configured to generate signal and noise characteristics 139 (e.g., bit count or bit count difference) as a byproduct of the read operation. The generation of the signal and noise characteristics 139 may be implemented in the integrated circuit memory device 130 with little or no impact on the latency of the read operation, as compared to a typical read that does not generate the signal and noise characteristics 139. Thus, the calibration circuit 145 may effectively determine the signal and noise characteristics 139 as a by-product of performing a read operation in accordance with a command from the controller 115 of the memory subsystem 110.

In general, for an optimized read voltage V _O May be stored in a memoryWithin the device 130 or performed by the controller 115 of the memory subsystem 110, which receives the signal and noise characteristics 139 as part of a rich status response from the memory device 130.

May be achieved by applying an optimized read voltage V across a group of memory cells _O And the memory cell is subjected to an optimized read voltage V _O The state of the memory cell is determined to obtain hard bit data 177.

Can be obtained by applying a slave optimized read voltage V _O The read voltages 181 and 182 are offset by a predetermined amount to obtain soft bit data 173. For example, the read voltage 181 is at a ratio of the optimized read voltage V _O A low offset 183 by a predetermined amount; and the read voltage 182 is at a ratio of the optimized read voltage V _O High by the same predetermined amount of offset 184. The memory cells experiencing the read voltage 181 may have a different state than the memory cells experiencing the read voltage 182. Soft bit data 173 may include or indicate XOR results of data read from memory cells using read voltages 181 and 182. The XOR result shows whether the memory cell experiencing the read voltage 181 has the same state as the memory cell experiencing the read voltage 182.

Fig. 4-6 illustrate techniques for calculating an optimized read voltage from a count difference, according to one embodiment. The technique of fig. 4 to 6 is simplified for calculating an optimized read voltage V _O Such that the operations may be implemented using reduced computing power and/or circuitry.

May be based on the reference to test voltage V in FIG. 3 _A 、V _B 、V _C 、V _D And V _E The bit count and count difference shown perform the operations shown in fig. 4 to 6.

In FIG. 4, operation 201 is performed to compare two center count differences D _B And D _C 。

If D _B Greater than D _C It can be assumed that the minimum value can be at V _C To V _E On the upper half of the test voltage region in between. Thus, operation 203 is performed to difference the lower of the two center bit counts by the D _C With another adjacent person D _D A comparison is made.

If D _C Not greater than its other neighbor D _D D is then _C Not greater than its neighbor D _B And D _D . Thus, it can be inferred that the minimum value can be at the test voltage V _C And V is equal to _D Between them. Based on D _C Adjacent to it D _B And D _D The ratio between the differences of (a) may be determined for the optimized read voltage V using a technique similar to that shown in fig. 5 _O Is used for the estimation of the position of the object.

If D _C Greater than its other neighbor D _D It can be assumed that the minimum value can be at V _D And V is equal to _E In the highest test voltage interval between. Thus, based on closest approach to the test voltage V _D And V _E Count difference D of (2) _D And D _C May use techniques similar to those shown in FIG. 6 to determine the optimized read voltage V _O Is used for the estimation of the position of the object.

Similarly, if D _B Not greater than D _C It can be assumed that the minimum value can be at V _A To V _C On the lower half of the test voltage area in between. Thus, operation 205 is performed to difference the lower of the two center bit counts by the D _B With another adjacent person D _A A comparison is made.

If D _B Less than its other neighbor D _A D is then _B Not greater than its neighbor D _A And D _C . Thus, it can be inferred that the minimum value can be at the test voltage V _B And V is equal to _C Between them. Based on D _B Adjacent to it D _A And D _C The ratio between the differences of (2) may be determined for the optimized read voltage V using the technique shown in FIG. 5 _O Is used for the estimation of the position of the object.

If D _B Not smaller than its other neighbor D _A It can be assumed that the minimum value can be at V _A And V is equal to _B In the lowest test voltage interval between. Thus, based on closest approach to the test voltage V _A And V _B Count difference D of (2) _A And D _B May be determined for the optimized read voltage V using the technique shown in fig. 6 _O Is used for the estimation of the position of the object.

FIG. 5 shows when the center count difference D _B Not greater than its neighbor D _A And D _C When used to estimate the optimized read voltage V _O Is a position technique of the above-mentioned device.

Due to the count difference D _B Is at test voltage V _B And V _C Lower bit count C _B And C _C Thus estimating the optimized read voltage V _O Is positioned at V _B And V is equal to _C Voltage intervals or gaps between.

When counting the difference D from the center _B To its adjacent person D _A And D _C When the increments of (2) are substantially equal to each other, an optimized read voltage V is estimated _O At V _B And V is equal to _C At the midpoint between them.

Count difference D from center _B To its adjacent person D _A And D _C The ratio between the increasing amounts of (a) can be mapped into the test voltage V in logarithmic scale _B And V is equal to _C The division line dimension between.

For example, a ratio of 1 (D _A -D _B )/(D _C -D _B ) Mapped to test voltage V _B And V is equal to _C The location of the optimized read voltage at the midpoint between.

Ratio of 1/2 (D _A -D _B )/(D _C -D _B ) Mapped to test voltage V _B And V is equal to _C The location of the optimized read voltage at the midpoint between, toward V _B Offset by a fixed increment. For example, the increment may be V _B And V is equal to _C One tenth of the voltage gap between.

Similarly, a ratio of 1/4, 1/8 or 1/16 (D _A -D _B )/(D _C -D _B ) Mapped to test voltage V _B And V is equal to _C The location of the optimized read voltage at the midpoint between, toward V _B Offset by two, three or four increments. A ratio (D) of less than 1/16 _A -D _B )/(D _C -D _B ) Can be mapped to V _B The location of the optimized read voltage.

Similarly, a ratio of 1/2, 1/4, 1/8 or 1/16 (D _C -D _B )/(D _A -D _B ) Mapped to test voltage V _B And V is equal to _C The location of the optimized read voltage at the midpoint between, toward V _C Offset by one, two, three or four increments. A ratio (D) of less than 1/16 _C -D _B )/(D _A -D _B ) Can be mapped to V _C The location of the optimized read voltage.

The technique of FIG. 5 may be implemented by setting the rough estimate of the optimized read voltage at V _B (or V) _C ) And by according to the count difference D _B To count difference D _A An increment (D) _A -D _B ) And count difference D _B To count difference D _C An increment (D) _C -D _B ) Is applied by applying increments to adjust the coarse estimate. An increment in a logarithmic scale (D _C -D _B ) The fraction or multiple of (2) may be calculated by iteratively dividing by two or multiplying by two, which may be effectively implemented by a bit-wise left-shift or right-shift operation.

For example, the optimized voltage V may be _O Is set at the test voltage V _B Where it is located. Can be increased by an amount (D _A -D _B ) Can be obtained by combining (D) _C -D _B ) Is calculated by the displacement bits (D _C -D _B ) And/16. If (D) _A -D _B ) Is greater than (D) _C -D _B ) /16, V _B And V is equal to _C An increment of one tenth of the gap between can be added to the optimized voltage V _O Is used for the estimation of the estimated value of (a). Subsequently, (D) _A -D _B ) Can be obtained by combining (D) _C -D _B ) Shift bits of/16 (D _C -D _B ) And/8. If (D) _A -D _B ) Is greater than (D) _C -D _B ) V is/8 _B And V is equal to _C The same increment of one tenth of the gap between is further added to the optimized voltage V _O Is used for the estimation of the estimated value of (a). Similarly, the method of (D _A -D _B ) Sequentially with (D) _C -D _B )/4、(D _C -D _B )/2、(D _C -D _B )、(D _C -D _B )*2、(D _C -D _B )*4、(D _C -D _B ) Sum (D) _C -D _B ) 16, comparison. If (D) _A -D _B ) In comparison greater than (D _C -D _B ) Any of the scaled versions of (c), then the same delta is added to the estimate. After a series of comparisons, the resulting estimate can be used as the optimized voltage V _O 。

FIG. 6 shows the current side count difference D _A Less than the two count differences D below _B And D _C But one of its neighbors has not been measured (e.g., test voltage V _A And lower than V _A Count difference between another test voltage of (a) to estimate the optimized read voltage V _O Is a position technique of the above-mentioned device.

Due to the count difference D _A At a count difference of D _A 、D _B And D _C Is the lowest, thus estimating the optimized voltage V _O At a difference of from the count D _A In the corresponding test voltage interval gap. Due to the count difference D _A Is at test voltage V _A And V _B Lower count C _A And C _B Thus estimating the optimized read voltage V _O Is positioned at V _A And V is equal to _B Voltage intervals or gaps between.

In FIG. 6, at V _A And V is equal to _B Optimized read voltage V within a voltage interval or gap between _O Is based on the count difference D _A And D _B Is a ratio of (2). Ratio D in logarithmic scale _A /D _B Mapping to V _A And V is equal to _B Optimized read voltage V in between _O Is a linear distribution of (c).

For example, V _A And V is equal to _B The voltage interval or gap between can be divided into five equal increments. Can optimize the voltage V _O Is set at the test voltage V _B Where it is located. The count differences D can be sequentially calculated _A And count difference D _B Scaled versions (e.g. D _B 、D _B 2 and D _B And/4) comparing. If the count difference D _A Less than the count difference D in comparison _B Any of the scaled versions of (c), the estimate decreases towards the test voltage V _A Increment of movement.

FIG. 7 shows a method of calculating optimized read voltages for reading a group of memory cells, according to one embodiment. The method of fig. 7 may be performed by processing logic that may comprise hardware (e.g., processing devices, circuitry, dedicated logic, programmable logic, microcode, hardware of the device, integrated circuits, etc.), software/firmware (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method of fig. 7 is performed at least in part by processing logic in the controller 115 of fig. 1 or the memory device 130 of fig. 2. Although shown in a particular order or sequence, the sequence of processes may be modified unless otherwise specified. Thus, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Further, one or more processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

For example, the method of fig. 7 may be implemented in the computing system of fig. 1 having the memory device of fig. 2 and the signal-to-noise characteristics shown in fig. 3 by some of the operations shown in fig. 4-6.

At block 301, the memory device 130 is programmed at a plurality of test voltages (e.g., V _A 、V _B 、V _C 、V _D And V _E ) The group of memory cells (e.g., 131 or 133) in memory device 130 is read down.

At block 303, the read manager 113 determines the test voltages (e.g., V _A 、V _B 、V _C 、V _D And V _E ) Lower bit count (e.g., C _A 、C _B 、C _C 、C _D And C _E ). At a test voltage (e.g., V _A ) Each bit below counts (e.g., C _A ) The number of memory cells in a group (e.g., 131 or 133) that when at a test voltage (e.g., V _A ) The read is performed down, providing a predetermined bit value (e.g., 0 or 1).

At block 305, the read manager 113 calculates the proximity in the test voltageCount differences in bit counts of voltage pairs (e.g., D _A 、D _B 、D _C And D _D ). Adjacent pairs of voltages (e.g., V _A And V _B ) Each count difference of voltage intervals therebetween (e.g., D _A ) Is a bit count of the adjacent voltage pair (e.g., D _A And D _B ) The difference between them.

At block 307, the read manager 113 identifies the following: after the count difference (e.g., D _A 、D _B 、D _C And D _D ) In (e.g., D _A ) Not greater than at least two of the count differences (e.g., D _B And D _C ) And a first count difference (e.g., D _A ) With the at least two (e.g., D _B And D _C ) Is set at a voltage interval (e.g., V _B To V _C V (V) _C To V _D ) Voltage interval between (e.g. V _A To V _B )。

In response to such a situation, at block 309, read manager 113 bases the first count difference (e.g., D _A ) With a second count difference (e.g. D _B ) The ratio between determines a first count difference (e.g., D _A ) Voltage interval (e.g., V _A To V _B ) The optimized read voltage V _O Wherein the second count difference (e.g., D _B ) Having a first one of the at least two medium and/or count differences closest to the count difference (e.g., D _A ) Voltage interval (e.g., V _A To V _B ) Voltage interval (e.g., V _B To V _C )。

For example, the first count difference (e.g., D _A ) With a second count difference (e.g. D _B ) The logarithmic scale of the ratio between is mapped to a first count difference (e.g., D _A ) Voltage interval (e.g., V _A To V _B ) The optimized read voltage V _O Position (e.g., V _A ) With a second count difference (e.g. V _B ) Determining an optimized read voltage V by linear distribution of _O Is a position of (c).

For example, it can be made withoutDetermining a first count difference (e.g., D _A ) Voltage interval (e.g., V _A To V _B ) Optimized read voltage V within _O Is a position of (c).

For example, the read manager 113 may generate a first count difference (e.g., D _A ) And a second count difference (e.g., D _B ) Scaled versions of at least one of the above. The read manager 113 may determine the optimized read voltage V based on the comparison performed according to the scaled version _O Is a position of (c).

For example, the scaled version may be generated by a shift operation. For example, shifting the number one bit to the left can scale the number by a factor of two; and shifting the number one bit to the right can scale the number down by a factor of two. Thus, without performing a floating point operation, the scaled version may be scaled by a predetermined number of powers of two.

For example, a scaled version may be generated by iteratively scaling twice; and may be performed by subtracting the first count from (e.g., D _A ) And a second count difference (e.g., D _B ) The non-scaled one of (a) is compared with the scaled version in turn to determine the location of the optimized read voltage.

For example, for an optimized read voltage V _O The determination of the location of (c) may comprise: the position is first set to correspond to the first count difference (e.g., D _A ) Test voltage of voltage interval (e.g., V _A And V _B ) One of them; and adjusting the position by a predetermined amount in response to determining that a predetermined relationship between: first count difference (e.g., D _A ) And a second count difference (e.g., D _B ) One of the non-scaled versions, and a scaled version of the plurality of scaled versions.

For example, the read manager 113 first sets the position at the test voltage V _B Where the test voltage will be a first count difference D _A Voltage interval V of (2) _A To V _B With a second count difference D _B Is of (a)Interval of pressure V _B To V _C And (5) separating. The read manager 113 compares the first count difference D _A With a second count difference D _B A comparison is made.

In response to determining the first count difference D _A Less than the second count difference D _B The read manager 113 moves the location away from the second count difference D _B Voltage interval V of (2) _B To V _C Predetermined amount (e.g. voltage interval V _A To V _B One fifth of (a) of the total number of the components).

The read manager 113 compares the second count difference D _B Scale down by a factor of two to produce a scaled version of the second count difference (e.g., D _B /2), difference D of the first count _A A scaled version of the difference from the second count (e.g., D _B Comparing and in response to determining the first count difference D _A A scaled version (e.g., D _B 2) moving the position farther from the second count difference D _B Voltage interval V of (2) _B To V _C Predetermined amount (e.g. voltage interval V _A To V _B One fifth of (a) of the total number of the components).

D _A And D _B The comparison between/2 is equivalent to comparison D _A /D _B And 1/2, which can be obtained by comparing D _A *2 and D _B And instead is performed.

Subsequently, the read manager 113 may send D _B /2 is further scaled down by a factor of two to produce a further scaled version of the second count difference (e.g., D _B 4), and the first count difference D _A A further scaled version of the difference from the second count (e.g., D _B And/4) comparing. In response to determining the first count difference D _A A further scaled version (e.g., D _B /4) the read manager 113 further moves the position even further away from the second count difference D _B Voltage interval V of (2) _B To V _C Predetermined amount (e.g. voltage interval V _A To V _B One fifth of (a) of the total number of the components).

D _A And D _B The comparison between/4 is equivalent to comparison D _A /D _B And 1/4 by comparison with D _A *2 and D _B /2 or by comparison of D _A *4 and D _B And instead is performed.

A non-transitory computer storage medium may be used to store instructions for firmware of a memory subsystem (e.g., 113). The instructions, when executed by the controller 115 and/or the processing device 117, cause the controller 115, the processing device 117, and/or the separate hardware modules to perform the methods discussed above.

FIG. 8 illustrates an example machine of a computer system 400 within which a set of instructions for causing the machine to perform any one or more of the methods discussed herein may be executed. In some embodiments, computer system 400 may correspond to a host system (e.g., host system 120 of fig. 1) that includes, is coupled to, or utilizes a memory subsystem (e.g., memory subsystem 110 of fig. 1) or may be used to perform operations of read manager 113 (e.g., execute instructions to perform operations corresponding to read manager 113 described with reference to fig. 1-7). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the Internet. The machine may operate as a peer machine in a peer-to-peer (or decentralized) network environment or as a server or client machine in a cloud computing infrastructure or environment in the capacity of a server or client machine in a client-server network environment.

The machine may be a Personal Computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any such machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Furthermore, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

Example computer system 400 includes a processing device 402, a main memory 404 (e.g., read Only Memory (ROM), flash memory, dynamic Random Access Memory (DRAM) such as Synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), static Random Access Memory (SRAM), etc.), and a data storage system 418 in communication with each other via a bus 430, which may include multiple buses.

The processing device 402 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More particularly, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device 402 may also be one or more special purpose processing devices, such as an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), a network processor, or the like. The processing device 402 is configured to execute instructions 426 for performing the operations and steps discussed herein. Computer system 400 may further include a network interface device 408 to communicate via a network 420.

The data storage system 418 may include a machine-readable storage medium 424 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 426 or software embodying any one or more of the methods or functions described herein. The instructions 426 may also reside, completely or at least partially, within the main memory 404 and/or within the processing device 402 during execution thereof by the computer system 400, the main memory 404 and the processing device 402 also constituting machine-readable storage media. The machine-readable storage medium 424, the data storage system 418, and/or the main memory 404 may correspond to the memory subsystem 110 of fig. 1.

In one embodiment, instructions 426 include instructions to implement functionality corresponding to read manager 113 (e.g., read manager 113 described with reference to fig. 1-7). While the machine-readable storage medium 424 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. Accordingly, the term "machine-readable storage medium" shall be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, considered to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

The present disclosure also relates to apparatus for performing the operations herein. Such an apparatus may be specially constructed for the desired purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random Access Memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. The structure of a variety of these systems will be presented as set forth in the following description. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the disclosure as described herein.

The present disclosure may be provided as a computer program product or software which may include a machine-readable medium having stored thereon instructions which may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as read-only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory components, and the like.

In this specification, various functions and operations are described as being performed by or caused by computer instructions to simplify the description. However, those skilled in the art will recognize that such expressions are meant to be representative of the execution of computer instructions by one or more controllers or processors, e.g., microprocessors. Alternatively or in combination, the functions and operations may be implemented using dedicated circuitry, with or without software instructions, such as with Application Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs). Embodiments may be implemented using hardwired circuitry without software instructions or in combination with software instructions. Thus, the techniques are not limited to any specific combination of hardware circuitry and software nor to any particular source for the instructions executed by the data processing system.

In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. A memory device, comprising:

an integrated circuit package enclosing the memory device; and

a plurality of groups of memory cells formed on at least one integrated circuit die;

wherein in response to a command identifying a group of memory cells within the plurality of groups of memory cells, the memory device is configured to:

reading the group of memory cells at a plurality of test voltages;

determining bit counts at the test voltage, respectively, wherein each bit count at the test voltage identifies a number of memory cells in the group of memory cells that provide a predetermined bit value when read at the test voltage;

calculating count differences in the bit counts of adjacent ones of the test voltages, wherein each count difference in voltage interval between adjacent ones of the test voltages is a difference between bit counts of the adjacent voltage pairs;

Identifying a first count difference of not greater than at least two of the count differences among the count differences, wherein the first count difference has a voltage interval between two voltage intervals that is not at the at least two of the count differences; and is also provided with

The location of the optimized read voltage in the voltage intervals of the first count differences is determined based on a ratio between the first count differences and a second count difference having a voltage interval closest to the voltage interval of the first count differences of the at least two of the count differences.

2. The memory device of claim 1, wherein the location of the optimized read voltage is selected from a plurality of candidates over the voltage interval of the first count difference.

3. The memory device of claim 2, wherein the plurality of candidates are evenly distributed over the voltage interval of the first count difference.

4. The memory device of claim 3, wherein the plurality of candidates corresponds to a logarithmic distribution of the ratio between the first count difference and the second count difference.

5. The memory device of claim 2, wherein the memory device is configured to:

Scaling at least one of the first count difference and the second count difference to generate a scaled version; and is also provided with

The location of the optimized read voltage is selected from a plurality of candidates by comparing to the scaled version.

6. The memory device of claim 5, wherein the memory device is configured to scale the at least one of the first count difference and the second count difference by a bit-shifting operation.

7. The memory device of claim 6, wherein the memory device is configured to:

iteratively shifting a first one of the first count difference and the second count difference to generate a series of scaled versions;

comparing the series of scaled versions one by one with a second of the first count difference and the second count difference; and is also provided with

The position of the optimized read voltage is adjusted by a predetermined increment in response to any of the series of scaled versions meeting a predetermined relationship as compared to the second of the first count difference and the second count difference.

8. The memory device of claim 7, wherein the predetermined increment is one fifth of the voltage interval of the first count difference.

9. A method of operating a memory device, comprising:

reading a group of memory cells in the memory device at a plurality of test voltages;

10. The method of claim 9, wherein the location of the optimized read voltage is determined based on a linear distribution mapping a logarithmic scale of the ratio between the first count difference and the second count difference to the location of the optimized read voltage in the voltage interval of the first count difference.

11. The method of claim 10, wherein the location of an optimized read voltage is determined without performing a floating point number operation.

12. The method as recited in claim 10, further comprising:

generating a plurality of scaled versions of at least one of the first count difference and the second count difference; and

the plurality of scaled versions are compared to determine the location of the optimized read voltage.

13. The method of claim 12, wherein the plurality of scaled versions are generated by a shift operation.

14. The method of claim 12, wherein the plurality of scaled versions are scaled by a predetermined number of powers of two.

15. The method of claim 14, wherein the plurality of scaled versions are generated by iteratively scaling twice.

16. The method of claim 15, wherein the determination of the location of the optimized read voltage is based on comparing an un-scaled one of the first count difference and the second count difference to the plurality of scaled versions.

17. The method of claim 15, wherein the determination of the location of the optimized read voltage includes:

initially setting the position at one of the test voltages corresponding to the voltage interval of the first count difference; and

adjusting the position by a predetermined amount in response to determining that a predetermined relationship is satisfied between:

one of the first count difference and the second count difference that is not scaled, and

a scaled version of the plurality of scaled versions.

18. A memory subsystem, comprising:

a processing device; and

at least one memory device having a group of memory cells formed on an integrated circuit die;

wherein the processing device is configured to transmit a command to the memory device having an address identifying the group of memory cells;

Wherein in response to the command, the memory device is configured to:

reading the group of memory cells at a plurality of test voltages;

comparing the count differences;

19. The memory subsystem of claim 18, wherein the location is determined based on a linear distribution of the locations over the voltage interval mapping a logarithmic scale of the ratio to the first count difference.

20. The memory subsystem of claim 19, wherein the memory device is configured to:

setting the position at a test voltage that separates the voltage interval of the first count difference from the voltage interval of the second count difference;

comparing the first count difference with the second count difference;

moving the position away from the voltage interval of the second count difference by a predetermined amount in response to determining that the first count difference is less than the second count difference;

scaling the second count difference by a factor of two to generate a scaled version of the second count difference;

comparing the scaled versions of the first count difference and the second count difference;

moving the position further from the voltage interval of the second count difference by the predetermined amount in response to determining that the first count difference is less than the scaled version of the second count difference;

Scaling the scaled version of the second count-up difference by a factor of two to generate another scaled version of the second count-up difference;

comparing the first count difference to the other scaled version of the second count difference; and is also provided with

The position is moved further from the voltage interval of the second count difference by the predetermined amount in response to determining that the first count difference is less than the other scaled version of the second count difference.