CN113628597A - GIP circuit architecture for improving discharge efficiency and driving method thereof - Google Patents
GIP circuit architecture for improving discharge efficiency and driving method thereof Download PDFInfo
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- CN113628597A CN113628597A CN202110990092.2A CN202110990092A CN113628597A CN 113628597 A CN113628597 A CN 113628597A CN 202110990092 A CN202110990092 A CN 202110990092A CN 113628597 A CN113628597 A CN 113628597A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
Abstract
The invention discloses a GIP circuit architecture for improving discharge efficiency and a driving method thereof. According to the GIP circuit power-off time sequence, the GIP level brush black mode is changed into the GIP Gate full-pull High mode, so that the discharge time is prolonged, the discharge efficiency is improved, and redundant charges existing in the surface can be effectively released.
Description
Technical Field
The invention relates to the field of LCD (liquid crystal display) screens, in particular to a GIP (gate in-phase) circuit architecture for improving discharge efficiency and a driving method thereof.
Background
The display of the liquid crystal display panel is completed by controlling the in-plane pixel TFT, specifically, the on and off of the TFT is controlled by a transverse grid signal (Gate) and the writing of a longitudinal Source signal (Source) into the data to be displayed is realized. The gate signals are generated by gate driving circuits on both sides of the panel, which are abbreviated as gip (gate In panel) driving circuits. The vertical source signal is supplied by the IC with a corresponding voltage according to the desired display. The GIP driving circuit design and driving have a large influence on the reliability and display quality of the panel. Such as: when the GIP circuit is normally driven, the charges in the plane do directional movement under the action of the driving voltage and cannot be separated from the control; however, when the GIP driving circuit stops working, there are a lot of parasitic capacitances in the panel itself, and if there is no good driving, there are a lot of uncontrolled charges in the panel that will be stored in these parasitic capacitances, which will affect the stability of the device and the display effect of the liquid crystal panel.
In the conventional 7T2C GIP circuit design, VGH is high, VGL is low, CK is the clock signal, and Gn is the output, as shown in fig. 1. T1-T7 are TFT devices, and C1 and C2 are capacitors. VGH, VSS and CK are input signals of the GIP, and Gn-4, Gn +4 and Gn are level transfer signals output by the GIP and used for controlling the pixel TFT.
As shown in fig. 2, when the GIP circuit is powered down, the timing of the input and output of each stage is determined. In general, in an a-Si thin film field effect transistor LCD, when power is prepared to be off when display is completed, a GIP is turned on step by step, and signals S1-Sn output by an IC output 0V are sent to the surface for discharging.
The thin film field effect transistor made of the metal oxide has excellent electron migration rate which is 20-30 times that of the a-Si thin film field effect transistor. The thin film field effect transistor made of the metal oxide has a good effect of storing charges, namely when the thin film field effect transistor is in an off state, electrons are difficult to leak out of the device, the characteristic can enable the GIP circuit to have a better charging effect, meanwhile, when the GIP circuit is turned off, in-plane charges are difficult to leak out, and charges stored in parasitic capacitors in the plane easily affect the performance of a panel. As shown in fig. 3, when the GIP circuit of the metal oxide is turned off, the input/output timing of each stage is determined by the above-mentioned black-out brush method due to the extremely low leakage characteristic of the metal oxide, and when the black-out time is short, charges may remain in the in-plane parasitic capacitance, which affects the display performance of the metal oxide panel, such as the flicker of the screen.
Disclosure of Invention
The invention aims to provide a GIP circuit architecture for improving discharge efficiency and a driving method thereof.
The technical scheme adopted by the invention is as follows:
a GIP circuit architecture for improving discharge efficiency comprises a plurality of GIP circuit units, wherein an output end of each GIP circuit unit is connected with an output end of a corresponding transistor Tn, an input end of the corresponding transistor Tn of the GIP circuit unit is connected with Sk, a control end of the corresponding transistor Tn of the GIP circuit unit is connected with Gk, the Gk is a gate control signal of the transistor Tn, the Sk is a Source end input signal of the transistor Tn, and the internal TFT is discharged under the common control of the Gk and the Sk.
Further, the GIP circuit cell is 7T 2C. Each GIP circuit unit includes capacitors C1, C2 and transistors T1, T2, T3, T4, T5, T6, T7,
the input end of the transistor T1 is connected with VGH, the output end of the transistor T1 is connected with VGL, and the control end of the transistor T1 is connected with Gn-4;
an input end of the transistor T2 is connected with CK through a capacitor C1, an input end of the transistor T2 is respectively connected with control ends of the transistor T3 and the transistor T6, and a control end of the transistor T2 is connected with VGL;
the input terminal of the transistor T3 is connected to VGL, the output terminal of the transistor T3 is connected to VGL,
the input end of the transistor T4 is connected with CK, the output end of the transistor T4 is respectively connected with the input ends of the transistor T5 and the transistor T6, the control end of the transistor T4 is respectively connected with one end of the capacitor C2 and VGL, the other end of the capacitor C2 is connected with the output end of the transistor T4 and the output end of the transistor T5, and then the output end of the GIP circuit unit is led out;
the control terminal of the transistor T5 is connected to CK, the output terminal of the transistor T5 is connected to VGL, the output terminal of the transistor T6 is connected to VGL,
the input end of the transistor T7 is connected with VGL, the output end of the transistor T7 is connected with VGL, and the control end of the transistor T7 is connected with Gn + 4;
VGH is direct current high voltage, VGL is direct current low voltage, CK is clock signal, Gn-4, Gn +4 are the class pass signal that GIP exported and is used for controlling pixel TFT.
Further, the transistor is a TFT thin film transistor.
Further, the transistor is provided on the display panel.
Further, the display panel is an LCD display panel.
Further, the display device further comprises sub-pixels, and the output end of each GIP circuit unit is connected with the sub-pixels.
Further, a driving IC is included, and CK, Gn-4 and Gn +4 are connected with the driving IC.
A driving method of a GIP circuit architecture for improving discharge efficiency is adopted, and the method comprises the following steps:
in the stage t1, VGH keeps high level, VGL keeps low level, CK writes low level, Gk, Sk writes low level; the output S1-Sn of the drive IC outputs high level;
in the stage t2, VGH keeps high level, VGL keeps low level, CK writes high level, Gk, Sk writes low level; the output S1-Sn of the drive IC outputs low level;
in the stage t3, VGH keeps high level, VGL keeps low level, CK writes high level, Gk, Sk writes low level; the output S1-Sn of the drive IC outputs high level;
in the stage t4, VGH keeps high level, VGL keeps low level, CK writes low level, Gk, Sk writes low level; the output S1-Sn of the drive IC outputs low level;
in the stage t5, VGH keeps high level, VGL keeps low level, CK writes low level, Gk, Sk writes low level; the output S1-Sn of the drive IC outputs high level;
in the stage t6, VGH keeps high level, VGL keeps low level, CK writes high level, Gk, Sk writes low level; the output S1-Sn of the drive IC outputs low level;
in the stage t7, VGH keeps high level, VGL keeps low level, CK writes high level, Gk, Sk writes low level; the output S1-Sn of the drive IC outputs high level;
in the stage t8, VGH keeps high level, VGL keeps low level, CK writes low level, Gk, Sk writes low level; the output S1-Sn of the drive IC outputs low level;
in the stage t9, VGH is reduced from high level to low level, VGL is increased from low level to high level, CK writes low level, and Gk and Sk write high level after short time delay; the output S1-Sn of the drive IC outputs low level;
in the stage t10, VGH keeps low level, VGL keeps high level, CK writes low level, Gk, Sk writes low level; the outputs S1-Sn of the driver IC output low levels.
Further, the t1 to t8 phases have the same duration, and the duration of the t9 phase is an integral multiple of any one of the t1 to t8 phases.
By adopting the technical scheme, the GIP circuit driving time sequence and the method can improve the discharge capacity of circuit charges in the opposite surface of the GIP circuit. The aging failure caused by the in-plane charge residual charge is reduced. According to the GIP circuit power-off time sequence, the GIP level brush-black mode is changed into the GIP Gate full-pull High mode, so that the discharge time is prolonged, the discharge efficiency is improved, and redundant charges existing in the surface can be effectively released.
Drawings
The invention is described in further detail below with reference to the accompanying drawings and the detailed description;
FIG. 1 is a schematic diagram of a prior art GIP circuit configuration;
FIG. 2 is a timing diagram of the input and output of each stage of the GIP circuit of the a-Si TFT during power-down;
FIG. 3 is a timing diagram of the input and output of each stage when the GIP circuit of metal oxide is turned off;
FIG. 4 is a schematic diagram of a GIP circuit architecture for improving the discharge efficiency according to the present invention;
FIG. 5 is a schematic diagram of a driving timing sequence of a GIP circuit architecture for improving the discharging efficiency according to the present invention;
FIG. 6 is a schematic diagram of the output timing obtained when the driving timing is powered down according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
As shown in fig. 4, the present invention discloses a GIP circuit architecture for improving discharge efficiency, which includes a plurality of GIP circuit units, wherein an output terminal of each GIP circuit unit is connected to an output terminal of a corresponding transistor Tn, an input terminal of the corresponding transistor Tn of the GIP circuit unit is connected to Sk, and a control terminal of the corresponding transistor Tn of the GIP circuit unit is connected to Gk.
Gk is a gate control signal of the transistor Tn, Sk is a Source terminal input signal of the transistor Tn, and the internal TFT is discharged under the common control of Gk and Sk.
Further, the GIP circuit cell is 7T 2C.
Further, each GIP circuit unit includes capacitors C1, C2 and transistors T1, T2, T3, T4, T5, T6, T7,
the input end of the transistor T1 is connected with VGH, the output end of the transistor T1 is connected with VGL, and the control end of the transistor T1 is connected with Gn-4;
an input end of the transistor T2 is connected with CK through a capacitor C1, an input end of the transistor T2 is respectively connected with control ends of the transistor T3 and the transistor T6, and a control end of the transistor T2 is connected with VGL;
the input terminal of the transistor T3 is connected to VGL, the output terminal of the transistor T3 is connected to VGL,
the input end of the transistor T4 is connected with CK, the output end of the transistor T4 is respectively connected with the input ends of the transistor T5 and the transistor T6, the control end of the transistor T4 is respectively connected with one end of the capacitor C2 and VGL, the other end of the capacitor C2 is respectively connected with the output end of the transistor T4 and the output end of the transistor T5, and the output ends of the transistor T4 and the transistor T5 are led out to serve as the output end of the GIP circuit unit;
the control terminal of the transistor T5 is connected to CK, the output terminal of the transistor T5 is connected to VGL, the output terminal of the transistor T6 is connected to VGL,
the input end of the transistor T7 is connected with VGL, the output end of the transistor T7 is connected with VGL, and the control end of the transistor T7 is connected with Gn + 4;
VGH is direct current high voltage, VGL is direct current low voltage, CK is clock signal, Gn-4, Gn +4 are the class pass signal that GIP exported and is used for controlling pixel TFT.
Further, the transistor is a TFT thin film transistor. The transistor is disposed on the display panel. The display panel is an LCD display panel.
Further, the display device further comprises sub-pixels, and the output end of each GIP circuit unit is connected with the sub-pixels.
Further, a driving IC is included, and CK, Gn-4 and Gn +4 are connected with the driving IC.
A driving method of a GIP circuit architecture for improving discharge efficiency is adopted, and the method comprises the following steps:
in the stage t1, VGH keeps high level, VGL keeps low level, CK writes low level, Gk, Sk writes low level; the output S1-Sn of the drive IC outputs high level;
in the stage t2, VGH keeps high level, VGL keeps low level, CK writes high level, Gk, Sk writes low level; the output S1-Sn of the drive IC outputs low level;
in the stage t3, VGH keeps high level, VGL keeps low level, CK writes high level, Gk, Sk writes low level; the output S1-Sn of the drive IC outputs high level;
in the stage t4, VGH keeps high level, VGL keeps low level, CK writes low level, Gk, Sk writes low level; the output S1-Sn of the drive IC outputs low level;
in the stage t5, VGH keeps high level, VGL keeps low level, CK writes low level, Gk, Sk writes low level; the output S1-Sn of the drive IC outputs high level;
in the stage t6, VGH keeps high level, VGL keeps low level, CK writes high level, Gk, Sk writes low level; the output S1-Sn of the drive IC outputs low level;
in the stage t7, VGH keeps high level, VGL keeps low level, CK writes high level, Gk, Sk writes low level; the output S1-Sn of the drive IC outputs high level;
in the stage t8, VGH keeps high level, VGL keeps low level, CK writes low level, Gk, Sk writes low level; the output S1-Sn of the drive IC outputs low level;
in the stage t9, VGH is reduced from high level to low level, VGL is increased from low level to high level, CK writes low level, and Gk and Sk write high level after short time delay; the output S1-Sn of the drive IC outputs low level;
in the stage t10, VGH keeps low level, VGL keeps high level, CK writes low level, Gk, Sk writes low level; the outputs S1-Sn of the driver IC output low levels.
Further, the periods t1 to t8 have the same duration, and may all be one pulse signal period, for example, the short time delay is one fourth of the duration of any period t1 to t8, that is, one fourth of the pulse signal period, and the duration of the period t9 is an integral multiple of any period t1 to t 8. As an embodiment, the duration of the t9 phase is 25 times that of any phase from t1 to t 8.
Specifically, as shown in fig. 5, the circuit driving method according to the present invention obtains a new circuit driving timing. Furthermore, the GIP circuit obtains the output timing sequence shown in FIG. 6 when the power is off, the GIP simultaneously pulls High output in one frame when the power is off, and the Source outputs S1-Sn perform the black brushing operation, taking the FHD resolution 1920 × 1080 as an example, the GIP level transfer discharge is compared with the GIP simultaneously pulling High. The GIP is adopted to simultaneously pull High, so that the GIP level is 1920 times of the GIP level transmission discharge, the discharge time is greatly prolonged, the discharge efficiency is improved, and residual charges are effectively discharged.
By adopting the technical scheme, the GIP circuit driving time sequence and the method can improve the discharge capacity of circuit charges in the opposite surface of the GIP circuit. The aging failure caused by the in-plane charge residual charge is reduced. According to the GIP circuit power-off time sequence, the GIP level brush-black mode is changed into the GIP Gate full-pull High mode, so that the discharge time is prolonged, the discharge efficiency is improved, and redundant charges existing in the surface can be effectively released.
It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. The embodiments and features of the embodiments in the present application may be combined with each other without conflict. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the detailed description of the embodiments of the present application is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Claims (10)
1. A GIP circuit architecture for improving discharge efficiency is characterized in that: the circuit comprises a plurality of GIP circuit units, wherein the output end of each GIP circuit unit is connected with the output end of a corresponding transistor Tn, the input end of the corresponding transistor Tn of the GIP circuit unit is connected with Sk, and the control end of the corresponding transistor Tn of the GIP circuit unit is connected with Gk; wherein, Gk is a gate control signal of the transistor Tn, Sk is a Source terminal input signal of the transistor Tn, and the internal TFT is discharged under the common control of Gk and Sk.
2. The GIP circuit architecture for improving discharging efficiency of claim 1, wherein: the GIP circuit cell is 7T 2C.
3. A GIP circuit architecture for improving discharge efficiency according to claim 1 or 2, wherein: each GIP circuit unit includes capacitors C1, C2 and transistors T1, T2, T3, T4, T5, T6, T7,
the input end of the transistor T1 is connected with VGH, the output end of the transistor T1 is connected with VGL, and the control end of the transistor T1 is connected with Gn-4;
an input end of the transistor T2 is connected with CK through a capacitor C1, an input end of the transistor T2 is respectively connected with control ends of the transistor T3 and the transistor T6, and a control end of the transistor T2 is connected with VGL;
the input terminal of the transistor T3 is connected to VGL, the output terminal of the transistor T3 is connected to VGL,
the input end of the transistor T4 is connected with CK, the output end of the transistor T4 is respectively connected with the input ends of the transistor T5 and the transistor T6, the control end of the transistor T4 is respectively connected with one end of the capacitor C2 and VGL, the other end of the capacitor C2 is respectively connected with the output end of the transistor T4 and the output end of the transistor T5, and the output ends of the transistor T4 and the transistor T5 are led out to serve as the output end of the GIP circuit unit;
the control terminal of the transistor T5 is connected to CK, the output terminal of the transistor T5 is connected to VGL, the output terminal of the transistor T6 is connected to VGL,
the input end of the transistor T7 is connected with VGL, the output end of the transistor T7 is connected with VGL, and the control end of the transistor T7 is connected with Gn + 4;
VGH is direct current high voltage, VGL is direct current low voltage, CK is clock signal, Gn-4, Gn +4 are the class pass signal that GIP exported and is used for controlling pixel TFT.
4. The GIP circuit architecture for improving discharging efficiency of claim 3, wherein: the transistor is a TFT thin film transistor.
5. The GIP circuit architecture for improving discharging efficiency of claim 1, wherein: the transistor is disposed on the display panel.
6. The GIP circuit architecture for improving discharging efficiency of claim 1, wherein: the display panel is an LCD display panel.
7. The GIP circuit architecture for improving discharging efficiency of claim 1, wherein: the display device further comprises sub-pixels, and the output end of each GIP circuit unit is connected with the sub-pixels.
8. The GIP circuit architecture for improving discharging efficiency of claim 1, wherein: comprises a driving IC, CK, Gn-4 and Gn +4 are connected with the driving IC.
9. A driving method of a GIP circuit architecture for improving discharge efficiency, which employs a GIP circuit architecture for improving discharge efficiency according to any one of claims 1 to 8, wherein: the method comprises the following steps:
in the stage t1, VGH keeps high level, VGL keeps low level, CK writes low level, Gk, Sk writes low level; the output S1-Sn of the drive IC outputs high level;
in the stage t2, VGH keeps high level, VGL keeps low level, CK writes high level, Gk, Sk writes low level; the output S1-Sn of the drive IC outputs low level;
in the stage t3, VGH keeps high level, VGL keeps low level, CK writes high level, Gk, Sk writes low level; the output S1-Sn of the drive IC outputs high level;
in the stage t4, VGH keeps high level, VGL keeps low level, CK writes low level, Gk, Sk writes low level; the output S1-Sn of the drive IC outputs low level;
in the stage t5, VGH keeps high level, VGL keeps low level, CK writes low level, Gk, Sk writes low level; the output S1-Sn of the drive IC outputs high level;
in the stage t6, VGH keeps high level, VGL keeps low level, CK writes high level, Gk, Sk writes low level; the output S1-Sn of the drive IC outputs low level;
in the stage t7, VGH keeps high level, VGL keeps low level, CK writes high level, Gk, Sk writes low level; the output S1-Sn of the drive IC outputs high level;
in the stage t8, VGH keeps high level, VGL keeps low level, CK writes low level, Gk, Sk writes low level; the output S1-Sn of the drive IC outputs low level;
in the stage t9, VGH is reduced from high level to low level, VGL is increased from low level to high level, CK writes low level, and Gk and Sk write high level after short time delay; the output S1-Sn of the drive IC outputs low level;
in the stage t10, VGH keeps low level, VGL keeps high level, CK writes low level, Gk, Sk writes low level; the outputs S1-Sn of the driver IC output low levels.
10. The driving method of GIP circuit architecture for improving discharging efficiency as claimed in claim 9, wherein: the t1 to t8 phases have the same duration, and the duration of the t9 phase is an integral multiple of any phase from t1 to t 8.
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| CN101188095A (en) * | 2007-12-20 | 2008-05-28 | 友达光电股份有限公司 | LCD and residual shadow attenuation method |
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Application publication date: 20211109 |