CN113626890B - Pin pin distribution structure and high-speed chip - Google Patents
Pin pin distribution structure and high-speed chip Download PDFInfo
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Abstract
The invention discloses a pin distribution structure and a high-speed chip, wherein pin rows are respectively corresponding to pin staggered distribution, two differential signal pin pairs are arranged at the same time, wherein two differential signal pin pairs of one differential signal pin pair are arranged in the same row, two differential signal pin pairs of the other differential signal pin pair are distributed in two adjacent rows, and the two differential signal pin pairs are distributed in a crossed manner, so that the two adjacent differential signal pin pairs are distributed at a certain angle, compared with the traditional parallel arrangement, the crosstalk is obviously improved, the signal integrity of a link is improved, the signal failure caused by crosstalk is avoided, the pin distribution space is reasonably utilized, and the cost waste caused by excessive involvement is avoided. The invention has simple and efficient structure and easy realization, and simultaneously increases the design reliability of the system.
Description
Technical Field
The invention relates to the field of pin distribution, in particular to a pin distribution structure and a high-speed chip.
Background
In the design of an Incloud server, especially in a PCIE5.0 high-speed signal interconnection topological link, as the signal rate increases, the density of boards increases, the thickness of a laminated board increases more and more, and in the design of a high-speed system link, how to achieve small volume and excellent performance becomes a target pursued by a designer.
For pin-distribution (i.e., pin map) designs of high-speed chips, the existing designs are generally distributed as shown in fig. 1, with TX signal pin and RX distribution pin being separated in different columns by a ground pin (i.e., GND pin), but there is no isolation ground pin between tx+ signal pin and TX-signal pin TX or between rx+ signal pin and RX-signal pin, because the addition of an isolation ground pin between tx+ signal pin and TX-signal pin TX or between rx+ signal pin and RX-signal pin in such a distribution greatly increases the size and cost of the chip.
Disclosure of Invention
In order to solve the problems, the invention provides a pin distributing structure and a high-speed chip, which reasonably utilize pin distributing space and reduce crosstalk.
In a first aspect, the present invention provides a pin distributing structure, including a plurality of rows of pin pins, where each pin in a previous row is staggered with a corresponding pin in a next adjacent row;
the pin pins comprise a grounding pin and a differential signal pin, wherein the differential signal pin comprises a positive differential signal pin and a negative differential signal pin, and a differential signal pin pair is formed by one positive differential signal pin and one negative differential signal pin;
the differential signal pin pair comprises a first differential signal pin pair and a second differential signal pin pair, wherein the two differential signal pin of the first differential signal pin pair are distributed in the same row, and the two differential signal pin of the second differential signal pin pair are distributed in two adjacent rows;
the structure is distributed with a plurality of first differential signal pin pairs and a plurality of second differential signal pin pairs, and the first differential signal pin pairs and the second differential signal pin pairs are arranged in a crossing way.
Further, the first differential signal pin pairs and the adjacent second differential signal pin pairs are distributed at an angle of 45 degrees.
Further, at least one differential signal pin is located in a row where the adjacent differential signal pin pair of the first type is located in two differential signal pin pairs of the second type.
Further, there is no ground pin between two differential signal pin pins of the first type of differential signal pin pins.
Further, for two differential signal pin pins of the second type differential signal pin pair, the differential signal pin of the upper row and one pin of the lower row and adjacent nearest pin pins form the second type differential signal pin pair.
Further, the first row pin pins are all grounding pin pins.
Further, the first pin at the left end of each of the other rows except the first row is a grounding pin.
Further, the differential signal pin is divided into an RX signal pin and a TX signal pin;
the RX signal pin comprises a positive RX signal pin and a negative RX signal pin, namely an RX+ signal pin and an RX-signal pin;
the TX signal pin comprises a positive TX signal pin and a negative TX signal pin, namely a TX+ signal pin and a TX-signal pin;
the first RX pin at one end of the structure is separated from the first TX pin at the other end by at least one row.
Further, the structure comprises six rows of pin pins, each row comprising seven pin pins;
the first pin and the third pin from the left side of the second row are RX+ signal pin, the second pin is RX-signal pin, and the rest pin of the row are grounding pin;
the fourth pin and the sixth pin from the left side of the third row are RX+ signal pin, the fifth pin and the seventh pin are RX-signal pin, and the rest pin of the row are grounding pin;
the second pin is a TX+ signal pin from the left side of the fourth row, the sixth pin is an RX-signal pin, and the rest pin of the row is a grounding pin;
the second pin and the fourth pin from the left side of the fifth row are TX-signal pin, the third pin and the fifth pin are TX+ signal pin, and the rest pin of the row is grounding pin;
the fourth and sixth pin pins from the left side of the sixth row are TX-signal pin pins, the fifth pin is tx+ signal pin, and the remaining pin pins of the row are ground pin pins.
In a second aspect, the present invention further provides a high-speed chip configured with the pin distribution structure of any one of the above embodiments.
Compared with the prior art, the pin distribution structure and the high-speed chip provided by the invention have the following beneficial effects: adjacent pin foot lines respectively correspond to pin foot staggered distribution, two differential signal pin foot pairs are arranged simultaneously, two differential signal pin feet of one differential signal pin foot pair are in the same line, two differential signal pin feet of the other differential signal pin foot pair are distributed in two adjacent lines, and the two differential signal pin foot pairs are distributed in a crossed mode, so that the two adjacent differential signal pin foot pairs are distributed at a certain angle, and compared with the traditional parallel arrangement side by side, crosstalk is obviously improved, signal integrity of a link is improved, signal failure caused by crosstalk is avoided, pin foot distribution space is reasonably utilized, and cost waste caused by related is avoided. The invention has simple and efficient structure and easy realization, and simultaneously increases the design reliability of the system.
Drawings
For a clearer description of embodiments of the present application or of the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description that follow are only some embodiments of the present application, and that other drawings may be obtained from these drawings by a person of ordinary skill in the art without inventive effort.
FIG. 1 is a schematic diagram of a conventional pin-foot distribution structure;
FIG. 2 is a schematic diagram of pin-foot distribution structure provided by the present invention;
fig. 3 is a schematic diagram showing pin distribution structure according to an embodiment of the present invention.
Detailed Description
The invention provides a pin distribution structure and a high-speed chip, wherein pin rows are respectively corresponding to pin staggered distribution, two differential signal pin pairs are arranged at the same time, wherein two differential signal pin pairs of one differential signal pin pair are arranged in the same row, two differential signal pin pairs of the other differential signal pin pair are distributed in two adjacent rows, and the two differential signal pin pairs are distributed in a crossed manner, so that the two adjacent differential signal pin pairs are distributed at a certain angle, pin distribution space is reasonably utilized, and crosstalk is reduced.
In order to provide a better understanding of the present application, those skilled in the art will now make further details of the present application with reference to the drawings and detailed description. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
Example 1
For pin-distribution (i.e., pin map) designs of high-speed chips, the existing designs are generally distributed as shown in fig. 1, with TX signal pin and RX distribution pin being separated in different columns by a ground pin (i.e., GND pin), but there is no isolation ground pin between tx+ signal pin and TX-signal pin TX or between rx+ signal pin and RX-signal pin, because the addition of an isolation ground pin between tx+ signal pin and TX-signal pin TX or between rx+ signal pin and RX-signal pin in such a distribution greatly increases the size and cost of the chip.
Therefore, this embodiment provides a pin foot distribution structure, makes adjacent pin foot line staggered distribution, and is certain angle between the adjacent differential signal pair, for traditional parallel distribution side by side, optimizes pin distribution space, reduces the crosstalk.
Fig. 2 is a schematic diagram of pin distribution structure provided in this embodiment, which includes multiple rows of pin pins, where each pin in a previous row is staggered with a corresponding pin in a next adjacent row, for example, a first pin in a second row is located between two pin pins in the first row.
The pin comprises a grounding pin and a differential signal pin, wherein the differential signal pin comprises a positive differential signal pin and a negative differential signal pin, and a differential signal pin pair is formed by the positive differential signal pin and the negative differential signal pin.
In order to realize that adjacent differential signal pin pairs are distributed at a certain angle, the differential signal pin pairs in the embodiment are two types, namely a first differential signal pin pair and a second differential signal pin pair. Wherein the two differential signal pin pins of the first differential signal pin pair are distributed in the same row, and the two differential signal pin pins of the second differential signal pin pair are distributed in two adjacent rows.
In addition, the structure is distributed with a plurality of first-type differential signal pin pairs and a plurality of second-type differential signal pin pairs, and the first-type differential signal pin pairs and the second-type differential signal pin pairs are arranged in a crossing mode.
Because the pin feet corresponding to the two adjacent rows of pin feet are distributed in a staggered manner, and meanwhile, the pin foot pairs of the first differential signal and the pin foot pairs of the second differential signal are distributed in a crossed manner, the pin foot pairs of the adjacent differential signals are not distributed in parallel side by side but are distributed in a certain angle, and compared with the traditional parallel side by side distribution, the pin foot distribution space can be obviously improved and optimized through simulation.
According to the pin distribution structure, pin rows are staggered and distributed respectively corresponding to pin, two differential signal pin pairs are arranged simultaneously, two differential signal pin pairs of one differential signal pin pair are arranged in the same row, two differential signal pin pairs of the other differential signal pin pair are distributed in two adjacent rows, and the two differential signal pin pairs are distributed in a crossed mode, so that the two adjacent differential signal pin pairs are distributed at a certain angle, the two differential signal pin pairs are distributed parallel to each other in parallel with the traditional side by side, crosstalk is obviously improved, signal integrity of a link is improved, signal failure caused by crosstalk is avoided, pin distribution space is reasonably utilized, and cost waste caused by the crosstalk is avoided. The invention has simple and efficient structure and easy realization, and simultaneously increases the design reliability of the system.
Example two
The embodiment provides a pin distribution structure, which enables adjacent pin rows to be distributed in a staggered manner, and a certain angle is formed between adjacent differential signal pairs, so that pin distribution space is optimized and crosstalk is reduced relative to traditional parallel distribution side by side.
Fig. 2 is a schematic diagram of pin distribution structure provided in this embodiment, which includes multiple rows of pin pins, where each pin in a previous row is staggered with a corresponding pin in a next adjacent row, for example, a first pin in a second row is located between two pin pins in the first row.
The pin comprises a grounding pin and a differential signal pin, wherein the differential signal pin comprises a positive differential signal pin and a negative differential signal pin, and a differential signal pin pair is formed by the positive differential signal pin and the negative differential signal pin.
In order to realize that adjacent differential signal pin pairs are distributed at a certain angle, the differential signal pin pairs in the embodiment are two types, namely a first differential signal pin pair and a second differential signal pin pair. Wherein the two differential signal pin pins of the first differential signal pin pair are distributed in the same row, and the two differential signal pin pins of the second differential signal pin pair are distributed in two adjacent rows.
In addition, the structure is distributed with a plurality of first-type differential signal pin pairs and a plurality of second-type differential signal pin pairs, and the first-type differential signal pin pairs and the second-type differential signal pin pairs are arranged in a crossing mode.
Because the pin feet corresponding to the two adjacent rows of pin feet are distributed in a staggered manner, and meanwhile, the pin foot pairs of the first differential signal and the pin foot pairs of the second differential signal are distributed in a crossed manner, the pin foot pairs of the adjacent differential signals are not distributed in parallel side by side but are distributed in a certain angle, and compared with the traditional parallel side by side distribution, the pin foot distribution space can be obviously improved and optimized through simulation.
According to the embodiment, the first differential signal pin pairs and the adjacent second differential signal pin pairs are distributed at 45 degrees, and through simulation, crosstalk can be avoided to a large extent. In fig. 2, two pin pins connected by a dotted line are a differential signal pin pair, a transverse dotted line is a first differential signal pin pair, an oblique dotted line is a second differential signal pin pair, and an angle of 45 degrees in this embodiment is an angle of 45 degrees between the transverse dotted line and the oblique dotted line.
In order to optimize pin distribution space, at least one differential signal pin is located in a row where an adjacent differential signal pin pair of the first type is located in two differential signal pin pairs of the second type. For the second type differential signal pin with the first type differential signal pin at two sides, the two differential signal pin are respectively positioned in the row corresponding to the first type differential signal pin, such as the first second type differential signal pin at the upper side in fig. 2. For the second type differential signal pin with the first type differential signal pin at one side, one of the differential signal pin is located in the row corresponding to the first type differential signal pin, such as the upper second type differential signal pin and the lower first differential signal pin in fig. 2.
In the structure of this embodiment, there is no ground pin between two differential signal pin pins of the first type differential signal pin, and in addition, for two differential signal pin pins of the second type differential signal pin pair, the differential signal pin of the upper row and one pin of the lower row and adjacent nearest pin form a second differential signal pin pair. It should be noted that, the second type differential signal pin pair is selected to be adjacent nearest pin, and the first type differential signal pin pair and the second type differential signal pin pair are guaranteed to be distributed at an angle of 45 degrees, at this time, two adjacent rows of pin pins are distributed in a staggered manner, specifically, pin pins of one row are located in the middle of two pin pins corresponding to the other row, as in fig. 2, the first pin of the second row is located in the middle of the first two pin pins of the first row, and the rest are similar. Note that the pitch between the pin pins in each row is uniform.
The structure of this embodiment makes the pin of first row all be the ground pin, and the pin of the first pin of the left end of each other row all is the ground pin except first row simultaneously, further reduces the crosstalk influence.
The differential signal pin is divided into an RX signal pin and a TX signal pin. The RX signal pin comprises a positive RX signal pin and a negative RX signal pin, namely an RX+ signal pin and an RX-signal pin; the TX signal pin pins include a positive TX signal pin and a negative TX signal pin, i.e., a tx+ signal pin and a TX-signal pin.
In this embodiment, the first RX pin at one end of the structure is separated from the first TX pin at the other end by at least one row, i.e. the RX pin and the TX pin are separated.
An embodiment of the pin distribution structure of the embodiment is shown in fig. 3.
The pin-foot distribution structure of this particular embodiment comprises six rows of pin-feet, each row comprising seven pin-feet.
The first row is the ground pin.
The first and third pin pins from the left side of the second row are RX+ signal pin pins, the second pin is RX-signal pin, and the rest pin pins of the row are grounding pin pins.
The fourth and sixth pin pins from the left side of the third row are RX+ signal pin pins, the fifth and seventh pin pins are RX-signal pin pins, and the rest pin pins of the row are ground pin pins.
The second pin from the left side of the fourth row is a TX+ signal pin, the sixth pin is an RX signal pin, and the rest pins in the row are grounding pins.
The second pin and the fourth pin from the left side of the fifth row are TX-signal pin, the third pin and the fifth pin are TX+ signal pin, and the rest pin of the row is grounding pin.
The fourth and sixth pin pins from the left side of the sixth row are TX-signal pin pins, the fifth pin is tx+ signal pin, and the remaining pin pins of the row are ground pin pins.
The cross-talk of the pin-foot distribution structure of this particular embodiment is, by simulation, significantly better than the conventional side-by-side parallel distribution.
According to the pin distribution structure, pin rows are staggered and distributed respectively corresponding to pin, two differential signal pin pairs are arranged simultaneously, two differential signal pin pairs of one differential signal pin pair are arranged in the same row, two differential signal pin pairs of the other differential signal pin pair are distributed in two adjacent rows, and the two differential signal pin pairs are distributed in a crossed mode, so that the two adjacent differential signal pin pairs are distributed at a certain angle, the two differential signal pin pairs are distributed parallel to each other in parallel with the traditional side by side, crosstalk is obviously improved, signal integrity of a link is improved, signal failure caused by crosstalk is avoided, pin distribution space is reasonably utilized, and cost waste caused by the crosstalk is avoided. The invention has simple and efficient structure and easy realization, and simultaneously increases the design reliability of the system.
Example III
The present embodiment provides a high-speed chip configured with the pin-out distribution structure of the first or second embodiment.
The high-speed chip of this embodiment is implemented based on the pin-distributing structure described above, so that the specific implementation of this device can be seen from the foregoing example part of the pin-distributing structure, and therefore, the specific implementation of this device can refer to the description of the corresponding examples of the respective parts, which will not be described herein.
In addition, since the high-speed chip of the present embodiment is implemented based on the pin distribution structure described above, the function corresponds to that of the above method, and will not be described here again.
In the description of the present invention, it should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "top," "bottom," "inner," "outer," and the like indicate or are based on the orientation or positional relationship shown in the drawings, merely to facilitate description of the present invention and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
The foregoing disclosure is merely illustrative of the preferred embodiments of the invention and the invention is not limited thereto, since modifications and variations may be made by those skilled in the art without departing from the principles of the invention.
Claims (8)
1. The pin distribution structure is characterized by comprising a plurality of rows of pin pins, wherein each pin in the upper row is staggered with each corresponding pin in the adjacent lower row;
the pin pins comprise a grounding pin and a differential signal pin, wherein the differential signal pin comprises a positive differential signal pin and a negative differential signal pin, and a differential signal pin pair is formed by one positive differential signal pin and one negative differential signal pin;
the differential signal pin pair comprises a first differential signal pin pair and a second differential signal pin pair, wherein the two differential signal pin of the first differential signal pin pair are distributed in the same row, and the two differential signal pin of the second differential signal pin pair are distributed in two adjacent rows;
the structure is provided with a plurality of first differential signal pin pairs and a plurality of second differential signal pin pairs, wherein the first differential signal pin pairs and the second differential signal pin pairs are arranged in a crossing way;
the differential signal pin is divided into an RX signal pin and a TX signal pin;
the RX signal pin comprises a positive RX signal pin and a negative RX signal pin, namely an RX+ signal pin and an RX-signal pin;
the TX signal pin comprises a positive TX signal pin and a negative TX signal pin, namely a TX+ signal pin and a TX-signal pin;
at least one row of the first RX signal pin at one end of the structure is separated from the first TX signal pin at the end;
the structure comprises six rows of pin feet, wherein each row comprises seven pin feet;
the second pin and the fourth pin are RX+ signal pin from the left side of the second row, the third pin is RX-signal pin, and the rest pin of the row is grounding pin;
the fifth pin and the seventh pin from the left side of the third row are RX+ signal pin, the fourth pin and the sixth pin are RX-signal pin, and the rest pin of the row are grounding pin;
the second pin is a TX+ signal pin from the left side of the fourth row, the sixth pin is an RX-signal pin, and the rest pin of the row is a grounding pin;
the second pin and the fourth pin from the left side of the fifth row are TX-signal pin, the third pin and the fifth pin are TX+ signal pin, and the rest pin of the row is grounding pin;
the fourth and sixth pin pins from the left side of the sixth row are TX-signal pin pins, the fifth pin is tx+ signal pin, and the remaining pin pins of the row are ground pin pins.
2. The pin-out arrangement according to claim 1, wherein the first type of differential signal pin pairs are distributed at 45 degrees to adjacent second type of differential signal pin pairs.
3. Pin-pin distribution structure according to claim 1 or 2, characterized in that at least one of the two differential signal pin pins of the differential signal pin pair of the second type is located in a row of the adjacent differential signal pin pair of the first type.
4. A pin profile structure according to claim 3, characterized in that there is no ground pin between two differential signal pin pins of the first type of differential signal pin pins.
5. The pin-out arrangement according to claim 4, wherein for two differential signal pin-out of the second differential signal pin-out pair, the differential signal pin-out of the upper row and one of the next row and its adjacent nearest pin-out constitute the second differential signal pin-out pair.
6. The pin profile structure of claim 5, wherein the first row of pin pins are all ground pin pins.
7. The pin-out distribution structure of claim 6, wherein the first pin at the left end of each of the rows except for the first row is a ground pin.
8. A high-speed chip, characterized in that a pin-distributing structure as claimed in any one of claims 1-7 is provided.
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| CN117293111B (en) * | 2023-11-24 | 2024-02-27 | 湖北芯擎科技有限公司 | V-shaped pin arrangement structure and high-speed differential signal chip |
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| CN109190269A (en) * | 2018-09-12 | 2019-01-11 | 郑州云海信息技术有限公司 | A method of cross talk effects at optimization PCIE PTH Connector |
| US10522949B1 (en) * | 2018-08-08 | 2019-12-31 | Qualcomm Incorporated | Optimized pin pattern for high speed input/output |
| CN212628549U (en) * | 2020-04-24 | 2021-02-26 | 苏州浪潮智能科技有限公司 | Connector with PCB fanout design framework |
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| US9514966B2 (en) * | 2014-04-11 | 2016-12-06 | Qualcomm Incorporated | Apparatus and methods for shielding differential signal pin pairs |
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| US10522949B1 (en) * | 2018-08-08 | 2019-12-31 | Qualcomm Incorporated | Optimized pin pattern for high speed input/output |
| CN109190269A (en) * | 2018-09-12 | 2019-01-11 | 郑州云海信息技术有限公司 | A method of cross talk effects at optimization PCIE PTH Connector |
| CN212628549U (en) * | 2020-04-24 | 2021-02-26 | 苏州浪潮智能科技有限公司 | Connector with PCB fanout design framework |
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