CN113626348A - Service execution method and device and electronic equipment - Google Patents
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Abstract
The embodiment of the specification provides a service execution method, a service execution device and electronic equipment, wherein in the service execution method, a processor starts to execute a service instruction in a first thread, and if data required by the service instruction in the first thread does not exist in a cache of the processor, a prefetch instruction is sent to a memory so as to read the data required by the service instruction in the first thread from the memory to the cache; before the cache receives the data required by the service instruction in the first thread, the processor switches the thread to the second thread, starts to execute the service instruction in the second thread, and if the data required by the service instruction in the second thread exists in the cache of the processor, reads the data required by the service instruction in the second thread from the cache and executes the service instruction in the second thread. In the method, after the processor sends the pre-fetching instruction to the memory, the CPU is switched to the second thread for execution, so that the CPU can execute at least two threads in parallel under the condition of no blockage, and the at least two threads run in parallel, thereby avoiding the performance loss caused by memory access and finally greatly improving the memory throughput capacity of the single-core CPU.
Description
[ technical field ] A method for producing a semiconductor device
The embodiment of the specification relates to the technical field of internet, in particular to a service execution method and device and electronic equipment.
[ background of the invention ]
Memory latency refers to a delay incurred while waiting for access to data stored in system memory to complete. At present, although moore's law has been developed, the memory throughput is seriously hindered due to slow memory latency increase.
Therefore, it is desirable to provide a scheme for avoiding performance loss caused by memory access and improving memory throughput.
[ summary of the invention ]
Embodiments of the present specification provide a method and an apparatus for executing a service, and an electronic device, so as to implement that synchronous access of a memory is changed into asynchronous access, and improve throughput of the memory.
In a first aspect, an embodiment of the present specification provides a service execution method, including: the processor starts to execute the service instruction in the first thread; if the data required by the service instruction in the first thread does not exist in the cache of the processor, the processor sends a pre-fetching instruction to the memory so as to read the data required by the service instruction in the first thread from the memory to the cache; before the cache receives data required by the service instruction in the first thread, the processor switches the thread to a second thread and starts to execute the service instruction in the second thread; and if the data required by the service instruction in the second thread exists in the cache of the processor, reading the data required by the service instruction in the second thread from the cache, and executing the service instruction in the second thread.
In the service execution method, after the processor sends the pre-fetch instruction to the memory, the CPU is switched to the second thread for execution, so that the CPU can execute at least two threads in parallel under the condition of no blockage, and the at least two threads run in parallel, thereby avoiding the performance loss caused by memory access and finally greatly improving the memory throughput capacity of the single-core CPU
In one possible implementation manner, after the processor switches a thread to a second thread and starts executing a service instruction in the second thread, the method further includes: if the data required by the service instruction in the second thread does not exist in the cache of the processor, the processor sends a prefetch instruction to the memory so as to read the data required by the service instruction in the second thread from the memory to the cache; before the cache receives data required by the service instruction in the second thread, the processor switches the thread to other threads except the second thread and starts to execute the service instruction in the other threads.
In one possible implementation manner, after the processor starts executing the service instruction in the first thread, the method further includes: and if the data required by the business instruction in the first thread exists in the cache of the processor, reading the data required by the business instruction in the first thread from the cache, and executing the business instruction in the first thread.
In one possible implementation manner, after the processor starts executing the service instruction in the first thread, the method further includes: judging whether data required by the service instruction in the first thread exists in a cache of the processor; after the starting of executing the service instruction in the second thread, the method further includes: and judging whether data required by the service instruction in the second thread exists in a cache of the processor.
In a second aspect, an embodiment of the present specification provides a service execution apparatus, which is disposed in a processor, and includes: the execution module is used for starting to execute the service instruction in the first thread; a sending module, configured to send a prefetch instruction to a memory when data required by the service instruction in the first thread does not exist in a cache of the processor, so as to read the data required by the service instruction in the first thread from the memory to the cache; the switching module is used for switching the thread to a second thread before the cache receives the data required by the service instruction in the first thread; the execution module is further configured to start executing the service instruction in the second thread, and when data required by the service instruction in the second thread exists in the cache of the processor, read the data required by the service instruction in the second thread from the cache, and execute the service instruction in the second thread.
In one possible implementation manner, the sending module is further configured to, after the switching module switches a thread to a second thread and starts to execute a service instruction in the second thread, send a prefetch instruction to the memory if data required by the service instruction in the second thread does not exist in a cache of the processor, so as to read the data required by the service instruction in the second thread from the memory to the cache; the switching module is further configured to switch the thread to another thread except the second thread before the cache receives data required by the service instruction in the second thread; the execution module is further configured to start executing the service instructions in the other threads.
In one possible implementation manner, after the execution of the service instruction in the first thread is started, if data required by the service instruction in the first thread exists in a cache of the processor, the execution module is further configured to read the data required by the service instruction in the first thread from the cache, and execute the service instruction in the first thread.
In one possible implementation manner, the apparatus further includes: the judging module is used for judging whether data required by the business instruction in the first thread exists in a cache of the processor after the executing module starts to execute the business instruction in the first thread; and after the execution module starts to execute the service instruction in the second thread, judging whether data required by the service instruction in the second thread exists in a cache of the processor or not.
In a third aspect, an embodiment of the present specification provides an electronic device, including: at least one processor; and at least one memory communicatively coupled to the processor, wherein: the memory stores program instructions executable by the processor, the processor calling the program instructions to be able to perform the method provided by the first aspect.
In a fourth aspect, embodiments of the present specification provide a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the method provided in the first aspect.
It should be understood that the second to fourth aspects of the embodiments of the present description are consistent with the technical solution of the first aspect of the embodiments of the present description, and similar beneficial effects are obtained in all aspects and corresponding possible implementation manners, and are not described again.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
FIG. 1 is a diagram illustrating a CPU executing instructions within a thread provided in the prior art;
fig. 2 is a flowchart of a service execution method provided in an embodiment of the present specification;
fig. 3 is a flowchart of a service execution method according to another embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a service execution device according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a service execution apparatus according to another embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of an electronic device provided in an embodiment of the present specification.
[ detailed description ] embodiments
For better understanding of the technical solutions in the present specification, the following detailed description of the embodiments of the present specification is provided with reference to the accompanying drawings.
It should be understood that the described embodiments are only a few embodiments of the present specification, and not all embodiments. All other embodiments obtained by a person skilled in the art based on the embodiments in the present specification without any inventive step are within the scope of the present specification.
The terminology used in the embodiments of the specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the specification. As used in the specification examples and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
Fig. 1 is a schematic diagram illustrating a Central Processing Unit (CPU) executing instructions in one thread according to the related art.
Referring to fig. 1, when the CPU accesses the memory and a cache miss occurs, the CPU must be idle waiting for data to arrive because the access to the memory is performed synchronously. The cache miss refers to that data required for executing the instruction is not found in the cache. In addition, the latency of accessing memory increases with increasing density (which can range from 50ns to 260ns), and this trend is still in progress, so although the frequency of the CPU is at 3GHz or even higher, this problem results in a large waste of CPU computing power. In most cases, developers completely know where a program is most likely to have cache miss according to the running condition, and meanwhile, the user-mode thread switching can be within 5ns, so that embodiments of the present specification provide a service execution method, a thread is generated in a software manner, a prefetch mode is used under the condition of cache miss, a prefetch instruction is issued before data is actually read, and then the thread is quickly switched to other threads, so that a CPU does not need to wait for the arrival of data, a plurality of threads can run in parallel to avoid performance loss caused by memory access, the throughput is finally greatly improved, and the memory access performance can be improved by 200% when data is displayed in a scene using the scheme.
Fig. 2 is a flowchart of a service execution method according to an embodiment of the present disclosure, and as shown in fig. 2, the service execution method may include:
at step 202, the processor begins executing the business instructions in the first thread.
In step 204, if the data required by the service instruction in the first thread does not exist in the cache of the processor, the processor sends a prefetch instruction to the memory to read the data required by the service instruction in the first thread from the memory to the cache.
Specifically, the prefetch instruction does not wait for data to return, and therefore does not block the CPU.
In step 206, before the cache receives the data required by the service instruction in the first thread, the processor switches the thread to the second thread to start executing the service instruction in the second thread.
And step 208, if the cache of the processor has the data required by the service instruction in the second thread, reading the data required by the service instruction in the second thread from the cache, and executing the service instruction in the second thread.
In this embodiment, after the processor sends the prefetch instruction to the memory, the processor switches to the second thread to execute, so that the CPU can execute at least two threads in parallel without blocking, thereby avoiding performance loss caused by memory access and greatly improving throughput of the memory.
Fig. 3 is a flowchart of a service execution method according to another embodiment of the present disclosure, and as shown in fig. 3, the service execution method may include:
at step 302, the processor begins executing the business instructions in the first thread.
In specific implementation, whether data required by the service instruction in the first thread exists in the cache of the processor can be judged by reading the register of the CPU.
In step 306, the processor issues a prefetch instruction to the memory to read data required by the service instruction in the first thread from the memory to the cache.
Specifically, the prefetch instruction does not wait for data to return, and therefore does not block the CPU.
In step 308, before the cache receives the data required by the service instruction in the first thread, the processor switches the thread to the second thread to start executing the service instruction in the second thread.
In specific implementation, whether data required by the service instruction in the second thread exists in the cache of the processor can be judged by reading the register of the CPU.
In a specific implementation, the data required by the service instruction in the second thread may be originally stored in the cache, or may be read from the memory into the cache by the processor through a prefetch instruction.
In this embodiment, after the processor sends the prefetch instruction to the memory, the CPU does not need to wait for the arrival of data, and directly switches to the second thread for execution, so that the CPU can execute at least two threads in parallel without blocking, and thus synchronous access of the memory can be changed into asynchronous access by user-mode thread switching, the memory throughput is greatly improved, and the throughput of the data display single-core CPU is improved by more than 200% to the maximum.
In step 314, the processor issues a prefetch instruction to the memory to read the data required by the service instruction in the second thread from the memory to the cache.
In step 316, before the cache receives the data required by the service instruction in the second thread, the processor switches the thread to another thread except the second thread, and starts to execute the service instruction in the other thread.
In a specific implementation, the other threads may be the first thread, that is, the processor may switch the thread back to the first thread before the cache receives the data required by the service instruction in the second thread, and perform step 302 and the subsequent steps.
In the service execution method, a processor starts to execute a service instruction in a first thread, and if data required by the service instruction in the first thread does not exist in a cache of the processor, a prefetch instruction is sent to a memory so as to read the data required by the service instruction in the first thread from the memory to the cache; before the cache receives the data required by the service instruction in the first thread, the processor switches the thread to the second thread, starts to execute the service instruction in the second thread, and if the data required by the service instruction in the second thread exists in the cache of the processor, reads the data required by the service instruction in the second thread from the cache and executes the service instruction in the second thread. In the method, after the processor sends the pre-fetching instruction to the memory, the CPU is switched to the second thread for execution, so that the CPU can execute at least two threads in parallel under the condition of no blockage, and the at least two threads run in parallel, thereby avoiding the performance loss caused by memory access and finally greatly improving the memory throughput capacity of the single-core CPU.
The foregoing description has been directed to specific embodiments of this disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.
Fig. 4 is a schematic structural diagram of a service execution device according to an embodiment of the present disclosure, and as shown in fig. 4, the service execution device may include: an execution module 41, a sending module 42 and a switching module 43;
the execution module 41 is configured to start executing a service instruction in a first thread;
a sending module 42, configured to send a prefetch instruction to the memory when data required by the service instruction in the first thread does not exist in the cache of the processor, so as to read the data required by the service instruction in the first thread from the memory to the cache;
a switching module 43, configured to switch a thread to a second thread before the cache receives data required by the service instruction in the first thread;
the execution module 41 is further configured to start executing the service instruction in the second thread, and when data required by the service instruction in the second thread exists in the cache of the processor, read the data required by the service instruction in the second thread from the cache, and execute the service instruction in the second thread.
The service execution apparatus provided in the embodiment shown in fig. 4 may be used to execute the technical solution of the method embodiment shown in fig. 2 in this specification, and the implementation principle and the technical effect may further refer to the related description in the method embodiment.
Fig. 5 is a schematic structural diagram of a service execution apparatus according to another embodiment of this specification, in comparison with the service execution apparatus shown in fig. 4, in the service execution apparatus shown in fig. 5, the sending module 42 is further configured to, after the switching module 43 switches the thread to the second thread and starts to execute the service instruction in the second thread, send a prefetch instruction to the memory if data required by the service instruction in the second thread does not exist in the cache of the processor, so as to read data required by the service instruction in the second thread from the memory to the cache;
the switching module 43 is further configured to switch the thread to another thread except the second thread before the cache receives the data required by the service instruction in the second thread;
the execution module 41 is further configured to start executing the service instruction in the other thread.
Further, the execution module 41 is further configured to, after starting to execute the business instruction in the first thread, if data required by the business instruction in the first thread exists in the cache of the processor, read the data required by the business instruction in the first thread from the cache, and execute the business instruction in the first thread.
Further, the service execution device may further include:
a judging module 44, configured to judge whether data required by the service instruction in the first thread exists in the cache of the processor after the execution module 41 starts executing the service instruction in the first thread; and after the execution module 41 starts to execute the service instruction in the second thread, determining whether data required by the service instruction in the second thread exists in the cache of the processor.
The service execution apparatus provided in the embodiment shown in fig. 5 may be used to execute the technical solutions of the method embodiments shown in fig. 2 to fig. 3 in this specification, and the implementation principle and the technical effect may further refer to the related descriptions in the method embodiments.
Fig. 6 is a schematic structural diagram of an electronic device provided in an embodiment of the present specification, where as shown in fig. 6, the electronic device may include at least one processor; and at least one memory communicatively coupled to the processor, wherein: the memory stores program instructions executable by the processor, and the processor calls the program instructions to execute the service execution method provided by the embodiments shown in fig. 2 to fig. 3 in the present specification.
The electronic device may be a server, for example: the cloud server or the electronic device may be a terminal device such as a Personal Computer (PC) or a notebook computer, and the form of the electronic device is not limited in this embodiment.
FIG. 6 illustrates a block diagram of an exemplary electronic device suitable for use in implementing embodiments of the present specification. The electronic device shown in fig. 6 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present specification.
As shown in fig. 6, the electronic device is in the form of a general purpose computing device. Components of the electronic device may include, but are not limited to: one or more processors 410, a communication interface 420, a memory 430, and a communication bus 440 that connects the various components (including the memory 430, the communication interface 420, and the processing unit 410).
Electronic devices typically include a variety of computer system readable media. Such media may be any available media that is accessible by the electronic device and includes both volatile and nonvolatile media, removable and non-removable media.
A program/utility having a set (at least one) of program modules, including but not limited to an operating system, one or more application programs, other program modules, and program data, may be stored in memory 430, each of which examples or some combination may include an implementation of a network environment. The program modules generally perform the functions and/or methods of the embodiments described in fig. 2-3 herein.
The processor 410 executes various functional applications and data processing by executing programs stored in the memory 430, for example, implementing the service execution method provided by the embodiments shown in fig. 2 to 3 in this specification.
The embodiments of the present specification provide a non-transitory computer-readable storage medium, which stores computer instructions, and the computer instructions cause the computer to execute the service execution method provided by the embodiments shown in fig. 2 to fig. 3 of the present specification.
The non-transitory computer readable storage medium described above may take any combination of one or more computer readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a Read Only Memory (ROM), an Erasable Programmable Read Only Memory (EPROM) or flash memory, an optical fiber, a portable compact disc read only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, Radio Frequency (RF), etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for aspects of the present description may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).
The foregoing description has been directed to specific embodiments of this disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.
In the description of the specification, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the specification. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present specification, "a plurality" means at least two, e.g., two, three, etc., unless explicitly defined otherwise.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing steps of a custom logic function or process, and alternate implementations are included within the scope of the preferred embodiment of the present description in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present description.
The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination" or "in response to a detection", depending on the context. Similarly, the phrases "if determined" or "if detected (a stated condition or event)" may be interpreted as "when determined" or "in response to a determination" or "when detected (a stated condition or event)" or "in response to a detection (a stated condition or event)", depending on the context.
It should be noted that the terminal referred to in the embodiments of the present specification may include, but is not limited to, a Personal Computer (PC), a Personal Digital Assistant (PDA), a wireless handheld device, a tablet computer (tablet computer), a mobile phone, an MP3 player, an MP4 player, and the like.
In the several embodiments provided in this specification, it should be understood that the disclosed system, apparatus, and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions in actual implementation, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
In addition, functional units in the embodiments of the present description may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
The integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device) or a processor (processor) to execute some steps of the methods described in the embodiments of the present disclosure. And the aforementioned storage medium includes: various media capable of storing program codes, such as a U disk, a removable hard disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The above description is only a preferred embodiment of the present disclosure, and should not be taken as limiting the present disclosure, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.
Claims (10)
1. A method of service execution, comprising:
the processor starts to execute the service instruction in the first thread;
if the data required by the service instruction in the first thread does not exist in the cache of the processor, the processor sends a pre-fetching instruction to the memory so as to read the data required by the service instruction in the first thread from the memory to the cache;
before the cache receives data required by the service instruction in the first thread, the processor switches the thread to a second thread and starts to execute the service instruction in the second thread;
and if the data required by the service instruction in the second thread exists in the cache of the processor, reading the data required by the service instruction in the second thread from the cache, and executing the service instruction in the second thread.
2. The method of claim 1, wherein the processor switching a thread to a second thread, after starting execution of the business instructions in the second thread, further comprising:
if the data required by the service instruction in the second thread does not exist in the cache of the processor, the processor sends a prefetch instruction to the memory so as to read the data required by the service instruction in the second thread from the memory to the cache;
before the cache receives data required by the service instruction in the second thread, the processor switches the thread to other threads except the second thread and starts to execute the service instruction in the other threads.
3. The method of claim 1, wherein after the processor begins executing the business instruction in the first thread, further comprising:
and if the data required by the business instruction in the first thread exists in the cache of the processor, reading the data required by the business instruction in the first thread from the cache, and executing the business instruction in the first thread.
4. The method of any of claims 1-3, wherein after the processor begins executing the business instruction in the first thread, further comprising:
judging whether data required by the service instruction in the first thread exists in a cache of the processor;
after the starting of executing the service instruction in the second thread, the method further includes:
and judging whether data required by the service instruction in the second thread exists in a cache of the processor.
5. A service execution apparatus, the apparatus comprising:
the execution module is used for starting to execute the service instruction in the first thread;
a sending module, configured to send a prefetch instruction to a memory when data required by the service instruction in the first thread does not exist in a cache of the processor, so as to read the data required by the service instruction in the first thread from the memory to the cache;
the switching module is used for switching the thread to a second thread before the cache receives the data required by the service instruction in the first thread;
the execution module is further configured to start executing the service instruction in the second thread, and when data required by the service instruction in the second thread exists in the cache of the processor, read the data required by the service instruction in the second thread from the cache, and execute the service instruction in the second thread.
6. The apparatus of claim 5, wherein,
the sending module is further configured to, after the switching module switches a thread to a second thread and starts executing a service instruction in the second thread, if data required by the service instruction in the second thread does not exist in a cache of the processor, send a prefetch instruction to the memory to read the data required by the service instruction in the second thread from the memory to the cache;
the switching module is further configured to switch the thread to another thread except the second thread before the cache receives data required by the service instruction in the second thread;
the execution module is further configured to start executing the service instructions in the other threads.
7. The apparatus of claim 5, wherein,
the execution module is further configured to, after the execution of the service instruction in the first thread is started, if data required by the service instruction in the first thread exists in the cache of the processor, read the data required by the service instruction in the first thread from the cache, and execute the service instruction in the first thread.
8. The apparatus of any of claims 5-7, further comprising:
the judging module is used for judging whether data required by the business instruction in the first thread exists in a cache of the processor after the executing module starts to execute the business instruction in the first thread; and after the execution module starts to execute the service instruction in the second thread, judging whether data required by the service instruction in the second thread exists in a cache of the processor or not.
9. An electronic device, comprising:
at least one processor; and
at least one memory communicatively coupled to the processor, wherein:
the memory stores program instructions executable by the processor, the processor invoking the program instructions to perform the method of any of claims 1 to 4.
10. A non-transitory computer-readable storage medium storing computer instructions that cause the computer to perform the method of any of claims 1-4.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0747816A2 (en) * | 1995-06-07 | 1996-12-11 | International Business Machines Corporation | Method and system for high performance multithread operation in a data processing system |
| CN1188932A (en) * | 1996-12-27 | 1998-07-29 | 国际商业机器公司 | Background completion of instruction and associated fetch request in multithread processor |
| US20050138627A1 (en) * | 2003-12-18 | 2005-06-23 | International Business Machines Corporation | Context switch data prefetching in multithreaded computer |
| US20060026594A1 (en) * | 2004-07-29 | 2006-02-02 | Fujitsu Limited | Multithread processor and thread switching control method |
| CN112925632A (en) * | 2021-05-08 | 2021-06-08 | 支付宝(杭州)信息技术有限公司 | Processing method and device, processor, electronic device and storage medium |
-
2021
- 2021-07-22 CN CN202110828917.0A patent/CN113626348A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0747816A2 (en) * | 1995-06-07 | 1996-12-11 | International Business Machines Corporation | Method and system for high performance multithread operation in a data processing system |
| CN1188932A (en) * | 1996-12-27 | 1998-07-29 | 国际商业机器公司 | Background completion of instruction and associated fetch request in multithread processor |
| US20050138627A1 (en) * | 2003-12-18 | 2005-06-23 | International Business Machines Corporation | Context switch data prefetching in multithreaded computer |
| US20060026594A1 (en) * | 2004-07-29 | 2006-02-02 | Fujitsu Limited | Multithread processor and thread switching control method |
| CN112925632A (en) * | 2021-05-08 | 2021-06-08 | 支付宝(杭州)信息技术有限公司 | Processing method and device, processor, electronic device and storage medium |
Non-Patent Citations (1)
| Title |
|---|
| 张延松;张宇;王珊;: "基于向量引用Platform-Oblivious内存连接优化技术", 软件学报, no. 03, 6 December 2017 (2017-12-06) * |
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