CN113626347B - Storage device and working method thereof - Google Patents
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- CN113626347B CN113626347B CN202110863032.4A CN202110863032A CN113626347B CN 113626347 B CN113626347 B CN 113626347B CN 202110863032 A CN202110863032 A CN 202110863032A CN 113626347 B CN113626347 B CN 113626347B
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000013507 mapping Methods 0.000 claims description 22
- 238000006243 chemical reaction Methods 0.000 claims description 10
- 238000010586 diagram Methods 0.000 description 14
- 101100397118 Arabidopsis thaliana PPA4 gene Proteins 0.000 description 9
- 230000015654 memory Effects 0.000 description 7
- OXXJZDJLYSMGIQ-ZRDIBKRKSA-N 8-[2-[(e)-3-hydroxypent-1-enyl]-5-oxocyclopent-3-en-1-yl]octanoic acid Chemical compound CCC(O)\C=C\C1C=CC(=O)C1CCCCCCCC(O)=O OXXJZDJLYSMGIQ-ZRDIBKRKSA-N 0.000 description 6
- 101001057699 Homo sapiens Inorganic pyrophosphatase Proteins 0.000 description 6
- 101000994880 Homo sapiens Inorganic pyrophosphatase 2, mitochondrial Proteins 0.000 description 6
- 102100027050 Inorganic pyrophosphatase Human genes 0.000 description 6
- 102100034415 Inorganic pyrophosphatase 2, mitochondrial Human genes 0.000 description 6
- 101100397117 Arabidopsis thaliana PPA3 gene Proteins 0.000 description 5
- 101001038001 Homo sapiens Lysophosphatidic acid receptor 2 Proteins 0.000 description 5
- 101001038043 Homo sapiens Lysophosphatidic acid receptor 4 Proteins 0.000 description 5
- 102100040387 Lysophosphatidic acid receptor 2 Human genes 0.000 description 5
- 102100040405 Lysophosphatidic acid receptor 4 Human genes 0.000 description 5
- 101001038037 Homo sapiens Lysophosphatidic acid receptor 5 Proteins 0.000 description 4
- 102100040404 Lysophosphatidic acid receptor 5 Human genes 0.000 description 4
- 101000966782 Homo sapiens Lysophosphatidic acid receptor 1 Proteins 0.000 description 3
- 102100040607 Lysophosphatidic acid receptor 1 Human genes 0.000 description 3
- 101100397119 Arabidopsis thaliana PPA5 gene Proteins 0.000 description 1
- 101100397120 Arabidopsis thaliana PPA6 gene Proteins 0.000 description 1
- 101100310155 Bacillus subtilis (strain 168) sfp gene Proteins 0.000 description 1
- 101001038006 Homo sapiens Lysophosphatidic acid receptor 3 Proteins 0.000 description 1
- 102100040388 Lysophosphatidic acid receptor 3 Human genes 0.000 description 1
- 101000882406 Staphylococcus aureus Enterotoxin type C-1 Proteins 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0615—Address space extension
- G06F12/0623—Address space extension for memory modules
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
Abstract
The application discloses a storage device and a working method thereof, belonging to the technical field of storage.
Description
Technical Field
The application relates to the technical field of storage, in particular to a storage device and a working method thereof.
Background
As shown in fig. 1, a user 1 typically accesses a storage device 2 directly using a physical address. The physical address direct access is independent of the specific access environment, i.e. the content in the storage device 2 can be accessed by the physical address in different environments.
When writing the physical address, the user 1 needs to directly manage the corresponding physical page state, i.e. judge whether the physical page is in a programmed state or an erased state, and then perform different operations according to different physical page states. However, as the upper limit of the storage capacity of the storage device 2 increases, the types of data that can be stored become more diversified, resulting in an increasingly difficult management work of the physical page status.
It should be noted that the above description of the background art is only for the purpose of facilitating a clear and complete understanding of the technical solution of the present application. Therefore, the technical solutions referred to above are not considered to be known to those skilled in the art, simply because they appear in the background of the application.
Disclosure of Invention
The application provides a storage device and a working method thereof, which are used for relieving the technical problem that the physical page state management is easy to be complicated when a physical address directly accesses the storage device.
In a first aspect, the present application provides a method for operating a storage device, including: receiving a logical page access address, wherein the logical page access address comprises a logical page address code; determining a physical page access address corresponding to the logical page access address based on the logical page access address, wherein the physical page access address comprises a physical page address code; and accessing the storage space corresponding to the physical page access address according to the physical page access address.
In some embodiments, the physical page address code includes an initial physical page address code and a target physical page address code, and determining the physical page access address corresponding to the logical page access address based on the logical page access address includes: determining an initial physical page address code corresponding to the logical page access address based on the mapping index relation; determining a physical page state corresponding to the initial physical page address code based on the state index relationship and the initial physical page address code; according to the physical page state corresponding to the initial physical page address code, maintaining the initial physical page address code or updating the initial physical page address code into the target physical page address code; and determining a physical page access address corresponding to the logical page access address based on the initial physical page address code or the target physical page address code.
In some embodiments, the physical page state includes an idle state, an active write state, and an inactive write state, and the step of maintaining the initial physical page address code or updating the initial physical page address code to the target physical page address code according to the physical page state corresponding to the initial physical page address code includes: when the storage device executes writing operation, determining a physical page state corresponding to the initial physical page address code; if the physical page state corresponding to the initial physical page address code is in an idle state, the initial physical page address code is kept unchanged.
In some embodiments, if the physical page state corresponding to the initial physical page address code is an idle state, the step of keeping the initial physical page address code unchanged further includes: determining a physical page access address corresponding to the initial physical page address code according to the initial physical page address code; writing the content to be stored into a storage space corresponding to the physical page access address based on the physical page access address corresponding to the initial physical page address code; and updating the physical page state corresponding to the initial physical page address code to be an effective writing state.
In some embodiments, the physical page state includes an idle state, an active write state, and an inactive write state, and the step of maintaining the initial physical page address code or updating the initial physical page address code to the target physical page address code according to the physical page state corresponding to the initial physical page address code includes: when the storage device executes writing operation, determining a physical page state corresponding to the initial physical page address code; if the physical page state corresponding to the initial physical page address code is the effective writing state, updating the initial physical page address code to be the target physical page address code, and if the physical page state corresponding to the target physical page address code is the idle state.
In some embodiments, if the physical page state corresponding to the initial physical page address code is the valid writing state, the step of updating the initial physical page address code to be the target physical page address code, and the physical page state corresponding to the target physical page address code to be the idle state includes: if the physical page state corresponding to the initial physical page address code is an effective writing state, searching a physical page access address corresponding to an idle state; determining a target physical page address code based on the physical page access address corresponding to the idle state; and updating the physical page state corresponding to the initial physical page address code to be an invalid writing state.
In some of these embodiments, the method of operation further comprises: determining a physical page address code corresponding to the logical page access address based on the mapping index relation; determining a physical page access address corresponding to the logical page access address based on a physical page address code corresponding to the logical page access address; and reading out the storage content corresponding to the physical page access address according to the physical page access address corresponding to the logical page access address.
In some of these embodiments, the method of operation further comprises: searching a physical page address code corresponding to the logical page access address based on the mapping index relation; if the physical page address code corresponding to the logical page access address is not found, determining the physical page access address corresponding to the physical page address code; and returning the read result: the physical page corresponding to the logical page access address is not described.
In some of these embodiments, the method of operation further comprises: inquiring a physical page state corresponding to the physical page access address, wherein the physical page state comprises an idle state and an invalid writing state; judging whether the physical page state is an invalid writing state or not; and if the physical page state is an invalid writing state, updating the physical page state corresponding to the physical page access address to be an idle state.
In a second aspect, the present application provides a storage apparatus, including a conversion device and a storage device, where the conversion device is configured to receive a logical page access address, and determine a physical page access address corresponding to the logical page access address based on the logical page access address, the logical page access address including a logical page address code, and the physical page access address including a physical page address code; the storage device is used for accessing the storage space corresponding to the physical page access address according to the physical page access address.
In some embodiments, the conversion device includes a first determining module, a second determining module, a processing module, and a third determining module, where the first determining module is configured to determine an initial physical page address code corresponding to the logical page access address based on the mapping index relationship; the second determining module is used for determining a physical page state corresponding to the initial physical page address code based on the state index relation and the initial physical page address code; the processing module is used for keeping the initial physical page address code or updating the initial physical page address code into the target physical page address code according to the physical page state corresponding to the initial physical page address code; the third determining module is used for determining a physical page access address corresponding to the logical page access address based on the initial physical page address code or the target physical page address code.
According to the storage device and the working method thereof, the logical page access address is converted into the corresponding physical page access address, and then the storage content is accessed, so that the storage content is prevented from being accessed directly through the physical address, management work of the physical page state is reduced or avoided, and the access flexibility and the access efficiency of the storage device are improved.
Drawings
The technical solution and other advantageous effects of the present application will be made apparent by the following detailed description of the specific embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of an access storage device according to a conventional technical scheme.
Fig. 2 is a flow chart of a working method of a storage device according to an embodiment of the present application.
FIG. 3 is a schematic diagram of a memory structure of multiple logical page access addresses according to an embodiment of the present application.
Fig. 4 is a schematic structural diagram of a physical page state according to an embodiment of the present application.
Fig. 5 is a schematic structural diagram of a mapping index relationship according to an embodiment of the present application.
FIG. 6 is a schematic diagram of a physical page access address storage and a physical page relationship structure according to an embodiment of the present application.
Fig. 7 is another schematic structural diagram of a mapping index relationship according to an embodiment of the present application.
Fig. 8 is a schematic structural diagram of a state index relationship according to an embodiment of the present application.
Fig. 9 is a schematic diagram of a first structure of a write operation according to an embodiment of the present application.
Fig. 10 is a schematic diagram of a second structure of a write operation according to an embodiment of the present application.
Fig. 11 is a schematic diagram of a third structure of a write operation according to an embodiment of the present application.
Fig. 12 is a fourth schematic diagram of a write operation according to an embodiment of the present application.
Fig. 13 is a schematic diagram of a fifth structure of a writing operation according to an embodiment of the present application.
Fig. 14 is a schematic structural diagram of a memory device according to an embodiment of the present application.
Fig. 15 is a schematic structural diagram of a conversion device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application.
Referring to fig. 2 to 15, as shown in fig. 2, the present embodiment provides a working method of a memory device, which includes the following steps:
step S100: a logical page access address is received, the logical page access address including a logical page address code.
Step S200: based on the logical page access address, a physical page access address corresponding to the logical page access address is determined, the physical page access address including a physical page address code.
Step S300: and accessing the storage space corresponding to the physical page access address according to the physical page access address.
It can be understood that, in the working method provided by this embodiment, by converting the logical page access address into the corresponding physical page access address and then accessing the storage content, it is possible to avoid directly accessing the storage content through the physical address, thereby reducing or avoiding the need to perform management work of the physical page state, and improving the access flexibility and the access efficiency of the storage device.
As shown in fig. 3, the logical page access address may be aligned with the physical page access address page to characterize the memory space of the memory device by the logical page access address, where one logical page access address may correspond to access to one physical page, and one physical page may be the minimum unit of access. The logical page access address may be a logical address, and the physical page access address may be a physical address. For example, a plurality of logical page access addresses may be defined as logical page access addresses LPA0 to LPA23 of 24 bits in total, which require three bytes of memory. The 24-bit logical page access addresses LPA0 to LPA23 can characterize a 4GB page address space. Wherein LPA is used to characterize the logical page address symbol, and numerals following LPA, e.g., "0", "23", etc., are used to characterize the corresponding logical page address code.
The storage device in this embodiment may be, but not limited to, a Nor Flash, but may also be other types of Flash memories, etc.
In one embodiment, the physical page address code includes an initial physical page address code and a target physical page address code, and the step of determining the physical page access address corresponding to the logical page access address based on the logical page access address includes: determining an initial physical page address code corresponding to the logical page access address based on the mapping index relation; determining a physical page state corresponding to the initial physical page address code based on the state index relationship and the initial physical page address code; according to the physical page state corresponding to the initial physical page address code, maintaining the initial physical page address code or updating the initial physical page address code into the target physical page address code; and determining a physical page access address corresponding to the logical page access address based on the initial physical page address code or the target physical page address code.
As shown in fig. 4, in one embodiment, the physical page states include an idle state, an active writing state, and an inactive writing state, and the step of maintaining the initial physical page address code or updating the initial physical page address code to the target physical page address code according to the physical page state corresponding to the initial physical page address code includes: when the storage device executes writing operation, determining a physical page state corresponding to the initial physical page address code; if the physical page state corresponding to the initial physical page address code is in an idle state, the initial physical page address code is kept unchanged.
It should be noted that, the physical page corresponding to the idle state description is not written in, and is to be selected and written in. The valid write state indicates that the corresponding physical page has written valid data. The invalid write state indicates that the corresponding physical page has written data, but the written data is already invalid, in a condition to be recycled. The three states of the physical page may be dynamically changed, for example, if the physical page in the idle state is selected to perform a write operation, the physical page in the idle state is correspondingly changed into a physical page in an effective write state; when the same logical page access address executes the writing operation again on the physical page in the effective writing state, the physical page in the effective writing state is changed into the physical page in the ineffective writing state; after the storage device performs reclamation processing on the physical page in the invalid writing state according to the existing reclamation algorithm and/or reclamation strategy, the physical page in the invalid writing state is changed into a physical page in an idle state.
Wherein "0" may be used to characterize the idle state. "1" may be used to characterize an active write state. "-1" can be used to characterize an invalid write state.
It will be appreciated that the state of the same physical page, i.e., the same physical page state, may be dynamically changed in response to the logical page access address, reducing or avoiding the need for a user to pay attention to the detailed state of the storage device when accessing with the physical page access address, e.g., performing management work on the physical page, etc.
As shown in fig. 5, the above mapping index relationship may be represented by one logical page access address corresponding to one physical page address code, for example, logical page access address LPA0 corresponding to physical page address code 0, logical page access address LPA1 corresponding to physical page address code 1, logical page access address LPA2 corresponding to physical page address code 2, logical page access address LPA3 corresponding to physical page address code 3, logical page access address LPA4 corresponding to physical page address code 4, logical page access address LPA5 corresponding to physical page address code 5, logical page access address LPA6 corresponding to physical page address code 6, logical page access address LPA7 corresponding to physical page address code 7, logical page access address LPA8 corresponding to physical page address code 8, logical page access address LPA9 corresponding to physical page address code 9, logical page access address LPAN corresponding to physical page address code M, and the like. Wherein PPA is used to characterize the physical page address.
Wherein M, N are integers, and M is greater than or equal to N.
In one embodiment, the logical page access address may also be represented by LPA N Z, where LPA may be used to represent a logical page address symbol, N is a logical head address, and Z is a data access length, so that batch access of the logical page access address may be implemented, and access efficiency may be improved. When receiving the logical page access address, the logical head address and the data access length can be sequentially and separately received. Where Z is an integer, for example, the logical page access address LPA4 1 indicates that the logical page access address LPA4 with the logical head address of 4 is required to be accessed this time, the logical page access address LPA4 2 indicates that two consecutive logical page access addresses with the logical head address of 4 are required to be accessed this time, i.e., LPA4 and LPA5, and for example, the logical page access address LPA5 3 indicates that three consecutive logical page access addresses with the logical head address of 5 are required to be accessed this time, i.e., LPA5, LPA6 and LPA7, and so on.
As shown in fig. 6, in one embodiment, the storage device may include a plurality of storage sectors, for example, storage sector SEC0, storage sector SEC1, and storage sector SECX, where X is a positive integer. These memory sectors are used to store corresponding physical page address codes.
Wherein one physical page address code corresponds to one physical page, for example, physical page address codes 0 to 9 correspond to physical pages P0 to P9 in order, and physical page address code M corresponds to physical page PM. In contrast, the physical page P15 may correspond to the physical page address code 15, the physical page address code 16, the physical page address code 18, or the like.
As shown in fig. 7, the mapping index relationship described above may also be expressed as that one logical page access address corresponds to one physical page address code, for example, logical page access addresses LPA0 to LPA9 sequentially correspond to physical page address codes 0 to 9, and logical page access address LPAN sequentially corresponds to physical page address code M.
As shown in fig. 8, the above state index relationship may be expressed as one physical page access address corresponding to one physical page state, for example, physical page access address PPA0 corresponding to physical page state Y, physical page access address PPA1 corresponding to physical page state Y, physical page access address PPA2 corresponding to physical page state Y, physical page access address PPA3 corresponding to physical page state Y, physical page access address PPA4 corresponding to physical page state Y, physical page access address PPA5 corresponding to physical page state Y, physical page access address PPA6 corresponding to physical page state Y, physical page access address PPA7 corresponding to physical page state Y, physical page access address PPA8 corresponding to physical page state Y, physical page access address PPA9 corresponding to physical page state Y, and physical page access address PPA m corresponding to physical page state Y, where Y may be any one of "-1", "0" and "1".
In one embodiment, if the physical page state corresponding to the initial physical page address code is an idle state, the step of keeping the initial physical page address code unchanged further includes: determining a physical page access address corresponding to the initial physical page address code according to the initial physical page address code; writing the content to be stored into a storage space corresponding to the physical page access address based on the physical page access address corresponding to the initial physical page address code; and updating the physical page state corresponding to the initial physical page address code to be an effective writing state.
In one embodiment, the physical page state includes an idle state, an active writing state, and an inactive writing state, and the step of maintaining the initial physical page address code or updating the initial physical page address code to the target physical page address code according to the physical page state corresponding to the initial physical page address code includes: when the storage device executes writing operation, determining a physical page state corresponding to the initial physical page address code; if the physical page state corresponding to the initial physical page address code is the effective writing state, updating the initial physical page address code to be the target physical page address code, and if the physical page state corresponding to the target physical page address code is the idle state.
In one embodiment, if the physical page state corresponding to the initial physical page address code is an effective writing state, the step of updating the initial physical page address code to be the target physical page address code and the physical page state corresponding to the target physical page address code to be an idle state includes: if the physical page state corresponding to the initial physical page address code is an effective writing state, searching a physical page access address corresponding to an idle state; determining a target physical page address code based on the physical page access address corresponding to the idle state; and updating the physical page state corresponding to the initial physical page address code to be an invalid writing state.
In one embodiment, the working method further comprises: determining a physical page address code corresponding to the logical page access address based on the mapping index relation; determining a physical page access address corresponding to the logical page access address based on a physical page address code corresponding to the logical page access address; and reading out the storage content corresponding to the physical page access address according to the physical page access address corresponding to the logical page access address.
In one embodiment, the working method further comprises: searching a physical page address code corresponding to the logical page access address based on the mapping index relation; if the physical page address code corresponding to the logical page access address is not found, determining the physical page access address corresponding to the physical page address code; and returning the read result: the physical page corresponding to the logical page access address is not described.
In one embodiment, the working method further comprises: inquiring a physical page state corresponding to the physical page access address, wherein the physical page state comprises an idle state and an invalid writing state; judging whether the physical page state is an invalid writing state or not; and if the physical page state is an invalid writing state, updating the physical page state corresponding to the physical page access address to be an idle state.
As shown in fig. 9, when performing a write operation, the storage device receives the logical page access address LPA0, finds that the physical page corresponding to the physical page access address PPA0 is in an idle state, writes data to the physical page corresponding to the physical page access address PPA0, rewrites the physical page address code PPA corresponding to the logical page access address LPA0 from a predetermined value "-1" to "0" based on the mapping index relationship described above, and rewrites the physical page state corresponding to the physical page access address PPA0 from "0" to "1" based on the state index relationship. Wherein, the preset value "-1" of the physical page address code PPA is different from the meaning represented by the "-1" of the physical page state.
It can be understood that, based on the above analysis, the storage device provided in this embodiment can automatically complete the writing operation shown in fig. 9, so that it can be seen that when the storage device is accessed by using the logical page access address, the physical page state can be automatically updated correspondingly, and the flexibility of access and the efficiency of access are effectively improved.
As shown in fig. 10, when performing a write operation, the storage device receives the logical page access address LPA1, finds that the physical page corresponding to the physical page access address PPA1 is in an idle state, writes data to the physical page corresponding to the physical page access address PPA1, rewrites the corresponding physical page address code PPA in the logical page access address LPA1 from a preset value "-1" to "1" based on the mapping index relationship described above, and rewrites the physical page state corresponding to the physical page access address PPA1 from "0" to "1" based on the state index relationship.
It can be understood that, based on the above analysis, the storage device provided in this embodiment can automatically complete the writing operation shown in fig. 10, so that it can be seen that when the storage device is accessed by using the logical page access address, the physical page state can be automatically updated correspondingly, and the flexibility of access and the efficiency of access are effectively improved.
As shown in fig. 11, when the storage device receives the logical page access address LPA0 for the second time and finds that the physical page corresponding to the physical page access address PPA2 is in the idle state, data is written to the physical page corresponding to the physical page access address PPA2, the corresponding physical page address code PPA in the logical page access address LPA0 is rewritten from "1" to "2" based on the above-mentioned mapping index relationship, and simultaneously, the physical page state corresponding to the physical page access address PPA2 is rewritten from "0" to "1" and the physical page state corresponding to the physical page access address PPA0 is rewritten from "1" to "-1" based on the state index relationship.
It can be understood that, based on the above analysis, the storage device provided in this embodiment can automatically complete the writing operation shown in fig. 11, so that it can be seen that when the storage device is accessed by using the logical page access address, the physical page state can be automatically updated correspondingly, and the flexibility of access and the efficiency of access are effectively improved.
As shown in fig. 12, when the storage device receives the logical page access address LPA2 and finds that the physical page corresponding to the physical page access address PPA3 is in an idle state, data is written to the physical page corresponding to the physical page access address PPA3, the corresponding physical page address code PPA in the logical page access address LPA2 is rewritten from a preset value "-1" to "3" based on the mapping index relationship, and the physical page state corresponding to the physical page access address PPA3 is rewritten from "0" to "1" based on the state index relationship.
It can be understood that, based on the above analysis, the storage device provided in this embodiment can automatically complete the writing operation shown in fig. 12, so that it can be seen that when the storage device is accessed by using the logical page access address, the physical page state can be automatically updated correspondingly, and the flexibility of access and the efficiency of access are effectively improved.
In another implementation, when the storage device receives the logical page access address LPA2 for the second time and finds that the physical page corresponding to the physical page access address PPA4 is in an idle state, writing data into the physical page corresponding to the physical page access address PPA4, and based on the mapping index relationship, rewriting the corresponding physical page address code PPA in the logical page access address LPA2 from "3" to "4", and simultaneously, based on the state index relationship, rewriting the physical page state corresponding to the physical page access address PPA4 from "0" to "1", and rewriting the physical page state corresponding to the physical page access address PPA2 from "1" to "-1". At this time, the physical page states corresponding to the physical page access address PPA0 and the physical page access address PPA2 are all invalid writing states, and the physical page states corresponding to the physical page access address PPA1 and the physical page access address PPA3 to the physical page access address PPA4 are all valid writing states.
As shown in fig. 13, when the storage device receives the logical page access address LPA0 for the third time and finds that the physical page corresponding to the physical page access address PPA4 is in the idle state, data is written to the physical page corresponding to the physical page access address PPA4, the corresponding physical page address code PPA in the logical page access address LPA0 is rewritten from "2" to "4" based on the above-mentioned mapping index relationship, and the physical page state corresponding to the physical page access address PPA4 is rewritten from "0" to "1" based on the state index relationship. At this time, the physical page state corresponding to the physical page access address PPA0 is an invalid writing state, and the physical page states corresponding to the physical page access addresses PPA1 to PPA4 are valid writing states.
It can be understood that, based on the above analysis, the storage device provided in this embodiment can automatically complete the writing operation shown in fig. 13, so that it can be seen that when the storage device is accessed by using the logical page access address, the physical page state can be automatically updated correspondingly, and the flexibility of access and the efficiency of access are effectively improved.
As shown in fig. 14, in one embodiment, the present embodiment provides a memory apparatus 1000, which includes a conversion device 100 and a memory device 200, the conversion device 100 being configured to receive a logical page access address, and determine a physical page access address corresponding to the logical page access address based on the logical page access address, the logical page access address including a logical page address symbol and a logical page address code, the physical page access address including a physical page address symbol and a physical page address code; the memory device 200 is configured to access a memory space corresponding to the physical page access address according to the physical page access address.
It can be appreciated that, in the storage device 1000 provided in this embodiment, by converting the logical page access address into the corresponding physical page access address and then accessing the storage content, it is possible to avoid directly accessing the storage content through the physical address, thereby reducing or avoiding the management work of the physical page state, and improving the access flexibility and the access efficiency of the storage device 1000.
It should be noted that the conversion device 100 and the memory device 200 may be electrically connected or communicatively connected. The logical page access address may be from a visitor to the storage device 1000, e.g., a user, etc.
As shown in fig. 15, in one embodiment, the conversion device 100 includes a first determining module 10, a second determining module 20, a processing module 30, and a third determining module 40, where the first determining module 10 is configured to determine an initial physical page address code corresponding to a logical page access address based on a mapping index relationship; the second determining module 20 is configured to determine a physical page state corresponding to the initial physical page address code based on the state index relationship and the initial physical page address code; the processing module 30 is configured to maintain the initial physical page address code or update the initial physical page address code to be the target physical page address code according to the physical page state corresponding to the initial physical page address code; the third determining module 40 is configured to determine a physical page access address corresponding to the logical page access address based on the initial physical page address code or the target physical page address code.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
The storage device and the working method thereof provided by the embodiment of the application are described in detail, and specific examples are applied to explain the principle and the implementation mode of the application, and the description of the above embodiment is only used for helping to understand the technical scheme and the core idea of the application; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.
Claims (10)
1. A method of operating a memory device, comprising:
receiving one or more logical page access addresses, the logical page access addresses comprising a logical page address code;
determining a physical page access address corresponding to the logical page access address based on the logical page access address, wherein the physical page access address comprises a physical page address code; and
accessing a storage space corresponding to the physical page access address according to the physical page access address;
the method comprises the steps of inquiring a physical page state corresponding to the physical page access address, wherein the physical page state comprises an idle state and an invalid writing state;
judging whether the physical page state is the invalid writing state or not; and
and if the physical page state is the invalid writing state, updating the physical page state corresponding to the physical page access address to be the idle state.
2. The method of claim 1, wherein the physical page address code includes an initial physical page address code and a target physical page address code, and wherein the step of determining the physical page access address corresponding to the logical page access address based on the logical page access address includes:
determining an initial physical page address code corresponding to the logical page access address based on the mapping index relation;
determining a physical page state corresponding to the initial physical page address code based on a state index relationship and the initial physical page address code;
according to the physical page state corresponding to the initial physical page address code, maintaining the initial physical page address code or updating the initial physical page address code into the target physical page address code; and
and determining a physical page access address corresponding to the logical page access address based on the initial physical page address code or the target physical page address code.
3. The method according to claim 2, wherein the physical page status further includes an active writing status, and the step of maintaining the initial physical page address code or updating the initial physical page address code to the target physical page address code according to the physical page status corresponding to the initial physical page address code includes:
when the storage device executes writing operation, determining a physical page state corresponding to the initial physical page address code;
and if the physical page state corresponding to the initial physical page address code is the idle state, keeping the initial physical page address code unchanged.
4. The method according to claim 3, wherein after the step of keeping the initial physical page address code unchanged if the physical page state corresponding to the initial physical page address code is the idle state, further comprising:
determining a physical page access address corresponding to the initial physical page address code according to the initial physical page address code;
writing the content to be stored into a storage space corresponding to the physical page access address based on the physical page access address corresponding to the initial physical page address code; and
and updating the physical page state corresponding to the initial physical page address code into the effective writing state.
5. The method according to claim 2, wherein the physical page status further includes an active writing status, and the step of maintaining the initial physical page address code or updating the initial physical page address code to the target physical page address code according to the physical page status corresponding to the initial physical page address code includes:
when the storage device executes writing operation, determining a physical page state corresponding to the initial physical page address code;
and if the physical page state corresponding to the initial physical page address code is the effective writing state, updating the initial physical page address code to be the target physical page address code, and if the physical page state corresponding to the target physical page address code is the idle state.
6. The method according to claim 5, wherein the step of updating the initial physical page address code to the target physical page address code if the physical page state corresponding to the initial physical page address code is the valid writing state, and the physical page state corresponding to the target physical page address code is the idle state, comprises:
if the physical page state corresponding to the initial physical page address code is the effective writing state, searching a physical page access address corresponding to an idle state;
determining the target physical page address code based on the physical page access address corresponding to the idle state;
and updating the physical page state corresponding to the initial physical page address code into the invalid writing state.
7. The method of operation of claim 1, further comprising:
determining a physical page address code corresponding to the logical page access address based on the mapping index relation;
determining a physical page access address corresponding to the logical page access address based on a physical page address code corresponding to the logical page access address; and
and reading out the storage content corresponding to the physical page access address according to the physical page access address corresponding to the logical page access address.
8. The method of operation of claim 1, further comprising:
searching a physical page address code corresponding to the logical page access address based on the mapping index relation;
if the physical page address code corresponding to the logical page access address is not found, determining the physical page access address corresponding to the physical page address code; and
returning the read result: and the physical page corresponding to the logical page access address is not recorded with content.
9. A memory device, comprising:
the conversion device is used for receiving a logic page access address and determining a physical page access address corresponding to the logic page access address based on the logic page access address, wherein the logic page access address comprises a logic page address symbol and a logic page address code, and the physical page access address comprises a physical page address symbol and a physical page address code; and
the storage device is used for accessing a storage space corresponding to the physical page access address according to the physical page access address;
the method comprises the steps of inquiring a physical page state corresponding to the physical page access address, wherein the physical page state comprises an idle state and an invalid writing state;
judging whether the physical page state is the invalid writing state or not; and
and if the physical page state is the invalid writing state, updating the physical page state corresponding to the physical page access address to be the idle state.
10. The memory device of claim 9, wherein the conversion means comprises:
the first determining module is used for determining an initial physical page address code corresponding to the logical page access address based on the mapping index relation;
the second determining module is used for determining a physical page state corresponding to the initial physical page address code based on a state index relation and the initial physical page address code;
the processing module is used for keeping the initial physical page address code or updating the initial physical page address code into a target physical page address code according to the physical page state corresponding to the initial physical page address code;
and the third determining module is used for determining the physical page access address corresponding to the logical page access address based on the initial physical page address code or the target physical page address code.
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| WO2007058617A1 (en) * | 2005-11-17 | 2007-05-24 | Chee Keng Chang | A controller for non-volatile memories, and methods of operating the memory controller |
| US8612718B2 (en) * | 2009-08-19 | 2013-12-17 | Seagate Technology Llc | Mapping alignment |
| CN107844431B (en) * | 2017-11-03 | 2022-01-25 | 合肥兆芯电子有限公司 | Mapping table updating method, memory control circuit unit and memory storage device |
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| CN101859279A (en) * | 2010-05-21 | 2010-10-13 | 北京星网锐捷网络技术有限公司 | Memory allocation and release method and device |
| CN102866955A (en) * | 2012-09-14 | 2013-01-09 | 记忆科技(深圳)有限公司 | Flash data management method and system |
| KR101936364B1 (en) * | 2017-08-09 | 2019-01-08 | 성균관대학교산학협력단 | Memory management system using flash memory and method thereof |
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